diff -r 37581bb7e6f1 linux/drivers/media/common/tuners/Kconfig --- a/linux/drivers/media/common/tuners/Kconfig Wed Feb 24 22:48:50 2010 -0300 +++ b/linux/drivers/media/common/tuners/Kconfig Sat Feb 27 16:17:22 2010 +0100 @@ -179,4 +179,11 @@ help A driver for the silicon tuner MAX2165 from Maxim. +config MEDIA_TUNER_TUA9001 + tristate "Infineon OMNITUNE TUA 9001 silicon tuner" + depends on VIDEO_MEDIA && I2C + default m if MEDIA_TUNER_CUSTOMISE + help + A driver for the silicon tuner OMNITUNE TUA 9001 from Infineon. + endif # MEDIA_TUNER_CUSTOMISE diff -r 37581bb7e6f1 linux/drivers/media/common/tuners/Makefile --- a/linux/drivers/media/common/tuners/Makefile Wed Feb 24 22:48:50 2010 -0300 +++ b/linux/drivers/media/common/tuners/Makefile Sat Feb 27 16:17:22 2010 +0100 @@ -23,6 +23,7 @@ obj-$(CONFIG_MEDIA_TUNER_MXL5005S) += mxl5005s.o obj-$(CONFIG_MEDIA_TUNER_MXL5007T) += mxl5007t.o obj-$(CONFIG_MEDIA_TUNER_MC44S803) += mc44s803.o +obj-$(CONFIG_MEDIA_TUNER_TUA9001) += tua9001.o obj-$(CONFIG_MEDIA_TUNER_MAX2165) += max2165.o EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core diff -r 37581bb7e6f1 linux/drivers/media/common/tuners/mxl5007t.c --- a/linux/drivers/media/common/tuners/mxl5007t.c Wed Feb 24 22:48:50 2010 -0300 +++ b/linux/drivers/media/common/tuners/mxl5007t.c Sat Feb 27 16:17:22 2010 +0100 @@ -375,7 +375,6 @@ mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if); mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz); - set_reg_bits(state->tab_init, 0x04, 0x01, cfg->loop_thru_enable); set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3); set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp); @@ -480,15 +479,21 @@ static int mxl5007t_write_regs(struct mxl5007t_state *state, struct reg_pair_t *reg_pair) { - unsigned int i = 0; - int ret = 0; + struct i2c_msg msg = { .addr = state->i2c_props.addr, .flags = 0, + .buf = (u8 *)reg_pair, .len = 0 }; + int ret; + int i = 0; - while ((ret == 0) && (reg_pair[i].reg || reg_pair[i].val)) { - ret = mxl5007t_write_reg(state, - reg_pair[i].reg, reg_pair[i].val); + while (reg_pair[i].reg || reg_pair[i].val) { i++; + msg.len += 2; } - return ret; + ret = i2c_transfer(state->i2c_props.adap, &msg, 1); + if (ret != 1) { + mxl_err("failed!"); + return -EREMOTEIO; + } + return 0; } static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val) @@ -865,6 +870,18 @@ /* check return value of mxl5007t_get_chip_id */ if (mxl_fail(ret)) goto fail; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + ret = mxl5007t_write_reg(state, 0x04, state->config->loop_thru_enable); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + /* check return value of mxl5007t_get_chip_id */ + if (mxl_fail(ret)) + goto fail; break; default: /* existing tuner instance */ diff -r 37581bb7e6f1 linux/drivers/media/common/tuners/mxl5007t.h --- a/linux/drivers/media/common/tuners/mxl5007t.h Wed Feb 24 22:48:50 2010 -0300 +++ b/linux/drivers/media/common/tuners/mxl5007t.h Sat Feb 27 16:17:22 2010 +0100 @@ -73,7 +73,7 @@ enum mxl5007t_xtal_freq xtal_freq_hz; enum mxl5007t_if_freq if_freq_hz; unsigned int invert_if:1; - unsigned int loop_thru_enable:1; + unsigned int loop_thru_enable:2; unsigned int clk_out_enable:1; }; diff -r 37581bb7e6f1 linux/drivers/media/common/tuners/tua9001.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/linux/drivers/media/common/tuners/tua9001.c Sat Feb 27 16:17:22 2010 +0100 @@ -0,0 +1,197 @@ +/* + * Infineon TUA 9001 silicon tuner driver + * + * Copyright (C) 2009 Antti Palosaari + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "tua9001.h" +#include "tua9001_priv.h" + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "debug"); + +/* write register */ +static int tua9001_writereg(struct tua9001_priv *priv, u8 reg, u16 val) +{ + u8 buf[3] = {reg, val >> 8, val & 0xff}; + struct i2c_msg msg = { .addr = priv->cfg->i2c_address, + .flags = 0, .buf = buf, .len = 3 }; + + if (i2c_transfer(priv->i2c, &msg, 1) != 1) { + err("I2C write failed, reg:%02x", reg); + return -EREMOTEIO; + } + return 0; +} + +static int tua9001_release(struct dvb_frontend *fe) +{ + kfree(fe->tuner_priv); + fe->tuner_priv = NULL; + return 0; +} + +static int tua9001_init(struct dvb_frontend *fe) +{ + struct tua9001_priv *priv = fe->tuner_priv; + int ret = 0; + u8 i; + struct regdesc data[] = { + {0x1e, 0x6512}, + {0x25, 0xb888}, + {0x39, 0x5460}, + {0x3b, 0x00c0}, + {0x3a, 0xf000}, + {0x08, 0x0000}, + {0x32, 0x0030}, + {0x41, 0x703a}, + {0x40, 0x1c78}, + {0x2c, 0x1c00}, + {0x36, 0xc013}, + {0x37, 0x6f18}, + {0x27, 0x0008}, + {0x2a, 0x0001}, + {0x34, 0x0a40}, + }; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c-gate */ + + for (i = 0; i < ARRAY_SIZE(data); i++) { + ret = tua9001_writereg(priv, data[i].reg, data[i].val); + if (ret) + break; + } + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c-gate */ + + if (ret) + deb_info("%s: failed:%d\n", __func__, ret); + + return ret; +} + +static int tua9001_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct tua9001_priv *priv = fe->tuner_priv; + int ret; + u16 val; + u8 i; + struct regdesc data[2]; + + switch (params->u.ofdm.bandwidth) { +#if 0 + case BANDWIDTH_5_MHZ: + val = 0x3000; + break; +#endif + case BANDWIDTH_6_MHZ: + val = 0x2000; + break; + case BANDWIDTH_7_MHZ: + val = 0x1000; + break; + case BANDWIDTH_8_MHZ: + default: + val = 0x0000; + break; + } + + data[0].reg = 0x04; + data[0].val = val; + +#define OFFSET 150000000 + val = 0.000048 * (params->frequency - OFFSET); + data[1].reg = 0x1f; + data[1].val = val; + + priv->frequency = (val * 20833.33334) + OFFSET; + + deb_info("%s: freq:%d bw:%d freq tuner:%d val:%d\n", __func__, + params->frequency, params->u.ofdm.bandwidth, priv->frequency, + val); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c-gate */ + + for (i = 0; i < ARRAY_SIZE(data); i++) { + ret = tua9001_writereg(priv, data[i].reg, data[i].val); + if (ret) + break; + } + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c-gate */ + + if (ret) + deb_info("%s: failed:%d\n", __func__, ret); + + return ret; +} + +static int tua9001_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct tua9001_priv *priv = fe->tuner_priv; + *frequency = priv->frequency; + return 0; +} + +static const struct dvb_tuner_ops tua9001_tuner_ops = { + .info = { + .name = "Infineon TUA 9001", + + .frequency_min = 170000000, + .frequency_max = 860000000, + .frequency_step = 0, + }, + + .release = tua9001_release, + .init = tua9001_init, + + .set_params = tua9001_set_params, + + .get_frequency = tua9001_get_frequency, +}; + +struct dvb_frontend * tua9001_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, struct tua9001_config *cfg) +{ + struct tua9001_priv *priv = NULL; + + priv = kzalloc(sizeof(struct tua9001_priv), GFP_KERNEL); + if (priv == NULL) + return NULL; + + priv->cfg = cfg; + priv->i2c = i2c; + + info("Infineon TUA 9001 successfully attached."); + + memcpy(&fe->ops.tuner_ops, &tua9001_tuner_ops, + sizeof(struct dvb_tuner_ops)); + + fe->tuner_priv = priv; + return fe; +} +EXPORT_SYMBOL(tua9001_attach); + +MODULE_DESCRIPTION("Infineon TUA 9001 silicon tuner driver"); +MODULE_AUTHOR("Antti Palosaari "); +MODULE_LICENSE("GPL"); diff -r 37581bb7e6f1 linux/drivers/media/common/tuners/tua9001.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/linux/drivers/media/common/tuners/tua9001.h Sat Feb 27 16:17:22 2010 +0100 @@ -0,0 +1,45 @@ +/* + * Infineon TUA 9001 silicon tuner driver + * + * Copyright (C) 2009 Antti Palosaari + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef TUA9001_H +#define TUA9001_H + +#include "dvb_frontend.h" + +struct tua9001_config { + u8 i2c_address; +}; + +#if defined(CONFIG_MEDIA_TUNER_TUA9001) || \ + (defined(CONFIG_MEDIA_TUNER_TUA9001_MODULE) && defined(MODULE)) +extern struct dvb_frontend *tua9001_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct tua9001_config *cfg); +#else +static inline struct dvb_frontend *tua9001_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct tua9001_config *cfg) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif + +#endif diff -r 37581bb7e6f1 linux/drivers/media/common/tuners/tua9001_priv.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/linux/drivers/media/common/tuners/tua9001_priv.h Sat Feb 27 16:17:22 2010 +0100 @@ -0,0 +1,53 @@ +/* + * Infineon TUA 9001 silicon tuner driver + * + * Copyright (C) 2009 Antti Palosaari + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef TUA9001_PRIV_H +#define TUA9001_PRIV_H + +#define LOG_PREFIX "tua9001" + +#define dprintk(var, level, args...) \ + do { \ + if ((var & level)) \ + printk(args); \ + } while (0) + +#define deb_info(args...) dprintk(debug, 0x01, args) + +#undef err +#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg) +#undef info +#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg) +#undef warn +#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg) + +struct regdesc { + u8 reg; + u16 val; +}; + +struct tua9001_priv { + struct tua9001_config *cfg; + struct i2c_adapter *i2c; + + u32 frequency; +}; + +#endif diff -r 37581bb7e6f1 linux/drivers/media/dvb/dvb-usb/Kconfig --- a/linux/drivers/media/dvb/dvb-usb/Kconfig Wed Feb 24 22:48:50 2010 -0300 +++ b/linux/drivers/media/dvb/dvb-usb/Kconfig Sat Feb 27 16:17:22 2010 +0100 @@ -323,6 +323,14 @@ help Say Y here to support the Intel CE6230 DVB-T USB2.0 receiver +config DVB_USB_AF9035 + tristate "Afatech AF9035 DVB-T USB2.0 support" + depends on DVB_USB + select DVB_AF9033 + select MEDIA_TUNER_TUA9001 if !MEDIA_TUNER_CUSTOMISE + help + Say Y here to support the Afatech AF9035 based DVB-T USB2.0 receiver + config DVB_USB_FRIIO tristate "Friio ISDB-T USB2.0 Receiver support" depends on DVB_USB diff -r 37581bb7e6f1 linux/drivers/media/dvb/dvb-usb/Makefile --- a/linux/drivers/media/dvb/dvb-usb/Makefile Wed Feb 24 22:48:50 2010 -0300 +++ b/linux/drivers/media/dvb/dvb-usb/Makefile Sat Feb 27 16:17:22 2010 +0100 @@ -88,6 +88,9 @@ dvb-usb-az6027-objs = az6027.o obj-$(CONFIG_DVB_USB_AZ6027) += dvb-usb-az6027.o +dvb-usb-af9035-objs = af9035.o +obj-$(CONFIG_DVB_USB_AF9035) += dvb-usb-af9035.o + EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/ -Idrivers/media/dvb/frontends/ # due to tuner-xc3028 EXTRA_CFLAGS += -Idrivers/media/common/tuners diff -r 37581bb7e6f1 linux/drivers/media/dvb/dvb-usb/af9035.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/linux/drivers/media/dvb/dvb-usb/af9035.c Sat Feb 27 16:17:22 2010 +0100 @@ -0,0 +1,1074 @@ +/* + * Afatech AF9035 DVB USB driver + * + * Copyright (C) 2008 Afatech + * Copyright (C) 2009 Antti Palosaari + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Thanks to TerraTec for a support received. + */ + +#include "af9035.h" +#include "af9033.h" +#include "tua9001.h" +#include "mxl5007t.h" + +static int dvb_usb_af9035_debug; +module_param_named(debug, dvb_usb_af9035_debug, int, 0644); +MODULE_PARM_DESC(debug, "set debugging level" DVB_USB_DEBUG_STATUS); +DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); + +static DEFINE_MUTEX(af9035_usb_mutex); + +static struct af9035_config af9035_config; +static struct dvb_usb_device_properties af9035_properties[1]; +static int af9035_properties_count = ARRAY_SIZE(af9035_properties); + +static struct af9033_config af9035_af9033_config[] = { + { + .demod_address = 0, + .tuner_address = 0, + .output_mode = AF9033_TS_MODE_USB, + }, { + .demod_address = 0, + .tuner_address = 0, + .output_mode = AF9033_TS_MODE_SERIAL, + } +}; + +static u8 regmask[8] = {0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff}; + +static int af9035_rw_udev(struct usb_device *udev, struct af9035_req *req) +{ +#define BUF_SIZE 63 + int act_len, ret; + u8 buf[BUF_SIZE]; + u32 msg_len; + static u8 seq; /* packet sequence number */ + u16 checksum = 0; + u8 i; + + /* buffer overflow check */ + if (req->wlen > (BUF_SIZE - 6) || req->rlen > (BUF_SIZE - 5)) { + err("too much data wlen:%d rlen:%d", req->wlen, req->rlen); + return -EINVAL; + } + + if (mutex_lock_interruptible(&af9035_usb_mutex) < 0) + return -EAGAIN; + + buf[0] = req->wlen + 3 + 2; /* 3 header + 2 checksum */ + buf[1] = req->mbox; + buf[2] = req->cmd; + buf[3] = seq++; + if (req->wlen) + memcpy(&buf[4], req->wbuf, req->wlen); + + /* calc and add checksum */ + for (i = 1; i < buf[0]-1; i++) { + if (i % 2) + checksum += buf[i] << 8; + else + checksum += buf[i]; + } + checksum = ~checksum; + + buf[buf[0]-1] = (checksum >> 8); + buf[buf[0]-0] = (checksum & 0xff); + + msg_len = buf[0]+1; + + deb_xfer(">>> "); + debug_dump(buf, msg_len, deb_xfer); + + /* send req */ + ret = usb_bulk_msg(udev, usb_sndbulkpipe(udev, 0x02), buf, msg_len, + &act_len, AF9035_USB_TIMEOUT); + if (ret) + err("bulk message failed:%d (%d/%d)", ret, msg_len, act_len); + else + if (act_len != msg_len) + ret = -EIO; /* all data is not send */ + if (ret) + goto error_unlock; + + /* no ack for those packets */ + if (req->cmd == CMD_FW_DOWNLOAD) + goto exit_unlock; + + /* receive ack and data if read req */ + msg_len = 3 + req->rlen + 2; /* data len + status + seq + checksum */ + ret = usb_bulk_msg(udev, usb_rcvbulkpipe(udev, 0x81), buf, msg_len, + &act_len, AF9035_USB_TIMEOUT); + if (ret) { + err("recv bulk message failed:%d", ret); + ret = -EIO; + goto error_unlock; + } + + deb_xfer("<<< "); + debug_dump(buf, act_len, deb_xfer); + + /* check status */ + if (buf[2]) { + err("command:%02x failed:%d", req->cmd, buf[2]); + ret = -EIO; + goto error_unlock; + } + + /* read request, copy returned data to return buf */ + if (req->rlen) + memcpy(req->rbuf, &buf[3], req->rlen); +error_unlock: +exit_unlock: + mutex_unlock(&af9035_usb_mutex); + + return ret; +} + +static int af9035_write_regs_bis(struct usb_device *d, u8 mbox, u16 reg, +u8 *val, u8 len) +{ + u8 wbuf[6+len]; + struct af9035_req req = {CMD_REG_DEMOD_WRITE, mbox, sizeof(wbuf), wbuf, + 0, NULL}; + wbuf[0] = len; + wbuf[1] = 2; + wbuf[2] = 0; + wbuf[3] = 0; + wbuf[4] = reg >> 8; + wbuf[5] = reg & 0xff; + memcpy(&wbuf[6], val, len); + return af9035_rw_udev(d, &req); +} + +static int af9035_write_regs(struct dvb_usb_device *d, u8 mbox, u16 reg, +u8 *val, u8 len) +{ + return af9035_write_regs_bis(d->udev, mbox, reg, val, len); +} + +static int af9035_read_regs_bis(struct usb_device *d, u8 mbox, u16 reg, u8 *val, + u8 len) +{ + u8 wbuf[] = {len, 2, 0, 0, reg >> 8, reg & 0xff}; + struct af9035_req req = {CMD_REG_DEMOD_READ, mbox, sizeof(wbuf), wbuf, + len, val}; + return af9035_rw_udev(d, &req); +} + +static int af9035_read_regs(struct dvb_usb_device *d, u8 mbox, u16 reg, u8 *val, + u8 len) +{ + return af9035_read_regs_bis(d->udev, mbox, reg, val, len); +} + +static int af9035_write_reg_bis(struct usb_device *d, u8 mbox, u16 reg, u8 val) +{ + return af9035_write_regs_bis(d, mbox, reg, &val, 1); +} + +static int af9035_write_reg(struct dvb_usb_device *d, u8 mbox, u16 reg, u8 val) +{ + return af9035_write_regs_bis(d->udev, mbox, reg, &val, 1); +} + +static int af9035_read_reg_bis(struct usb_device *d, u8 mbox, u16 reg, u8 *val) +{ + return af9035_read_regs_bis(d, mbox, reg, val, 1); +} + +static int af9035_write_reg_bits_bis(struct usb_device *d, u8 mbox, u16 reg, + u8 pos, u8 len, u8 val) +{ + int ret; + u8 tmp, mask; + + ret = af9035_read_reg_bis(d, mbox, reg, &tmp); + if (ret) + return ret; + + mask = regmask[len - 1] << pos; + tmp = (tmp & ~mask) | ((val << pos) & mask); + + return af9035_write_reg_bis(d, mbox, reg, tmp); +} + +static int af9035_write_reg_bits(struct dvb_usb_device *d, u8 mbox, u16 reg, + u8 pos, u8 len, u8 val) +{ + return af9035_write_reg_bits_bis(d->udev, mbox, reg, pos, len, val); +} + +static int af9035_read_reg_bits_bis(struct usb_device *d, u8 mbox, u16 reg, + u8 pos, u8 len, u8 *val) +{ + int ret; + u8 tmp; + + ret = af9035_read_reg_bis(d, mbox, reg, &tmp); + if (ret) + return ret; + *val = (tmp >> pos) & regmask[len - 1]; + return 0; +} + +static int af9035_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], + int num) +{ + struct dvb_usb_device *d = i2c_get_adapdata(adap); + int ret = 0, i = 0; + u16 reg; + u8 mbox; + + if (mutex_lock_interruptible(&d->i2c_mutex) < 0) + return -EAGAIN; + + while (i < num) { + mbox = msg[i].buf[0]; + reg = msg[i].buf[1] << 8; + reg += msg[i].buf[2]; + if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) { + if (msg[i].addr == + af9035_af9033_config[0].demod_address || + msg[i].addr == + af9035_af9033_config[1].demod_address) { + if (af9035_af9033_config[1].demod_address && (msg[i].addr == af9035_af9033_config[1].demod_address)) + mbox += 0x10; + ret = af9035_read_regs(d, mbox, reg, + &msg[i+1].buf[0], msg[i+1].len); + } else { + /* FIXME */ + u8 wbuf[5]; + u8 rbuf[BUF_SIZE]; + struct af9035_req req = {CMD_REG_TUNER_READ, + LINK, sizeof(wbuf), wbuf, msg[i + 1].len, + rbuf}; + if (af9035_af9033_config[1].tuner_address && + (msg[i].addr == af9035_af9033_config[1].tuner_address)) { + msg[i].addr = af9035_af9033_config[0].tuner_address; + req.mbox += 0x10; + } + wbuf[0] = msg[i + 1].len; /* read len */ + wbuf[1] = msg[i].addr; /* tuner i2c addr */ + wbuf[2] = 0x01; /* reg width */ + wbuf[3] = 0x00; /* reg MSB */ + wbuf[4] = msg[i].buf[0]; /* reg LSB */ + ret = af9035_rw_udev(d->udev, &req); + memcpy (msg[i + 1].buf, rbuf, msg[i + 1].len); + } + i += 2; + } else { + if (msg[i].addr == + af9035_af9033_config[0].demod_address || + msg[i].addr == + af9035_af9033_config[1].demod_address) { + if (af9035_af9033_config[1].demod_address && (msg[i].addr == af9035_af9033_config[1].demod_address)) + mbox += 0x10; + ret = af9035_write_regs(d, mbox, reg, + &msg[i].buf[3], msg[i].len-3); + } else { + u8 wbuf[BUF_SIZE]; + struct af9035_req req = {CMD_REG_TUNER_WRITE, + LINK, 4 + msg[i].len, wbuf, 0, NULL}; + if (af9035_af9033_config[1].tuner_address && + (msg[i].addr == af9035_af9033_config[1].tuner_address)) { + msg[i].addr = af9035_af9033_config[0].tuner_address; + req.mbox += 0x10; + } + wbuf[0] = msg[i].len - 1; /* write len */ + wbuf[1] = msg[i].addr; /* tuner i2c addr */ + wbuf[2] = 0x01; /* reg width */ + wbuf[3] = 0x00; /* reg MSB */ + memcpy (&wbuf[4], msg[i].buf, msg[i].len); + ret = af9035_rw_udev(d->udev, &req); + } + i += 1; + } + if (ret) + goto error; + + } + ret = i; +error: + mutex_unlock(&d->i2c_mutex); + + return ret; +} + +static u32 af9035_i2c_func(struct i2c_adapter *adapter) +{ + return I2C_FUNC_I2C; +} + +static struct i2c_algorithm af9035_i2c_algo = { + .master_xfer = af9035_i2c_xfer, + .functionality = af9035_i2c_func, +#ifdef NEED_ALGO_CONTROL + .algo_control = dummy_algo_control, +#endif +}; + +static int af9035_init_endpoint(struct dvb_usb_device *d) +{ + int ret; + u16 frame_size; + u8 packet_size; + + if (d->udev->speed == USB_SPEED_FULL) { + frame_size = TS_USB11_FRAME_SIZE/4; + packet_size = TS_USB11_MAX_PACKET_SIZE/4; + } else { + frame_size = TS_USB20_FRAME_SIZE/4; + packet_size = TS_USB20_MAX_PACKET_SIZE/4; + } + + deb_info("%s: USB speed:%d frame_size:%04x packet_size:%02x\n", + __func__, d->udev->speed, frame_size, packet_size); + + /* enable EP4 reset */ + ret = af9035_write_reg_bits(d, OFDM, p_reg_mp2_sw_rst, + reg_mp2_sw_rst_pos, reg_mp2_sw_rst_len, 1); + if (ret) + goto error; + + /* enable EP5 reset */ + ret = af9035_write_reg_bits(d, OFDM, p_reg_mp2if2_sw_rst, + reg_mp2if2_sw_rst_pos, reg_mp2if2_sw_rst_len, 1); + if (ret) + goto error; + + /* disable EP4 */ + ret = af9035_write_reg_bits(d, LINK, p_reg_ep4_tx_en, + reg_ep4_tx_en_pos, reg_ep4_tx_en_len, 0); + if (ret) + goto error; + + /* disable EP5 */ + ret = af9035_write_reg_bits(d, LINK, p_reg_ep5_tx_en, + reg_ep5_tx_en_pos, reg_ep5_tx_en_len, 0); + if (ret) + goto error; + + /* disable EP4 NAK */ + ret = af9035_write_reg_bits(d, LINK, p_reg_ep4_tx_nak, + reg_ep4_tx_nak_pos, reg_ep4_tx_nak_len, 0); + if (ret) + goto error; + + /* disable EP5 NAK */ + ret = af9035_write_reg_bits(d, LINK, p_reg_ep5_tx_nak, + reg_ep5_tx_nak_pos, reg_ep5_tx_nak_len, 0); + if (ret) + goto error; + + /* enable EP4 */ + ret = af9035_write_reg_bits(d, LINK, p_reg_ep4_tx_en, + reg_ep4_tx_en_pos, reg_ep4_tx_en_len, 1); + if (ret) + goto error; + + /* EP4 xfer length */ + ret = af9035_write_regs(d, LINK, p_reg_ep4_tx_len_7_0, + (u8 *) &frame_size, sizeof(frame_size)); + if (ret) + goto error; + + /* EP4 packet size */ + ret = af9035_write_reg(d, LINK, p_reg_ep4_max_pkt, packet_size); + if (ret) + goto error; + + /* configure EP5 for dual mode */ + if (af9035_config.dual_mode) { + /* enable EP5 */ + ret = af9035_write_reg_bits(d, LINK, p_reg_ep5_tx_en, + reg_ep5_tx_en_pos, reg_ep5_tx_en_len, 1); + if (ret) + goto error; + + /* EP5 xfer length */ + ret = af9035_write_regs(d, LINK, p_reg_ep5_tx_len_7_0, + (u8 *) &frame_size, sizeof(frame_size)); + if (ret) + goto error; + + /* EP5 packet size */ + ret = af9035_write_reg(d, LINK, p_reg_ep5_max_pkt, packet_size); + if (ret) + goto error; + } + + /* enable / disable mp2if2 */ + ret = af9035_write_reg_bits(d, OFDM, p_reg_mp2if2_en, + reg_mp2if2_en_pos, reg_mp2if2_en_len, af9035_config.dual_mode); + if (ret) + goto error; + + /* enable / disable tsis */ + ret = af9035_write_reg_bits(d, OFDM, p_reg_tsis_en, reg_tsis_en_pos, + reg_tsis_en_len, af9035_config.dual_mode); + if (ret) + goto error; + + /* negate EP4 reset */ + ret = af9035_write_reg_bits(d, OFDM, p_reg_mp2_sw_rst, + reg_mp2_sw_rst_pos, reg_mp2_sw_rst_len, 0); + if (ret) + goto error; + + /* negate EP5 reset */ + ret = af9035_write_reg_bits(d, OFDM, p_reg_mp2if2_sw_rst, + reg_mp2if2_sw_rst_pos, reg_mp2if2_sw_rst_len, 0); + if (ret) + goto error; + +error: + if (ret) + err("endpoint init failed:%d", ret); + return ret; +} + +static int af9035_init(struct dvb_usb_device *d) +{ + int ret; + deb_info("%s:\n", __func__); + + ret = af9035_init_endpoint(d); + if (ret) + goto error; +error: + return ret; +} + +static int af9035_download_firmware(struct usb_device *udev, + const struct firmware *fw) +{ + u8 *fw_data_ptr = (u8 *) fw->data; + int i, j, len, packets, remainder, ret; + u8 wbuf[1]; + u8 rbuf[4]; + struct af9035_firmware_header fw_hdr; + struct af9035_req req = {0, LINK, 0, NULL, 1, rbuf}; + struct af9035_req req_fw_dl = {CMD_FW_DOWNLOAD, LINK, 0, NULL, 0, NULL}; + struct af9035_req req_rom = {CMD_SCATTER_WRITE, LINK, 0, NULL, 1, rbuf}; + struct af9035_req req_fw_ver = {CMD_QUERYINFO, LINK, 1, wbuf, 4, rbuf}; + + /* read firmware segment info from beginning of the firmware file */ + fw_hdr.segment_count = *fw_data_ptr++; + deb_info("%s: fw segment count:%d\n", __func__, fw_hdr.segment_count); + if (fw_hdr.segment_count > SEGMENT_MAX_COUNT) { + warn("too big firmware segmen count:%d", fw_hdr.segment_count); + fw_hdr.segment_count = SEGMENT_MAX_COUNT; + } + for (i = 0; i < fw_hdr.segment_count; i++) { + fw_hdr.segment[i].type = (*fw_data_ptr++); + fw_hdr.segment[i].len = (*fw_data_ptr++) << 24; + fw_hdr.segment[i].len += (*fw_data_ptr++) << 16; + fw_hdr.segment[i].len += (*fw_data_ptr++) << 8; + fw_hdr.segment[i].len += (*fw_data_ptr++) << 0; + deb_info("%s: fw segment type:%d len:%d\n", __func__, + fw_hdr.segment[i].type, fw_hdr.segment[i].len); + } + + #define FW_PACKET_MAX_DATA 57 /* 63-4-2, packet_size-header-checksum */ + + /* download all segments */ + for (i = 0; i < fw_hdr.segment_count; i++) { + deb_info("%s: segment type:%d\n", __func__, + fw_hdr.segment[i].type); + if (fw_hdr.segment[i].type == SEGMENT_FW_DOWNLOAD) { + /* download begin packet */ + req.cmd = CMD_FW_DOWNLOAD_BEGIN; + ret = af9035_rw_udev(udev, &req); + if (ret) { + err("firmware download failed:%d", ret); + goto error; + } + + packets = fw_hdr.segment[i].len / FW_PACKET_MAX_DATA; + remainder = fw_hdr.segment[i].len % FW_PACKET_MAX_DATA; + len = FW_PACKET_MAX_DATA; + for (j = 0; j <= packets; j++) { + if (j == packets) /* size of the last packet */ + len = remainder; + + req_fw_dl.wlen = len; + req_fw_dl.wbuf = fw_data_ptr; + ret = af9035_rw_udev(udev, &req_fw_dl); + if (ret) { + err("firmware download failed at " \ + "segment:%d packet:%d err:%d", \ + i, j, ret); + goto error; + } + fw_data_ptr += len; + } + /* download end packet */ + req.cmd = CMD_FW_DOWNLOAD_END; + ret = af9035_rw_udev(udev, &req); + if (ret) { + err("firmware download failed:%d", ret); + goto error; + } + } else if (fw_hdr.segment[i].type == SEGMENT_ROM_COPY){ + packets = fw_hdr.segment[i].len / FW_PACKET_MAX_DATA; + remainder = fw_hdr.segment[i].len % FW_PACKET_MAX_DATA; + len = FW_PACKET_MAX_DATA; + for (j = 0; j <= packets; j++) { + if (j == packets) /* size of the last packet */ + len = remainder; + + req_rom.wlen = len; + req_rom.wbuf = fw_data_ptr; + ret = af9035_rw_udev(udev, &req_rom); + if (ret) { + err("firmware download failed at " \ + "segment:%d packet:%d err:%d", \ + i, j, ret); + goto error; + } + fw_data_ptr += len; + } + } else { + deb_info("%s: segment type:%d not implemented\n", + __func__, fw_hdr.segment[i].type); + } + } + + /* firmware loaded, request boot */ + req.cmd = CMD_BOOT; + ret = af9035_rw_udev(udev, &req); + if (ret) + goto error; + + /* ensure firmware starts */ + wbuf[0] = 1; + ret = af9035_rw_udev(udev, &req_fw_ver); + if (ret) + goto error; + + deb_info("%s: reply:%02x %02x %02x %02x\n", __func__, + rbuf[0], rbuf[1], rbuf[2], rbuf[3]); + + if (!(rbuf[0] || rbuf[1] || rbuf[2] || rbuf[3])) { + err("firmware did not run"); + ret = -EIO; + } + +error: + if (ret) + deb_info("%s: failed:%d\n", __func__, ret); + + return ret; +} + +static int af9035_read_eeprom_reg(struct usb_device *udev, u16 reg, u8 *val) +{ + u8 wbuf[] = {1, 2, 0, 0, reg >> 8, reg & 0xff}; + struct af9035_req req = {CMD_REG_DEMOD_READ, LINK, sizeof(wbuf), wbuf, + 1, val}; + return af9035_rw_udev(udev, &req); +} + +static int af9035_read_config(struct usb_device *udev) +{ + int ret; + u8 val, i, offset = 0; + + /* IR remote controller */ + ret = af9035_read_eeprom_reg(udev, EEPROM_IR_MODE, &val); + if (ret) + goto error; + deb_info("%s: IR mode:%d\n", __func__, val); + + /* TS mode - one or two receivers */ + ret = af9035_read_eeprom_reg(udev, EEPROM_TS_MODE, &val); + if (ret) + goto error; + af9035_config.dual_mode = val; + deb_info("%s: TS mode:%d\n", __func__, af9035_config.dual_mode); + + /* Set adapter0 buffer size according to USB port speed, adapter1 buffer + size can be static because it is enabled only USB2.0 */ + for (i = 0; i < af9035_properties_count; i++) { + /* USB1.1 set smaller buffersize and disable 2nd adapter */ + if (udev->speed == USB_SPEED_FULL) { + af9035_properties[i].adapter[0].stream.u.bulk.buffersize + = TS_USB11_MAX_PACKET_SIZE; + /* disable 2nd adapter because we don't have + PID-filters */ + af9035_config.dual_mode = 0; + } else { + af9035_properties[i].adapter[0].stream.u.bulk.buffersize + = TS_USB20_FRAME_SIZE; + } + } + + if (af9035_config.dual_mode) { + /* read 2nd demodulator I2C address */ + ret = af9035_read_eeprom_reg(udev, EEPROM_2WIREADDR, &val); + if (ret) + goto error; + deb_info("%s: 2nd demod I2C addr:%02x\n", __func__, val); + af9035_af9033_config[1].demod_address = val; + /* enable 2nd adapter */ + for (i = 0; i < af9035_properties_count; i++) + af9035_properties[i].num_adapters = 2; + } else { + /* disable 2nd adapter */ + for (i = 0; i < af9035_properties_count; i++) + af9035_properties[i].num_adapters = 1; + } + + for (i = 0; i < af9035_properties[0].num_adapters; i++) { + if (i == 1) + offset = EEPROM_SHIFT; + + /* saw BW */ + ret = af9035_read_eeprom_reg(udev, EEPROM_SAW_BW1 + offset, + &val); + if (ret) + goto error; + deb_info("%s: [%d] saw BW:%d\n", __func__, i, val); + + /* xtal */ + ret = af9035_read_eeprom_reg(udev, EEPROM_XTAL1 + offset, &val); + if (ret) + goto error; + deb_info("%s: [%d] xtal:%d\n", __func__, i, val); + + /* RF spectrum inversion */ + ret = af9035_read_eeprom_reg(udev, EEPROM_SPECINV1 + offset, + &val); + if (ret) + goto error; + deb_info("%s: [%d] RF spectrum inv:%d\n", __func__, i, val); + + /* IF */ + ret = af9035_read_eeprom_reg(udev, EEPROM_IFFREQH1 + offset, + &val); + if (ret) + goto error; + af9035_af9033_config[i].if_freq = val << 8; + ret = af9035_read_eeprom_reg(udev, EEPROM_IFFREQL1 + offset, + &val); + if (ret) + goto error; + af9035_af9033_config[i].if_freq += val; + deb_info("%s: [%d] IF:%d\n", __func__, i, + af9035_af9033_config[0].if_freq); + + /* MT2060 IF1 */ + ret = af9035_read_eeprom_reg(udev, EEPROM_IF1H1 + offset, &val); + if (ret) + goto error; + af9035_config.mt2060_if1[i] = val << 8; + ret = af9035_read_eeprom_reg(udev, EEPROM_IF1L1 + offset, &val); + if (ret) + goto error; + af9035_config.mt2060_if1[i] += val; + deb_info("%s: [%d] MT2060 IF1:%d\n", __func__, i, + af9035_config.mt2060_if1[i]); + + /* tuner */ + ret = af9035_read_eeprom_reg(udev, EEPROM_TUNER_ID1 + offset, + &val); + if (ret) + goto error; + switch (val) { + case AF9033_TUNER_TUA9001: + af9035_af9033_config[i].rf_spec_inv = 1; + break; + case AF9033_TUNER_MXL5007t: + af9035_af9033_config[i].rf_spec_inv = 1; + break; + default: + warn("tuner ID:%d not supported, please report!", val); + return -ENODEV; + }; + + af9035_af9033_config[i].tuner = val; + deb_info("%s: [%d] tuner ID:%d\n", __func__, i, val); + } + +error: + if (ret) + err("eeprom read failed:%d", ret); + + if (le16_to_cpu(udev->descriptor.idVendor) == USB_VID_AVERMEDIA && + le16_to_cpu(udev->descriptor.idProduct) == USB_PID_AVERMEDIA_A825) { + deb_info("%s: AverMedia A825: overriding config\n", __func__); + /* set correct IF */ + for (i = 0; i < af9035_properties[0].num_adapters; i++) { + af9035_af9033_config[i].if_freq = 4570000; + } + } + + return ret; +} + +static int af9035_aux_init(struct usb_device *d) +{ + int ret; + u8 tmp, i; + + /* get demod crystal and ADC freqs */ + ret = af9035_read_reg_bits_bis(d, LINK, + r_io_mux_pwron_clk_strap, io_mux_pwron_clk_strap_pos, + io_mux_pwron_clk_strap_len, &tmp); + if (ret) + goto error; + + for (i = 0; i < af9035_properties[0].num_adapters; i++) { + af9035_af9033_config[i].crystal_clock = + clock_table[tmp].crystal; + af9035_af9033_config[i].adc_clock = + clock_table[tmp].adc; + } + + /* write 2nd demod I2C address to device */ + ret = af9035_write_reg_bis(d, LINK, 0x417f, + af9035_af9033_config[1].demod_address); + if (ret) + goto error; + + /* enable / disable clock out for 2nd demod for power saving */ + ret = af9035_write_reg_bis(d, LINK, p_reg_top_clkoen, + af9035_config.dual_mode); + +error: + return ret; +} + +static int af9035_identify_state(struct usb_device *udev, + struct dvb_usb_device_properties *props, + struct dvb_usb_device_description **desc, + int *cold) +{ + int ret; + u8 wbuf[1] = {1}; + u8 rbuf[4]; + struct af9035_req req = {CMD_QUERYINFO, 0, sizeof(wbuf), wbuf, + sizeof(rbuf), rbuf}; + + ret = af9035_rw_udev(udev, &req); + if (ret) + return ret; + + deb_info("%s: reply:%02x %02x %02x %02x\n", __func__, + rbuf[0], rbuf[1], rbuf[2], rbuf[3]); + if (rbuf[0] || rbuf[1] || rbuf[2] || rbuf[3]) + *cold = 0; + else + *cold = 1; + + return ret; +} + +static int af9035_af9033_frontend_attach(struct dvb_usb_adapter *adap) +{ + /* attach demodulator */ + adap->fe = dvb_attach(af9033_attach, &af9035_af9033_config[adap->id], + &adap->dev->i2c_adap); + + return adap->fe == NULL ? -ENODEV : 0; +} + +static struct tua9001_config af9035_tua9001_config[] = { + { + .i2c_address = 0xc0, + } , { + .i2c_address = 0xc1, + } +}; + +static struct mxl5007t_config af9035_mxl5007t_config[] = { + { + .xtal_freq_hz = MxL_XTAL_24_MHZ, + .if_freq_hz = MxL_IF_4_57_MHZ, + .invert_if = 0, + .loop_thru_enable = 0, + .clk_out_enable = 0, + .clk_out_amp = MxL_CLKOUT_AMP_0_94V, + } , { + .xtal_freq_hz = MxL_XTAL_24_MHZ, + .if_freq_hz = MxL_IF_4_57_MHZ, + .invert_if = 0, + .loop_thru_enable = 3, + .clk_out_enable = 1, + .clk_out_amp = MxL_CLKOUT_AMP_0_94V, + } +}; + +static int af9035_tuner_attach(struct dvb_usb_adapter *adap) +{ + int ret; + deb_info("%s: \n", __func__); + + switch (af9035_af9033_config[adap->id].tuner) { + case AF9033_TUNER_TUA9001: + af9035_af9033_config[adap->id].tuner_address = af9035_tua9001_config[adap->id].i2c_address; + af9035_af9033_config[adap->id].tuner_address += adap->id; + if (adap->id == 0) { + /* gpiot3 TUA9001 RESETN + gpiot2 TUA9001 RXEN */ + ret = af9035_write_reg_bits(adap->dev, LINK, + p_reg_top_gpiot2_en, reg_top_gpiot2_en_pos, + reg_top_gpiot2_en_len, 1); + ret = af9035_write_reg_bits(adap->dev, LINK, + p_reg_top_gpiot2_on, reg_top_gpiot2_on_pos, + reg_top_gpiot2_on_len, 1); + ret = af9035_write_reg_bits(adap->dev, LINK, + p_reg_top_gpiot3_en, reg_top_gpiot3_en_pos, + reg_top_gpiot3_en_len, 1); + ret = af9035_write_reg_bits(adap->dev, LINK, + p_reg_top_gpiot3_on, reg_top_gpiot3_on_pos, + reg_top_gpiot3_on_len, 1); + + /* reset tuner */ + ret = af9035_write_reg_bits(adap->dev, LINK, p_reg_top_gpiot3_o, + reg_top_gpiot3_o_pos, reg_top_gpiot3_o_len, 0); + msleep(1); + ret = af9035_write_reg_bits(adap->dev, LINK, p_reg_top_gpiot3_o, + reg_top_gpiot3_o_pos, reg_top_gpiot3_o_len, 1); + + /* activate tuner - TODO: do that like I2C gate control */ + ret = af9035_write_reg_bits(adap->dev, LINK, p_reg_top_gpiot2_o, + reg_top_gpiot2_o_pos, reg_top_gpiot2_o_len, 1); + } + + ret = dvb_attach(tua9001_attach, adap->fe, &adap->dev->i2c_adap, + &af9035_tua9001_config[adap->id]) == NULL ? -ENODEV : 0; + + break; + case AF9033_TUNER_MXL5007t: + af9035_af9033_config[adap->id].tuner_address = 0xc0; + af9035_af9033_config[adap->id].tuner_address += adap->id; + if (adap->id == 0) { + ret = af9035_write_reg(adap->dev, LINK, + p_reg_top_gpioh12_en, + 1); + + ret = af9035_write_reg(adap->dev, LINK, + p_reg_top_gpioh12_on, + 1); + + ret = af9035_write_reg(adap->dev, LINK, + p_reg_top_gpioh12_o, + 0); + + msleep(30); + + ret = af9035_write_reg(adap->dev, LINK, + p_reg_top_gpioh12_o, + 1); + + msleep(300); + + ret = af9035_write_reg(adap->dev, LINK, + p_reg_top_gpioh4_en, + 1); + + ret = af9035_write_reg(adap->dev, LINK, + p_reg_top_gpioh4_on, + 1); + + ret = af9035_write_reg(adap->dev, LINK, + p_reg_top_gpioh4_o, + 0); + + ret = af9035_write_reg(adap->dev, LINK, + p_reg_top_gpioh3_en, + 1); + + ret = af9035_write_reg(adap->dev, LINK, + p_reg_top_gpioh3_on, + 1); + + ret = af9035_write_reg(adap->dev, LINK, + p_reg_top_gpioh3_o, + 1); + } + + ret = dvb_attach(mxl5007t_attach, adap->fe, &adap->dev->i2c_adap, + af9035_af9033_config[adap->id].tuner_address, + &af9035_mxl5007t_config[adap->id]) == NULL ? -ENODEV : 0; + + break; + default: + ret = -ENODEV; + err("unknown tuner ID:%d", + af9035_af9033_config[adap->id].tuner); + } + + return ret; +} + +static struct usb_device_id af9035_usb_table[] = { +/* 0 */{USB_DEVICE(USB_VID_AFATECH, USB_PID_AFATECH_AF9035_1000)}, + {USB_DEVICE(USB_VID_AFATECH, USB_PID_AFATECH_AF9035_1001)}, + {USB_DEVICE(USB_VID_AFATECH, USB_PID_AFATECH_AF9035_1002)}, + {USB_DEVICE(USB_VID_AFATECH, USB_PID_AFATECH_AF9035_1003)}, + {USB_DEVICE(USB_VID_AFATECH, USB_PID_AFATECH_AF9035_9035)}, +/* 5 */{USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_CINERGY_T_STICK)}, +/* 6 */{USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A825)}, + {0}, +}; + +MODULE_DEVICE_TABLE(usb, af9035_usb_table); + +static struct dvb_usb_device_properties af9035_properties[] = { + { + .caps = DVB_USB_IS_AN_I2C_ADAPTER, + + .usb_ctrl = DEVICE_SPECIFIC, + .download_firmware = af9035_download_firmware, + .firmware = "dvb-usb-af9035-01.fw", + .no_reconnect = 1, + + .size_of_priv = 0, + + .adapter = { + { + .frontend_attach = + af9035_af9033_frontend_attach, + .tuner_attach = af9035_tuner_attach, + .stream = { + .type = USB_BULK, + .count = 4, + .endpoint = 0x84, + }, + }, + { + .frontend_attach = + af9035_af9033_frontend_attach, + .tuner_attach = af9035_tuner_attach, + .stream = { + .type = USB_BULK, + .count = 4, + .endpoint = 0x85, + .u = { + .bulk = { + .buffersize = + TS_USB20_FRAME_SIZE, + } + } + }, + } + }, + + .identify_state = af9035_identify_state, + + .i2c_algo = &af9035_i2c_algo, + + .num_device_descs = 3, + .devices = { + { + .name = "Afatech AF9035 DVB-T USB2.0 stick", + .cold_ids = {&af9035_usb_table[0], + &af9035_usb_table[1], + &af9035_usb_table[2], + &af9035_usb_table[3], + &af9035_usb_table[4], NULL}, + .warm_ids = {NULL}, + }, + { + .name = "TerraTec Cinergy T Stick", + .cold_ids = {&af9035_usb_table[5], NULL}, + .warm_ids = {NULL}, + }, + { + .name = "Avermedia TwinStar", + .cold_ids = {&af9035_usb_table[6], NULL}, + .warm_ids = {NULL}, + }, + } + }, +}; + +static int af9035_usb_probe(struct usb_interface *intf, + const struct usb_device_id *id) +{ + int ret = 0; + struct dvb_usb_device *d = NULL; + struct usb_device *udev = interface_to_usbdev(intf); + u8 i; + + deb_info("%s: interface:%d\n", __func__, + intf->cur_altsetting->desc.bInterfaceNumber); + + /* interface 0 is used by DVB-T receiver and + interface 1 is for remote controller (HID) */ + if (intf->cur_altsetting->desc.bInterfaceNumber == 0) { + ret = af9035_read_config(udev); + if (ret) + return ret; + + ret = af9035_aux_init(udev); + if (ret) + return ret; + + for (i = 0; i < af9035_properties_count; i++) { + ret = dvb_usb_device_init(intf, &af9035_properties[i], + THIS_MODULE, &d, adapter_nr); + if (!ret) + break; + if (ret != -ENODEV) + return ret; + } + if (ret) + return ret; + + if (d) + ret = af9035_init(d); + } + + return ret; +} + +/* usb specific object needed to register this driver with the usb subsystem */ +static struct usb_driver af9035_usb_driver = { + .name = "dvb_usb_af9035", + .probe = af9035_usb_probe, + .disconnect = dvb_usb_device_exit, + .id_table = af9035_usb_table, +}; + +/* module stuff */ +static int __init af9035_usb_module_init(void) +{ + int ret; + ret = usb_register(&af9035_usb_driver); + if (ret) + err("module init failed:%d", ret); + + return ret; +} + +static void __exit af9035_usb_module_exit(void) +{ + /* deregister this driver from the USB subsystem */ + usb_deregister(&af9035_usb_driver); +} + +module_init(af9035_usb_module_init); +module_exit(af9035_usb_module_exit); + +MODULE_AUTHOR("Antti Palosaari "); +MODULE_DESCRIPTION("Afatech AF9035 driver"); +MODULE_LICENSE("GPL"); diff -r 37581bb7e6f1 linux/drivers/media/dvb/dvb-usb/af9035.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/linux/drivers/media/dvb/dvb-usb/af9035.h Sat Feb 27 16:17:22 2010 +0100 @@ -0,0 +1,187 @@ +/* + * Afatech AF9035 DVB USB driver + * + * Copyright (C) 2008 Afatech + * Copyright (C) 2009 Antti Palosaari + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Thanks to TerraTec for a support received. + */ + +#ifndef AF9035_H +#define AF9035_H +#include "af9033_reg.h" + +#define DVB_USB_LOG_PREFIX "af9035" +#include "dvb-usb.h" + +#define deb_info(args...) dprintk(dvb_usb_af9035_debug, 0x01, args) +#define deb_rc(args...) dprintk(dvb_usb_af9035_debug, 0x02, args) +#define deb_xfer(args...) dprintk(dvb_usb_af9035_debug, 0x04, args) +#define deb_reg(args...) dprintk(dvb_usb_af9035_debug, 0x08, args) +#define deb_i2c(args...) dprintk(dvb_usb_af9035_debug, 0x10, args) +#define deb_fw(args...) dprintk(dvb_usb_af9035_debug, 0x20, args) + +#define AF9035_USB_TIMEOUT 2000 + +#define LINK 0x00 +#define OFDM 0x80 + +#define TS_MODE_SINGLE 0 +#define TS_MODE_DCA_PIP 1 +#define TS_MODE_DCA 2 /* any other value than 0, 1, 3 (?) */ +#define TS_MODE_PIP 3 + +#define TS_PACKET_SIZE 188 +#define TS_USB20_PACKET_COUNT 348 +#define TS_USB20_FRAME_SIZE (TS_PACKET_SIZE*TS_USB20_PACKET_COUNT) +#define TS_USB11_PACKET_COUNT 21 +#define TS_USB11_FRAME_SIZE (TS_PACKET_SIZE*TS_USB11_PACKET_COUNT) +#define TS_USB20_MAX_PACKET_SIZE 512 +#define TS_USB11_MAX_PACKET_SIZE 64 + +/* EEPROM locations */ +#define GANY_ONLY 0x42f5 +#define EEPROM_FLB_OFS 8 +#define EEPROM_BASE_ADDR (GANY_ONLY + EEPROM_FLB_OFS) +#define EEPROM_SHIFT (0x10) + +#define EEPROM_IR_MODE (EEPROM_BASE_ADDR+0x10) /* 00:disabled, 01:HID */ +#define EEPROM_SELSUSPEND (EEPROM_BASE_ADDR+0x28) /* selective suspend mode */ +#define EEPROM_TS_MODE (EEPROM_BASE_ADDR+0x28+1) /* 0:one ts, 1:dual ts */ +#define EEPROM_2WIREADDR (EEPROM_BASE_ADDR+0x28+2) /* 2nd demod I2C addr */ +#define EEPROM_SUSPEND (EEPROM_BASE_ADDR+0x28+3) /* suspend mode */ +#define EEPROM_IR_TYPE (EEPROM_BASE_ADDR+0x28+4) /* 0:NEC, 1:RC6 */ + +#define EEPROM_SAW_BW1 (EEPROM_BASE_ADDR+0x28+5) +#define EEPROM_XTAL1 (EEPROM_BASE_ADDR+0x28+6) +#define EEPROM_SPECINV1 (EEPROM_BASE_ADDR+0x28+7) +#define EEPROM_TUNER_ID1 (EEPROM_BASE_ADDR+0x30+4) +#define EEPROM_IFFREQL1 (EEPROM_BASE_ADDR+0x30) +#define EEPROM_IFFREQH1 (EEPROM_BASE_ADDR+0x30+1) +#define EEPROM_IF1L1 (EEPROM_BASE_ADDR+0x30+2) +#define EEPROM_IF1H1 (EEPROM_BASE_ADDR+0x30+3) + +#define EEPROM_SAW_BW2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x28+5) +#define EEPROM_XTAL2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x28+6) +#define EEPROM_SPECINV2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x28+7) +#define EEPROM_TUNER_ID2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x30+4) +#define EEPROM_IFFREQL2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x30) +#define EEPROM_IFFREQH2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x30+1) +#define EEPROM_IF1L2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x30+2) +#define EEPROM_IF1H2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x30+3) + +struct af9035_clock { + u32 crystal; + u32 adc; +}; + +static struct af9035_clock clock_table[] = { + {20480000, 20480000}, /* FPGA */ + {16384000, 20480000}, /* 16.38MHz */ + {20480000, 20480000}, /* 20.48MHz */ + {36000000, 20250000}, /* 36.00MHz */ + {30000000, 20156250}, /* 30.00MHz */ + {26000000, 20583333}, /* 26.00MHz */ + {28000000, 20416667}, /* 28.00MHz */ + {32000000, 20500000}, /* 32.00MHz */ + {34000000, 20187500}, /* 34.00MHz */ + {24000000, 20500000}, /* 24.00MHz */ + {22000000, 20625000}, /* 22.00MHz */ + {12000000, 20250000}, /* 12.00MHz */ +}; + +struct af9035_req { + u8 cmd; + u8 mbox; + u8 wlen; + u8 *wbuf; + u8 rlen; + u8 *rbuf; +}; + +/* USB commands */ +#define CMD_REG_DEMOD_READ 0x00 +#define CMD_REG_DEMOD_WRITE 0x01 +#define CMD_REG_TUNER_READ 0x02 +#define CMD_REG_TUNER_WRITE 0x03 +#define CMD_REG_EEPROM_READ 0x04 +#define CMD_REG_EEPROM_WRITE 0x05 +#define CMD_VAR_READ 0x08 +#define CMD_VAR_WRITE 0x09 + +#define CMD_DATA_READ 0x06 + +#define CMD_PLATFORM_GET 0x0A +#define CMD_PLATFORM_SET 0x0B +#define CMD_IP_CACHE 0x0D +#define CMD_IP_ADD 0x0E +#define CMD_IP_REMOVE 0x0F +#define CMD_PID_ADD 0x10 +#define CMD_PID_REMOVE 0x11 +/* get SI/PSI table for specific PID "once" */ +#define CMD_SIPSI_GET 0x12 +#define CMD_SIPSI_MPE_RESET 0x13 +#define CMD_H_PID_ADD 0x15 +#define CMD_H_PID_REMOVE 0x16 +#define CMD_ABORT 0x17 +#define CMD_IR_GET 0x18 +#define CMD_IR_SET 0x19 +#define CMD_FW_DOWNLOAD_BEGIN 0x24 +#define CMD_FW_DOWNLOAD 0x21 +#define CMD_FW_DOWNLOAD_END 0x25 +#define CMD_QUERYINFO 0x22 +#define CMD_BOOT 0x23 +#define CMD_REBOOT 0x23 +#define CMD_RUN_CODE 0x26 +#define CMD_SCATTER_READ 0x28 +#define CMD_SCATTER_WRITE 0x29 +#define CMD_GENERIC_READ 0x2A +#define CMD_GENERIC_WRITE 0x2B + +#define CMD_SERVICES_GET 0x83 +#define CMD_COMPONENT_ADD 0x86 +#define CMD_COMPONENT_REMOVE 0x87 +#define CMD_FIG_ADD 0x88 +#define CMD_FIG_REMOVE 0x89 + +/* this Linux driver does not implement usage of "short command" at all */ +#define CMD_SHORT_REG_DEMOD_READ 0x02 +#define CMD_SHORT_REG_DEMOD_WRITE 0X03 +#define CMD_SHORT_REG_TUNER_READ 0x04 +#define CMD_SHORT_REG_TUNER_WRITE 0X05 + +struct af9035_config { + u8 dual_mode:1; + u16 mt2060_if1[2]; +}; + +struct af9035_segment { +#define SEGMENT_FW_DOWNLOAD 0 +#define SEGMENT_ROM_COPY 1 +#define SEGMENT_DIRECT_CMD 2 + u8 type; + u32 len; +}; + +struct af9035_firmware_header { +#define SEGMENT_MAX_COUNT 50 + u8 segment_count; + struct af9035_segment segment[SEGMENT_MAX_COUNT]; +}; + +#endif diff -r 37581bb7e6f1 linux/drivers/media/dvb/dvb-usb/dvb-usb-ids.h --- a/linux/drivers/media/dvb/dvb-usb/dvb-usb-ids.h Wed Feb 24 22:48:50 2010 -0300 +++ b/linux/drivers/media/dvb/dvb-usb/dvb-usb-ids.h Sat Feb 27 16:17:22 2010 +0100 @@ -73,6 +73,11 @@ #define USB_PID_AFATECH_AF9005 0x9020 #define USB_PID_AFATECH_AF9015_9015 0x9015 #define USB_PID_AFATECH_AF9015_9016 0x9016 +#define USB_PID_AFATECH_AF9035_1000 0x1000 +#define USB_PID_AFATECH_AF9035_1001 0x1001 +#define USB_PID_AFATECH_AF9035_1002 0x1002 +#define USB_PID_AFATECH_AF9035_1003 0x1003 +#define USB_PID_AFATECH_AF9035_9035 0x9035 #define USB_PID_TREKSTOR_DVBT 0x901b #define USB_VID_ALINK_DTU 0xf170 #define USB_PID_ANSONIC_DVBT_USB 0x6000 @@ -195,12 +200,14 @@ #define USB_PID_AVERMEDIA_A310 0xa310 #define USB_PID_AVERMEDIA_A850 0x850a #define USB_PID_AVERMEDIA_A805 0xa805 +#define USB_PID_AVERMEDIA_A825 0x0825 #define USB_PID_TECHNOTREND_CONNECT_S2400 0x3006 #define USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY 0x005a #define USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY_2 0x0081 #define USB_PID_TERRATEC_CINERGY_HT_USB_XE 0x0058 #define USB_PID_TERRATEC_CINERGY_HT_EXPRESS 0x0060 #define USB_PID_TERRATEC_CINERGY_T_EXPRESS 0x0062 +#define USB_PID_TERRATEC_CINERGY_T_STICK 0x0093 #define USB_PID_TERRATEC_CINERGY_T_XXS 0x0078 #define USB_PID_TERRATEC_CINERGY_T_XXS_2 0x00ab #define USB_PID_TERRATEC_T3 0x10a0 diff -r 37581bb7e6f1 linux/drivers/media/dvb/frontends/Kconfig --- a/linux/drivers/media/dvb/frontends/Kconfig Wed Feb 24 22:48:50 2010 -0300 +++ b/linux/drivers/media/dvb/frontends/Kconfig Sat Feb 27 16:17:22 2010 +0100 @@ -606,6 +606,13 @@ Currently supported tuners: * Panasonic ENV57H12D5 (ET-50DT) +config DVB_AF9033 + tristate "Afatech AF9033 demodulator" + depends on DVB_CORE && I2C + default m if DVB_FE_CUSTOMISE + help + Say Y when you want to support this frontend. + comment "Tools to develop new frontends" config DVB_DUMMY_FE diff -r 37581bb7e6f1 linux/drivers/media/dvb/frontends/Makefile --- a/linux/drivers/media/dvb/frontends/Makefile Wed Feb 24 22:48:50 2010 -0300 +++ b/linux/drivers/media/dvb/frontends/Makefile Sat Feb 27 16:17:22 2010 +0100 @@ -79,6 +79,7 @@ obj-$(CONFIG_DVB_STV090x) += stv090x.o obj-$(CONFIG_DVB_STV6110x) += stv6110x.o obj-$(CONFIG_DVB_ISL6423) += isl6423.o +obj-$(CONFIG_DVB_AF9033) += af9033.o obj-$(CONFIG_DVB_EC100) += ec100.o obj-$(CONFIG_DVB_DS3000) += ds3000.o obj-$(CONFIG_DVB_MB86A16) += mb86a16.o diff -r 37581bb7e6f1 linux/drivers/media/dvb/frontends/af9033.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/linux/drivers/media/dvb/frontends/af9033.c Sat Feb 27 16:17:22 2010 +0100 @@ -0,0 +1,1663 @@ +/* + * Afatech AF9033 demodulator driver + * + * Copyright (C) 2008 Afatech + * Copyright (C) 2009 Antti Palosaari + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Thanks to TerraTec for a support received. + */ + +#include "dvb_frontend.h" +#include "af9033_priv.h" +#include "af9033.h" +#include "af9033_reg.h" + +static int af9033_debug; +module_param_named(debug, af9033_debug, int, 0644); +MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); + +struct af9033_state { + struct i2c_adapter *i2c; + struct dvb_frontend frontend; + struct af9033_config config; + + u16 signal_strength; + u32 ber; + u32 ucblocks; + u16 snr; + u32 frequency; + unsigned long next_statistics_check; +}; + +static u8 regmask[8] = {0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff}; + +/* write multiple registers */ +static int af9033_write_regs(struct af9033_state *state, u8 mbox, u16 reg, + u8 *val, u8 len) +{ + u8 buf[3+len]; + struct i2c_msg msg = { + .addr = state->config.demod_address, + .flags = 0, + .len = sizeof(buf), + .buf = buf }; + + buf[0] = mbox; + buf[1] = reg >> 8; + buf[2] = reg & 0xff; + memcpy(&buf[3], val, len); + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + warn("I2C write failed reg:%04x len:%d", reg, len); + return -EREMOTEIO; + } + return 0; +} + +/* read multiple registers */ +static int af9033_read_regs(struct af9033_state *state, u8 mbox, u16 reg, + u8 *val, u8 len) +{ + u8 obuf[3] = {mbox, reg >> 8, reg & 0xff}; + struct i2c_msg msg[2] = { + { + .addr = state->config.demod_address, + .flags = 0, + .len = sizeof(obuf), + .buf = obuf + }, { + .addr = state->config.demod_address, + .flags = I2C_M_RD, + .len = len, + .buf = val + } + }; + + if (i2c_transfer(state->i2c, msg, 2) != 2) { + warn("I2C read failed reg:%04x", reg); + return -EREMOTEIO; + } + return 0; +} + +/* write single register */ +static int af9033_write_reg(struct af9033_state *state, u8 mbox, u16 reg, + u8 val) +{ + return af9033_write_regs(state, mbox, reg, &val, 1); +} + +/* read single register */ +static int af9033_read_reg(struct af9033_state *state, u8 mbox, u16 reg, + u8 *val) +{ + return af9033_read_regs(state, mbox, reg, val, 1); +} + +/* write single register bits */ +static int af9033_write_reg_bits(struct af9033_state *state, u8 mbox, u16 reg, + u8 pos, u8 len, u8 val) +{ + int ret; + u8 tmp, mask; + + ret = af9033_read_reg(state, mbox, reg, &tmp); + if (ret) + return ret; + + mask = regmask[len - 1] << pos; + tmp = (tmp & ~mask) | ((val << pos) & mask); + + return af9033_write_reg(state, mbox, reg, tmp); +} + +/* read single register bits */ +static int af9033_read_reg_bits(struct af9033_state *state, u8 mbox, u16 reg, + u8 pos, u8 len, u8 *val) +{ + int ret; + u8 tmp; + + ret = af9033_read_reg(state, mbox, reg, &tmp); + if (ret) + return ret; + + *val = (tmp >> pos) & regmask[len - 1]; + return 0; +} + +static u32 af913_div(u32 a, u32 b, u32 x) +{ + u32 r = 0, c = 0, i; + deb_info("%s: a:%d b:%d x:%d\n", __func__, a, b, x); + + if (a > b) { + c = a / b; + a = a - c * b; + } + + for (i = 0; i < x; i++) { + if (a >= b) { + r += 1; + a -= b; + } + a <<= 1; + r <<= 1; + } + r = (c << (u32)x) + r; + + deb_info("%s: a:%d b:%d x:%d r:%d r:%x\n", __func__, a, b, x, r, r); + return r; +} + +static int af9033_set_coeff(struct af9033_state *state, fe_bandwidth_t bw) +{ + int ret = 0; + u8 tmp, i = 0; + u8 buf[36]; + u32 uninitialized_var(coeff1_2048nu); + u32 uninitialized_var(coeff1_4096nu); + u32 uninitialized_var(coeff1_8191nu); + u32 uninitialized_var(coeff1_8192nu); + u32 uninitialized_var(coeff1_8193nu); + u32 uninitialized_var(coeff2_2k); + u32 uninitialized_var(coeff2_4k); + u32 uninitialized_var(coeff2_8k); + u16 uninitialized_var(bfsfcw_fftindex_ratio); + u16 uninitialized_var(fftindex_bfsfcw_ratio); + deb_info("%s: adc_clock:%d bw:%d\n", __func__, + state->config.adc_clock, bw); + + switch (state->config.adc_clock) { + case 20156250: + switch (bw) { +#if 0 /* keep */ + case BANDWIDTH_5_MHZ: + coeff1_2048nu = 0x02449b5c; + coeff1_4096nu = 0x01224dae; + coeff1_8191nu = 0x00912b60; + coeff1_8192nu = 0x009126d7; + coeff1_8193nu = 0x0091224e; + coeff2_2k = 0x01224dae; + coeff2_4k = 0x009126d7; + coeff2_8k = 0x0048936b; + bfsfcw_fftindex_ratio = 0x0387; + fftindex_bfsfcw_ratio = 0x0122; + break; +#endif + case BANDWIDTH_6_MHZ: + coeff1_2048nu = 0x02b8ba6e; + coeff1_4096nu = 0x015c5d37; + coeff1_8191nu = 0x00ae340d; + coeff1_8192nu = 0x00ae2e9b; + coeff1_8193nu = 0x00ae292a; + coeff2_2k = 0x015c5d37; + coeff2_4k = 0x00ae2e9b; + coeff2_8k = 0x0057174e; + bfsfcw_fftindex_ratio = 0x02f1; + fftindex_bfsfcw_ratio = 0x015c; + break; + case BANDWIDTH_7_MHZ: + coeff1_2048nu = 0x032cd980; + coeff1_4096nu = 0x01966cc0; + coeff1_8191nu = 0x00cb3cba; + coeff1_8192nu = 0x00cb3660; + coeff1_8193nu = 0x00cb3007; + coeff2_2k = 0x01966cc0; + coeff2_4k = 0x00cb3660; + coeff2_8k = 0x00659b30; + bfsfcw_fftindex_ratio = 0x0285; + fftindex_bfsfcw_ratio = 0x0196; + break; + case BANDWIDTH_8_MHZ: + coeff1_2048nu = 0x03a0f893; + coeff1_4096nu = 0x01d07c49; + coeff1_8191nu = 0x00e84567; + coeff1_8192nu = 0x00e83e25; + coeff1_8193nu = 0x00e836e3; + coeff2_2k = 0x01d07c49; + coeff2_4k = 0x00e83e25; + coeff2_8k = 0x00741f12; + bfsfcw_fftindex_ratio = 0x0234; + fftindex_bfsfcw_ratio = 0x01d0; + break; + default: + ret = -EINVAL; + } + break; + case 20187500: + switch (bw) { +#if 0 /* keep */ + case BANDWIDTH_5_MHZ: + coeff1_2048nu = 0x0243b546; + coeff1_4096nu = 0x0121daa3; + coeff1_8191nu = 0x0090f1d9; + coeff1_8192nu = 0x0090ed51; + coeff1_8193nu = 0x0090e8ca; + coeff2_2k = 0x0121daa3; + coeff2_4k = 0x0090ed51; + coeff2_8k = 0x004876a9; + bfsfcw_fftindex_ratio = 0x0388; + fftindex_bfsfcw_ratio = 0x0122; + break; +#endif + case BANDWIDTH_6_MHZ: + coeff1_2048nu = 0x02b7a654; + coeff1_4096nu = 0x015bd32a; + coeff1_8191nu = 0x00adef04; + coeff1_8192nu = 0x00ade995; + coeff1_8193nu = 0x00ade426; + coeff2_2k = 0x015bd32a; + coeff2_4k = 0x00ade995; + coeff2_8k = 0x0056f4ca; + bfsfcw_fftindex_ratio = 0x02f2; + fftindex_bfsfcw_ratio = 0x015c; + break; + case BANDWIDTH_7_MHZ: + coeff1_2048nu = 0x032b9761; + coeff1_4096nu = 0x0195cbb1; + coeff1_8191nu = 0x00caec30; + coeff1_8192nu = 0x00cae5d8; + coeff1_8193nu = 0x00cadf81; + coeff2_2k = 0x0195cbb1; + coeff2_4k = 0x00cae5d8; + coeff2_8k = 0x006572ec; + bfsfcw_fftindex_ratio = 0x0286; + fftindex_bfsfcw_ratio = 0x0196; + break; + case BANDWIDTH_8_MHZ: + coeff1_2048nu = 0x039f886f; + coeff1_4096nu = 0x01cfc438; + coeff1_8191nu = 0x00e7e95b; + coeff1_8192nu = 0x00e7e21c; + coeff1_8193nu = 0x00e7dadd; + coeff2_2k = 0x01cfc438; + coeff2_4k = 0x00e7e21c; + coeff2_8k = 0x0073f10e; + bfsfcw_fftindex_ratio = 0x0235; + fftindex_bfsfcw_ratio = 0x01d0; + break; + default: + ret = -EINVAL; + } + break; + case 20250000: + switch (bw) { +#if 0 /* keep */ + case BANDWIDTH_5_MHZ: + coeff1_2048nu = 0x0241eb3b; + coeff1_4096nu = 0x0120f59e; + coeff1_8191nu = 0x00907f53; + coeff1_8192nu = 0x00907acf; + coeff1_8193nu = 0x0090764b; + coeff2_2k = 0x0120f59e; + coeff2_4k = 0x00907acf; + coeff2_8k = 0x00483d67; + bfsfcw_fftindex_ratio = 0x038b; + fftindex_bfsfcw_ratio = 0x0121; + break; +#endif + case BANDWIDTH_6_MHZ: + coeff1_2048nu = 0x02b580ad; + coeff1_4096nu = 0x015ac057; + coeff1_8191nu = 0x00ad6597; + coeff1_8192nu = 0x00ad602b; + coeff1_8193nu = 0x00ad5ac1; + coeff2_2k = 0x015ac057; + coeff2_4k = 0x00ad602b; + coeff2_8k = 0x0056b016; + bfsfcw_fftindex_ratio = 0x02f4; + fftindex_bfsfcw_ratio = 0x015b; + break; + case BANDWIDTH_7_MHZ: + coeff1_2048nu = 0x03291620; + coeff1_4096nu = 0x01948b10; + coeff1_8191nu = 0x00ca4bda; + coeff1_8192nu = 0x00ca4588; + coeff1_8193nu = 0x00ca3f36; + coeff2_2k = 0x01948b10; + coeff2_4k = 0x00ca4588; + coeff2_8k = 0x006522c4; + bfsfcw_fftindex_ratio = 0x0288; + fftindex_bfsfcw_ratio = 0x0195; + break; + case BANDWIDTH_8_MHZ: + coeff1_2048nu = 0x039cab92; + coeff1_4096nu = 0x01ce55c9; + coeff1_8191nu = 0x00e7321e; + coeff1_8192nu = 0x00e72ae4; + coeff1_8193nu = 0x00e723ab; + coeff2_2k = 0x01ce55c9; + coeff2_4k = 0x00e72ae4; + coeff2_8k = 0x00739572; + bfsfcw_fftindex_ratio = 0x0237; + fftindex_bfsfcw_ratio = 0x01ce; + break; + default: + ret = -EINVAL; + } + break; + case 20583333: + switch (bw) { +#if 0 /* keep */ + case BANDWIDTH_5_MHZ: + coeff1_2048nu = 0x02388f54; + coeff1_4096nu = 0x011c47aa; + coeff1_8191nu = 0x008e2846; + coeff1_8192nu = 0x008e23d5; + coeff1_8193nu = 0x008e1f64; + coeff2_2k = 0x011c47aa; + coeff2_4k = 0x008e23d5; + coeff2_8k = 0x004711ea; + bfsfcw_fftindex_ratio = 0x039a; + fftindex_bfsfcw_ratio = 0x011c; + break; +#endif + case BANDWIDTH_6_MHZ: + coeff1_2048nu = 0x02aa4598; + coeff1_4096nu = 0x015522cc; + coeff1_8191nu = 0x00aa96bb; + coeff1_8192nu = 0x00aa9166; + coeff1_8193nu = 0x00aa8c12; + coeff2_2k = 0x015522cc; + coeff2_4k = 0x00aa9166; + coeff2_8k = 0x005548b3; + bfsfcw_fftindex_ratio = 0x0300; + fftindex_bfsfcw_ratio = 0x0155; + break; + case BANDWIDTH_7_MHZ: + coeff1_2048nu = 0x031bfbdc; + coeff1_4096nu = 0x018dfdee; + coeff1_8191nu = 0x00c7052f; + coeff1_8192nu = 0x00c6fef7; + coeff1_8193nu = 0x00c6f8bf; + coeff2_2k = 0x018dfdee; + coeff2_4k = 0x00c6fef7; + coeff2_8k = 0x00637f7b; + bfsfcw_fftindex_ratio = 0x0293; + fftindex_bfsfcw_ratio = 0x018e; + break; + case BANDWIDTH_8_MHZ: + coeff1_2048nu = 0x038db21f; + coeff1_4096nu = 0x01c6d910; + coeff1_8191nu = 0x00e373a3; + coeff1_8192nu = 0x00e36c88; + coeff1_8193nu = 0x00e3656d; + coeff2_2k = 0x01c6d910; + coeff2_4k = 0x00e36c88; + coeff2_8k = 0x0071b644; + bfsfcw_fftindex_ratio = 0x0240; + fftindex_bfsfcw_ratio = 0x01c7; + break; + default: + ret = -EINVAL; + } + break; + case 20416667: + switch (bw) { +#if 0 /* keep */ + case BANDWIDTH_5_MHZ: + coeff1_2048nu = 0x023d337f; + coeff1_4096nu = 0x011e99c0; + coeff1_8191nu = 0x008f515a; + coeff1_8192nu = 0x008f4ce0; + coeff1_8193nu = 0x008f4865; + coeff2_2k = 0x011e99c0; + coeff2_4k = 0x008f4ce0; + coeff2_8k = 0x0047a670; + bfsfcw_fftindex_ratio = 0x0393; + fftindex_bfsfcw_ratio = 0x011f; + break; +#endif + case BANDWIDTH_6_MHZ: + coeff1_2048nu = 0x02afd765; + coeff1_4096nu = 0x0157ebb3; + coeff1_8191nu = 0x00abfb39; + coeff1_8192nu = 0x00abf5d9; + coeff1_8193nu = 0x00abf07a; + coeff2_2k = 0x0157ebb3; + coeff2_4k = 0x00abf5d9; + coeff2_8k = 0x0055faed; + bfsfcw_fftindex_ratio = 0x02fa; + fftindex_bfsfcw_ratio = 0x0158; + break; + case BANDWIDTH_7_MHZ: + coeff1_2048nu = 0x03227b4b; + coeff1_4096nu = 0x01913da6; + coeff1_8191nu = 0x00c8a518; + coeff1_8192nu = 0x00c89ed3; + coeff1_8193nu = 0x00c8988e; + coeff2_2k = 0x01913da6; + coeff2_4k = 0x00c89ed3; + coeff2_8k = 0x00644f69; + bfsfcw_fftindex_ratio = 0x028d; + fftindex_bfsfcw_ratio = 0x0191; + break; + case BANDWIDTH_8_MHZ: + coeff1_2048nu = 0x03951f32; + coeff1_4096nu = 0x01ca8f99; + coeff1_8191nu = 0x00e54ef7; + coeff1_8192nu = 0x00e547cc; + coeff1_8193nu = 0x00e540a2; + coeff2_2k = 0x01ca8f99; + coeff2_4k = 0x00e547cc; + coeff2_8k = 0x0072a3e6; + bfsfcw_fftindex_ratio = 0x023c; + fftindex_bfsfcw_ratio = 0x01cb; + break; + default: + ret = -EINVAL; + } + break; + case 20480000: + switch (bw) { +#if 0 /* keep */ + case BANDWIDTH_5_MHZ: + coeff1_2048nu = 0x023b6db7; + coeff1_4096nu = 0x011db6db; + coeff1_8191nu = 0x008edfe5; + coeff1_8192nu = 0x008edb6e; + coeff1_8193nu = 0x008ed6f7; + coeff2_2k = 0x011db6db; + coeff2_4k = 0x008edb6e; + coeff2_8k = 0x00476db7; + bfsfcw_fftindex_ratio = 0x0396; + fftindex_bfsfcw_ratio = 0x011e; + break; +#endif + case BANDWIDTH_6_MHZ: + coeff1_2048nu = 0x02adb6db; + coeff1_4096nu = 0x0156db6e; + coeff1_8191nu = 0x00ab7312; + coeff1_8192nu = 0x00ab6db7; + coeff1_8193nu = 0x00ab685c; + coeff2_2k = 0x0156db6e; + coeff2_4k = 0x00ab6db7; + coeff2_8k = 0x0055b6db; + bfsfcw_fftindex_ratio = 0x02fd; + fftindex_bfsfcw_ratio = 0x0157; + break; + case BANDWIDTH_7_MHZ: + coeff1_2048nu = 0x03200000; + coeff1_4096nu = 0x01900000; + coeff1_8191nu = 0x00c80640; + coeff1_8192nu = 0x00c80000; + coeff1_8193nu = 0x00c7f9c0; + coeff2_2k = 0x01900000; + coeff2_4k = 0x00c80000; + coeff2_8k = 0x00640000; + bfsfcw_fftindex_ratio = 0x028f; + fftindex_bfsfcw_ratio = 0x0190; + break; + case BANDWIDTH_8_MHZ: + coeff1_2048nu = 0x03924925; + coeff1_4096nu = 0x01c92492; + coeff1_8191nu = 0x00e4996e; + coeff1_8192nu = 0x00e49249; + coeff1_8193nu = 0x00e48b25; + coeff2_2k = 0x01c92492; + coeff2_4k = 0x00e49249; + coeff2_8k = 0x00724925; + bfsfcw_fftindex_ratio = 0x023d; + fftindex_bfsfcw_ratio = 0x01c9; + break; + default: + ret = -EINVAL; + } + break; + case 20500000: + switch (bw) { +#if 0 /* keep */ + case BANDWIDTH_5_MHZ: + coeff1_2048nu = 0x023adeff; + coeff1_4096nu = 0x011d6f80; + coeff1_8191nu = 0x008ebc36; + coeff1_8192nu = 0x008eb7c0; + coeff1_8193nu = 0x008eb34a; + coeff2_2k = 0x011d6f80; + coeff2_4k = 0x008eb7c0; + coeff2_8k = 0x00475be0; + bfsfcw_fftindex_ratio = 0x0396; + fftindex_bfsfcw_ratio = 0x011d; + break; +#endif + case BANDWIDTH_6_MHZ: + coeff1_2048nu = 0x02ad0b99; + coeff1_4096nu = 0x015685cc; + coeff1_8191nu = 0x00ab4840; + coeff1_8192nu = 0x00ab42e6; + coeff1_8193nu = 0x00ab3d8c; + coeff2_2k = 0x015685cc; + coeff2_4k = 0x00ab42e6; + coeff2_8k = 0x0055a173; + bfsfcw_fftindex_ratio = 0x02fd; + fftindex_bfsfcw_ratio = 0x0157; + break; + case BANDWIDTH_7_MHZ: + coeff1_2048nu = 0x031f3832; + coeff1_4096nu = 0x018f9c19; + coeff1_8191nu = 0x00c7d44b; + coeff1_8192nu = 0x00c7ce0c; + coeff1_8193nu = 0x00c7c7ce; + coeff2_2k = 0x018f9c19; + coeff2_4k = 0x00c7ce0c; + coeff2_8k = 0x0063e706; + bfsfcw_fftindex_ratio = 0x0290; + fftindex_bfsfcw_ratio = 0x0190; + break; + case BANDWIDTH_8_MHZ: + coeff1_2048nu = 0x039164cb; + coeff1_4096nu = 0x01c8b266; + coeff1_8191nu = 0x00e46056; + coeff1_8192nu = 0x00e45933; + coeff1_8193nu = 0x00e45210; + coeff2_2k = 0x01c8b266; + coeff2_4k = 0x00e45933; + coeff2_8k = 0x00722c99; + bfsfcw_fftindex_ratio = 0x023e; + fftindex_bfsfcw_ratio = 0x01c9; + break; + default: + ret = -EINVAL; + } + break; + case 20625000: + switch (bw) { +#if 0 /* keep */ + case BANDWIDTH_5_MHZ: + coeff1_2048nu = 0x02376948; + coeff1_4096nu = 0x011bb4a4; + coeff1_8191nu = 0x008ddec1; + coeff1_8192nu = 0x008dda52; + coeff1_8193nu = 0x008dd5e3; + coeff2_2k = 0x011bb4a4; + coeff2_4k = 0x008dda52; + coeff2_8k = 0x0046ed29; + bfsfcw_fftindex_ratio = 0x039c; + fftindex_bfsfcw_ratio = 0x011c; + break; +#endif + case BANDWIDTH_6_MHZ: + coeff1_2048nu = 0x02a8e4bd; + coeff1_4096nu = 0x0154725e; + coeff1_8191nu = 0x00aa3e81; + coeff1_8192nu = 0x00aa392f; + coeff1_8193nu = 0x00aa33de; + coeff2_2k = 0x0154725e; + coeff2_4k = 0x00aa392f; + coeff2_8k = 0x00551c98; + bfsfcw_fftindex_ratio = 0x0302; + fftindex_bfsfcw_ratio = 0x0154; + break; + case BANDWIDTH_7_MHZ: + coeff1_2048nu = 0x031a6032; + coeff1_4096nu = 0x018d3019; + coeff1_8191nu = 0x00c69e41; + coeff1_8192nu = 0x00c6980c; + coeff1_8193nu = 0x00c691d8; + coeff2_2k = 0x018d3019; + coeff2_4k = 0x00c6980c; + coeff2_8k = 0x00634c06; + bfsfcw_fftindex_ratio = 0x0294; + fftindex_bfsfcw_ratio = 0x018d; + break; + case BANDWIDTH_8_MHZ: + coeff1_2048nu = 0x038bdba6; + coeff1_4096nu = 0x01c5edd3; + coeff1_8191nu = 0x00e2fe02; + coeff1_8192nu = 0x00e2f6ea; + coeff1_8193nu = 0x00e2efd2; + coeff2_2k = 0x01c5edd3; + coeff2_4k = 0x00e2f6ea; + coeff2_8k = 0x00717b75; + bfsfcw_fftindex_ratio = 0x0242; + fftindex_bfsfcw_ratio = 0x01c6; + break; + default: + ret = -EINVAL; + } + break; + default: + err("invalid xtal freq"); + return -EINVAL; + } + if (ret) { + err("invalid bandwidth"); + return ret; + } + + /* adc multiplier */ + ret = af9033_read_reg(state, OFDM, api_adcx2, &tmp); + if (ret) + return ret; + + if (tmp == 1) { + coeff1_2048nu /= 2; + coeff1_4096nu /= 2; + coeff1_8191nu /= 2; + coeff1_8192nu /= 2; + coeff1_8193nu /= 2 ; + coeff2_2k /= 2; + coeff2_4k /= 2; + coeff2_8k /= 2; + } + + buf[i++] = (u8) ((coeff1_2048nu & 0x03000000) >> 24); + buf[i++] = (u8) ((coeff1_2048nu & 0x00ff0000) >> 16); + buf[i++] = (u8) ((coeff1_2048nu & 0x0000ff00) >> 8); + buf[i++] = (u8) ((coeff1_2048nu & 0x000000ff)); + buf[i++] = (u8) ((coeff1_4096nu & 0x03000000) >> 24); + buf[i++] = (u8) ((coeff1_4096nu & 0x00ff0000) >> 16); + buf[i++] = (u8) ((coeff1_4096nu & 0x0000ff00) >> 8); + buf[i++] = (u8) ((coeff1_4096nu & 0x000000ff)); + buf[i++] = (u8) ((coeff1_8191nu & 0x03000000) >> 24); + buf[i++] = (u8) ((coeff1_8191nu & 0x00ff0000) >> 16); + buf[i++] = (u8) ((coeff1_8191nu & 0x0000ff00) >> 8); + buf[i++] = (u8) ((coeff1_8191nu & 0x000000ff)); + buf[i++] = (u8) ((coeff1_8192nu & 0x03000000) >> 24); + buf[i++] = (u8) ((coeff1_8192nu & 0x00ff0000) >> 16); + buf[i++] = (u8) ((coeff1_8192nu & 0x0000ff00) >> 8); + buf[i++] = (u8) ((coeff1_8192nu & 0x000000ff)); + buf[i++] = (u8) ((coeff1_8193nu & 0x03000000) >> 24); + buf[i++] = (u8) ((coeff1_8193nu & 0x00ff0000) >> 16); + buf[i++] = (u8) ((coeff1_8193nu & 0x0000ff00) >> 8); + buf[i++] = (u8) ((coeff1_8193nu & 0x000000ff)); + buf[i++] = (u8) ((coeff2_8k & 0x01000000) >> 24); + buf[i++] = (u8) ((coeff2_8k & 0x00ff0000) >> 16); + buf[i++] = (u8) ((coeff2_8k & 0x0000ff00) >> 8); + buf[i++] = (u8) ((coeff2_8k & 0x000000ff)); + buf[i++] = (u8) ((coeff2_2k & 0x01000000) >> 24); + buf[i++] = (u8) ((coeff2_2k & 0x00ff0000) >> 16); + buf[i++] = (u8) ((coeff2_2k & 0x0000ff00) >> 8); + buf[i++] = (u8) ((coeff2_2k & 0x000000ff)); + buf[i++] = (u8) ((coeff2_4k & 0x01000000) >> 24); + buf[i++] = (u8) ((coeff2_4k & 0x00ff0000) >> 16); + buf[i++] = (u8) ((coeff2_4k & 0x0000ff00) >> 8); + buf[i++] = (u8) ((coeff2_4k & 0x000000ff)); + buf[i++] = (u8) ((bfsfcw_fftindex_ratio & 0x00ff)); + buf[i++] = (u8) ((bfsfcw_fftindex_ratio & 0xff00) >> 8); + buf[i++] = (u8) ((fftindex_bfsfcw_ratio & 0x00ff)); + buf[i++] = (u8) ((fftindex_bfsfcw_ratio & 0xff00) >> 8); + + deb_info("%s: coeff:", __func__); + debug_dump(buf, sizeof(buf), deb_info); + + /* program */ + return af9033_write_regs(state, OFDM, api_cfoe_NS_2048_coeff1_25_24, + buf, sizeof(buf)); +} + +static int af9033_set_crystal_ctrl(struct af9033_state *state) +{ + u8 buf[4]; + u32 crystal_cw; + deb_info("%s: crystal_clock:%d\n", __func__, + state->config.crystal_clock); + + crystal_cw = af913_div(state->config.crystal_clock, 1000000ul, 19ul); + + buf[0] = (u8) ((crystal_cw & 0x000000ff)); + buf[1] = (u8) ((crystal_cw & 0x0000ff00) >> 8); + buf[2] = (u8) ((crystal_cw & 0x00ff0000) >> 16); + buf[3] = (u8) ((crystal_cw & 0xff000000) >> 24); + + deb_info("%s: crystal_cw:", __func__); + debug_dump(buf, sizeof(buf), deb_info); + + /* program */ + return af9033_write_regs(state, OFDM, api_crystal_clk_7_0, buf, + sizeof(buf)); +} + +static int af9033_set_adc_ctrl(struct af9033_state *state) +{ + u8 buf[3]; + u32 adc_cw; + deb_info("%s: adc_clock:%d\n", __func__, state->config.adc_clock); + + adc_cw = af913_div(state->config.adc_clock, 1000000ul, 19ul); + + buf[0] = (u8) ((adc_cw & 0x000000ff)); + buf[1] = (u8) ((adc_cw & 0x0000ff00) >> 8); + buf[2] = (u8) ((adc_cw & 0x00ff0000) >> 16); + + deb_info("%s: adc_cw:", __func__); + debug_dump(buf, sizeof(buf), deb_info); + + /* program */ + return af9033_write_regs(state, OFDM, p_reg_f_adc_7_0, buf, + sizeof(buf)); +} + +static int af9033_set_freq_ctrl(struct af9033_state *state, fe_bandwidth_t bw) +{ + int ret; + u8 buf[3], tmp; + u32 adc_freq, freq_cw; + s8 bfs_spec_inv; + int if_sample_freq; + + bfs_spec_inv = state->config.rf_spec_inv ? -1 : 1; + + adc_freq = state->config.adc_clock; + if_sample_freq = state->config.if_freq; + + while (if_sample_freq > (adc_freq / 2)) + if_sample_freq = if_sample_freq - adc_freq; + + if (if_sample_freq >= 0) + bfs_spec_inv = bfs_spec_inv * (-1); + else + if_sample_freq = if_sample_freq * (-1); + + freq_cw = af913_div(if_sample_freq, adc_freq, 23ul); + + if (bfs_spec_inv == -1) + freq_cw *= -1; + + /* adc multiplier */ + ret = af9033_read_reg(state, OFDM, api_adcx2, &tmp); + if (ret) + return ret; + + if (tmp == 1) + freq_cw /= 2; + + buf[0] = (u8) ((freq_cw & 0x000000ff)); + buf[1] = (u8) ((freq_cw & 0x0000ff00) >> 8); + buf[2] = (u8) ((freq_cw & 0x007f0000) >> 16); + + deb_info("%s: freq_cw:", __func__); + debug_dump(buf, sizeof(buf), deb_info); + + /* program */ + return af9033_write_regs(state, OFDM, api_bfs_fcw_7_0, buf, + sizeof(buf)); +} +static void af9033_release(struct dvb_frontend *fe) +{ + struct af9033_state *state = fe->demodulator_priv; + kfree(state); +} + +static int af9033_init(struct dvb_frontend *fe) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret, i, len; + u8 tmp0, tmp1; + struct regdesc *init; + deb_info("%s\n", __func__); + + /* power on */ + ret = af9033_write_reg_bits(state, OFDM, p_reg_afe_mem0, 3, 1, 0); + if (ret) + goto error; + + ret = af9033_write_reg(state, OFDM, api_suspend_flag, 0); + if (ret) + goto error; + + /* tell to the firmware type of the tuner */ + ret = af9033_write_reg(state, LINK, p_reg_link_ofsm_dummy_15_8, + state->config.tuner); + if (ret) + goto error; + + /* set read-update bit for constellation */ + ret = af9033_write_reg_bits(state, OFDM, p_reg_feq_read_update, + reg_feq_read_update_pos, reg_feq_read_update_len, 1); + if (ret) + goto error; + + /* enable FEC monitor */ + ret = af9033_write_reg_bits(state, OFDM, p_fec_vtb_rsd_mon_en, + fec_vtb_rsd_mon_en_pos, fec_vtb_rsd_mon_en_len, 1); + if (ret) + goto error; + + /* program crystal control */ + ret = af9033_set_crystal_ctrl(state); + if (ret) + goto error; + + /* program ADC control */ + ret = af9033_set_adc_ctrl(state); + if (ret) + goto error; + + /* enable DVB-T interrupt */ + ret = af9033_write_reg_bits(state, LINK, p_reg_dvbt_inten, + reg_dvbt_inten_pos, reg_dvbt_inten_len, 1); + if (ret) + goto error; + + /* enable DVB-T mode */ + ret = af9033_write_reg_bits(state, LINK, p_reg_dvbt_en, + reg_dvbt_en_pos, reg_dvbt_en_len, 1); + if (ret) + goto error; + + /* set dca_upper_chip */ + ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_upper_chip, + reg_dca_upper_chip_pos, reg_dca_upper_chip_len, 0); + if (ret) + goto error; + + ret = af9033_write_reg_bits(state, LINK, p_reg_top_hostb_dca_upper, + reg_top_hostb_dca_upper_pos, reg_top_hostb_dca_upper_len, 0); + if (ret) + goto error; + + ret = af9033_write_reg_bits(state, LINK, p_reg_top_hosta_dca_upper, + reg_top_hosta_dca_upper_pos, reg_top_hosta_dca_upper_len, 0); + if (ret) + goto error; + + /* set dca_lower_chip */ + ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_lower_chip, + reg_dca_lower_chip_pos, reg_dca_lower_chip_len, 0); + if (ret) + goto error; + + ret = af9033_write_reg_bits(state, LINK, p_reg_top_hostb_dca_lower, + reg_top_hostb_dca_lower_pos, reg_top_hostb_dca_lower_len, 0); + if (ret) + goto error; + + ret = af9033_write_reg_bits(state, LINK, p_reg_top_hosta_dca_lower, + reg_top_hosta_dca_lower_pos, reg_top_hosta_dca_lower_len, 0); + if (ret) + goto error; + + /* set phase latch */ + ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_platch, + reg_dca_platch_pos, reg_dca_platch_len, 0); + if (ret) + goto error; + + /* set fpga latch */ + ret = af9033_write_reg(state, OFDM, p_reg_dca_fpga_latch, 0); + if (ret) + goto error; + + /* set stand alone */ + ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_stand_alone, + reg_dca_stand_alone_pos, reg_dca_stand_alone_len, 1); + if (ret) + goto error; + + /* set DCA enable */ + ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_en, reg_dca_en_pos, + reg_dca_en_len, 0); + if (ret) + goto error; + + /* load OFSM settings */ + deb_info("%s: load ofsm settings\n", __func__); + len = ARRAY_SIZE(ofsm_init); + init = ofsm_init; + for (i = 0; i < len; i++) { + ret = af9033_write_reg(state, OFDM, init[i].addr, init[i].val); + if (ret) + goto error; + } + + /* load tuner specific settings */ + deb_info("%s: load tuner specific settings\n", __func__); + switch (state->config.tuner) { + case AF9033_TUNER_TUA9001: + len = ARRAY_SIZE(tuner_init_tua9001); + init = tuner_init_tua9001; + break; + case AF9033_TUNER_MXL5007t: + len = ARRAY_SIZE(tuner_init_mxl5007t); + init = tuner_init_mxl5007t; + break; + default: + len = 0; + init = NULL; + break; + } + for (i = 0; i < len; i++) { + ret = af9033_write_reg(state, OFDM, init[i].addr, init[i].val); + if (ret) + goto error; + } + + /* set H/W MPEG2 locked detection **/ + ret = af9033_write_reg(state, LINK, p_reg_top_lock3_out, 1); + if (ret) + goto error; + + /* set registers for driving power */ + ret = af9033_write_reg(state, LINK, p_reg_top_padmiscdr2, 1); + if (ret) + goto error; + + /* et registers for driving power */ + ret = af9033_write_reg(state, LINK, p_reg_top_padmiscdr4, 0); + if (ret) + goto error; + + /* set registers for driving power */ + ret = af9033_write_reg(state, LINK, p_reg_top_padmiscdr8, 0); + if (ret) + goto error; + + /* set TS mode */ + deb_info("%s: setting ts mode\n", __func__); + tmp0 = 0; /* parallel mode */ + tmp1 = 0; /* serial mode */ + switch (state->config.output_mode) { + case AF9033_TS_MODE_PARALLEL: + tmp0 = 1; + break; + case AF9033_TS_MODE_SERIAL: + tmp1 = 1; + break; + case AF9033_TS_MODE_USB: + /* usb mode for AF9035 */ + default: + break; + } + ret = af9033_write_reg_bits(state, OFDM, p_mp2if_mpeg_par_mode, + mp2if_mpeg_par_mode_pos, mp2if_mpeg_par_mode_len, tmp0); + if (ret) + goto error; + ret = af9033_write_reg_bits(state, OFDM, p_mp2if_mpeg_ser_mode, + mp2if_mpeg_ser_mode_pos, mp2if_mpeg_ser_mode_len, tmp1); + if (ret) + goto error; + + if (state->config.output_mode == AF9033_TS_MODE_SERIAL) { + ret = af9033_write_reg_bits(state, LINK, p_reg_top_hostb_mpeg_ser_mode, + reg_top_hostb_mpeg_ser_mode_pos, reg_top_hostb_mpeg_ser_mode_len, 1); + if (ret) + goto error; + } +error: + if (ret) + deb_info("%s: failed:%d\n", __func__, ret); + + return ret; +} + +static int af9033_sleep(struct dvb_frontend *fe) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret; + u8 tmp, i; + deb_info("%s\n", __func__); + + ret = af9033_write_reg(state, OFDM, api_suspend_flag, 1); + if (ret) + goto error; + + ret = af9033_write_reg(state, OFDM, api_trigger_ofsm, 0); + if (ret) + goto error; + + for (i = 0; i < 150; i++) { + ret = af9033_read_reg(state, OFDM, api_suspend_flag, &tmp); + if (ret) + goto error; + if (!tmp) + break; + msleep(10); + } + if (tmp) { + deb_info("%s: power off time outs\n", __func__); + return -ETIMEDOUT; + } + + ret = af9033_write_reg_bits(state, OFDM, p_reg_afe_mem0, 3, 1, 1); + if (ret) + goto error; + + /* fixed current leakage (?) */ + if (state->config.output_mode != AF9033_TS_MODE_USB) { + /* enable parallel TS */ + ret = af9033_write_reg_bits(state, LINK, + p_reg_top_hosta_mpeg_ser_mode, + reg_top_hosta_mpeg_ser_mode_pos, + reg_top_hosta_mpeg_ser_mode_len, 0); + if (ret) + goto error; + + ret = af9033_write_reg_bits(state, LINK, + p_reg_top_hosta_mpeg_par_mode, + reg_top_hosta_mpeg_par_mode_pos, + reg_top_hosta_mpeg_par_mode_len, 1); + } + +error: + if (ret) + deb_info("%s: failed:%d\n", __func__, ret); + + return ret; +} + +static int af9033_set_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret; + u8 tmp; + deb_info("%s: freq:%d bw:%d\n", __func__, params->frequency, + params->u.ofdm.bandwidth); + + state->frequency = params->frequency; + + /* program tuner */ + if (fe->ops.tuner_ops.set_params) + fe->ops.tuner_ops.set_params(fe, params); + + /* program CFOE coefficients */ + ret = af9033_set_coeff(state, params->u.ofdm.bandwidth); + if (ret) + goto error; + + /* program frequency control */ + ret = af9033_set_freq_ctrl(state, params->u.ofdm.bandwidth); + if (ret) + goto error; + + /* program bandwidth */ + switch (params->u.ofdm.bandwidth) { + case BANDWIDTH_6_MHZ: + tmp = 0; + break; + case BANDWIDTH_7_MHZ: + tmp = 1; + break; + case BANDWIDTH_8_MHZ: + tmp = 2; + break; +#if 0 /* keep */ + case BANDWIDTH_5_MHZ: + tmp = 3; + break; +#endif + default: + deb_info("%s: invalid bandwidth\n", __func__); + return -EINVAL; + } + ret = af9033_write_reg_bits(state, OFDM, g_reg_bw, reg_bw_pos, + reg_bw_len, tmp); + if (ret) + goto error; + + /* clear easy mode flag */ + ret = af9033_write_reg(state, OFDM, api_Training_Mode, 0x00); + if (ret) + goto error; + + /* clear empty channel flag */ + ret = af9033_write_reg(state, OFDM, api_empty_channel_status, 0x00); + if (ret) + goto error; + + /* clear MPEG2 lock flag */ + ret = af9033_write_reg_bits(state, OFDM, r_mp2if_sync_byte_locked, + mp2if_sync_byte_locked_pos, mp2if_sync_byte_locked_len, 0x00); + if (ret) + goto error; + + /* set frequency band + 174 - 230 MHz VHF band = 0x00 + 350 - 900 MHz UHF band = 0x01 + 1670 - 1680 MHz L-BAND band = 0x02 + otherwise band = 0xff */ + /* TODO: are both min/max ranges really required... */ + if ((state->frequency >= 174000000) && (state->frequency <= 230000000)) + tmp = 0x00; /* VHF */ + else if ((state->frequency >= 350000000) && (state->frequency <= 900000000)) + tmp = 0x01; /* UHF */ + else if ((state->frequency >= 1670000000) && (state->frequency <= 1680000000)) + tmp = 0x02; /* L-BAND */ + else + tmp = 0xff; + + ret = af9033_write_reg(state, OFDM, api_FreBand, tmp); + if (ret) + goto error; + + /* trigger ofsm */ + ret = af9033_write_reg(state, OFDM, api_trigger_ofsm, 0); + if (ret) + goto error; +error: + if (ret) + deb_info("%s: failed:%d\n", __func__, ret); + + return ret; +} + +static int af9033_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *fesettings) +{ + fesettings->min_delay_ms = 800; + fesettings->step_size = 0; + fesettings->max_drift = 0; + + return 0; +} + +static int af9033_get_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret; + u8 buf[8]; + deb_info("%s\n", __func__); +#define TRANSMISSION_MODE (g_reg_tpsd_txmod - g_reg_tpsd_txmod) +#define GUARD_INTERVAL (g_reg_tpsd_gi - g_reg_tpsd_txmod) +#define HIERARCHY (g_reg_tpsd_hier - g_reg_tpsd_txmod) +#define CONSTELLATION (g_reg_tpsd_const - g_reg_tpsd_txmod) +#define BANDWIDTH (g_reg_bw - g_reg_tpsd_txmod) +#define PRIORITY (g_reg_dec_pri - g_reg_tpsd_txmod) +#define CODE_RATE_HP (g_reg_tpsd_hpcr - g_reg_tpsd_txmod) +#define CODE_RATE_LP (g_reg_tpsd_lpcr - g_reg_tpsd_txmod) + + /* read all needed registers */ + ret = af9033_read_regs(state, OFDM, g_reg_tpsd_txmod, buf, sizeof(buf)); + if (ret) + goto error; + + deb_info("%s: ", __func__); + debug_dump(buf, sizeof(buf), deb_info); + + switch ((buf[CONSTELLATION] >> 0) & 3) { + case 0: + p->u.ofdm.constellation = QPSK; + break; + case 1: + p->u.ofdm.constellation = QAM_16; + break; + case 2: + p->u.ofdm.constellation = QAM_64; + break; + } + + switch ((buf[TRANSMISSION_MODE] >> 0) & 3) { + case 0: + p->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; + break; + case 1: + p->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; + break; +#if 0 /* keep */ + case 2: + p->u.ofdm.transmission_mode = TRANSMISSION_MODE_4K; + break; +#endif + } + + switch ((buf[GUARD_INTERVAL] >> 0) & 3) { + case 0: + p->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; + break; + case 1: + p->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; + break; + case 2: + p->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; + break; + case 3: + p->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; + break; + } + + switch ((buf[HIERARCHY] >> 0) & 7) { + case 0: + p->u.ofdm.hierarchy_information = HIERARCHY_NONE; + break; + case 1: + p->u.ofdm.hierarchy_information = HIERARCHY_1; + break; + case 2: + p->u.ofdm.hierarchy_information = HIERARCHY_2; + break; + case 3: + p->u.ofdm.hierarchy_information = HIERARCHY_4; + break; + } + + switch ((buf[CODE_RATE_HP] >> 0) & 7) { + case 0: + p->u.ofdm.code_rate_HP = FEC_1_2; + break; + case 1: + p->u.ofdm.code_rate_HP = FEC_2_3; + break; + case 2: + p->u.ofdm.code_rate_HP = FEC_3_4; + break; + case 3: + p->u.ofdm.code_rate_HP = FEC_5_6; + break; + case 4: + p->u.ofdm.code_rate_HP = FEC_7_8; + break; + case 5: + p->u.ofdm.code_rate_HP = FEC_NONE; + break; + } + + switch ((buf[CODE_RATE_LP] >> 0) & 7) { + case 0: + p->u.ofdm.code_rate_LP = FEC_1_2; + break; + case 1: + p->u.ofdm.code_rate_LP = FEC_2_3; + break; + case 2: + p->u.ofdm.code_rate_LP = FEC_3_4; + break; + case 3: + p->u.ofdm.code_rate_LP = FEC_5_6; + break; + case 4: + p->u.ofdm.code_rate_LP = FEC_7_8; + break; + case 5: + p->u.ofdm.code_rate_HP = FEC_NONE; + break; + } + + switch ((buf[BANDWIDTH] >> 0) & 3) { + case 0: + p->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; + break; + case 1: + p->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; + break; + case 2: + p->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; + break; +#if 0 /* keep */ + case 3: + p->u.ofdm.bandwidth = BANDWIDTH_5_MHZ; + break; +#endif + } + + p->inversion = INVERSION_AUTO; + p->frequency = state->frequency; + +error: + if (ret) + deb_info("%s: failed:%d\n", __func__, ret); + + return ret; +} + +static int af9033_update_ber_ucblocks(struct dvb_frontend *fe) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret; + u8 buf[3]; + u32 error_bit_count = 0; + u32 total_bit_count = 0; + u16 abort_packet_count = 0; + + /* don't update ber / ucblocks unnecessary often */ + if (time_before(jiffies, state->next_statistics_check)) + return 0; + + /* set minimum ber / ucblocks update interval */ + state->next_statistics_check = jiffies + msecs_to_jiffies(500); + + state->ber = 0; + + /* no need to check ber / ucblocks in case of no lock */ + ret = af9033_read_reg_bits(state, OFDM, + r_mp2if_sync_byte_locked, mp2if_sync_byte_locked_pos, + mp2if_sync_byte_locked_len, buf); + if (ret) + goto error; + if (!buf[0]) + goto exit; + + /* get abort packet count */ + ret = af9033_read_regs(state, OFDM, api_rsd_abort_packet_cnt_7_0, buf, + sizeof(buf) - 1); + if (ret) + goto error; + + abort_packet_count = (buf[1] << 8) + buf[0]; + + /* get error bit count */ + ret = af9033_read_regs(state, OFDM, api_rsd_bit_err_cnt_7_0, buf, + sizeof(buf)); + if (ret) + goto error; + + error_bit_count = (buf[2] << 16) + (buf[1] << 8) + buf[0]; + error_bit_count = error_bit_count - abort_packet_count * 8 * 8; + + /* get used RSD counting period (it is 10000 by defaut) */ + ret = af9033_read_regs(state, OFDM, api_r_rsd_packet_unit_7_0, buf, + sizeof(buf) - 1); + if (ret) + goto error; + + total_bit_count = (buf[1] << 8) + buf[0]; + total_bit_count = total_bit_count - abort_packet_count; + total_bit_count = total_bit_count * 204 * 8; + + if (total_bit_count) + state->ber = error_bit_count * 1000000000 / total_bit_count; + + state->ucblocks += abort_packet_count; + + deb_info("%s: err bits:%d total bits:%d abort count:%d\n", __func__, + error_bit_count, total_bit_count, abort_packet_count); + +error: + if (ret) + deb_info("%s: failed:%d\n", __func__, ret); +exit: + return ret; +} + +static int af9033_update_snr(struct dvb_frontend *fe) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret; + u8 buf[3], i, len; + u32 snr_val; + struct snr_table *uninitialized_var(snr_table); + + /* read snr registers */ + ret = af9033_read_regs(state, OFDM, api_qnt_vbc_err_7_0, buf, + sizeof(buf)); + if (ret) + goto error; + snr_val = (buf[2] << 16) + (buf[1] << 8) + buf[0]; + + /* read current constellation */ + ret = af9033_read_reg_bits(state, OFDM, g_reg_tpsd_const, + reg_tpsd_const_pos, reg_tpsd_const_len, &buf[0]); + if (ret) + goto error; + + switch (buf[0]) { + case 0: + len = ARRAY_SIZE(qpsk_snr_table); + snr_table = qpsk_snr_table; + break; + case 1: + len = ARRAY_SIZE(qam16_snr_table); + snr_table = qam16_snr_table; + break; + case 2: + len = ARRAY_SIZE(qam64_snr_table); + snr_table = qam64_snr_table; + break; + default: + len = 0; + } + + /* get snr from lookup table */ + for (i = 0; i < len; i++) { + if (snr_val < snr_table[i].val) { + state->snr = snr_table[i].snr * 10; + break; + } + } + deb_info("%s: snr_val:%x snr:%x\n", __func__, snr_val, state->snr); + +error: + return ret; +} + +static int af9033_update_signal_strength(struct dvb_frontend *fe) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret; + u8 strength; + + /* read signal strength from 0-100 scale */ + ret = af9033_read_reg(state, OFDM, api_signal_strength, &strength); + if (ret) + goto error; + + /* scale value to 0x0000-0xffff */ + state->signal_strength = strength * 0xffff / 100; + +error: + return ret; +} + +static int af9033_read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret = 0; + u8 tmp; + *status = 0; + + /* empty channel; 0:no result, 1:signal, 2:empty */ + ret = af9033_read_reg(state, OFDM, api_empty_channel_status, &tmp); + if (ret) + goto error; + if (tmp == 0x01) /* have signal */ + *status |= FE_HAS_SIGNAL; + + if (tmp != 0x02) { + /* TPS lock */ + ret = af9033_read_reg_bits(state, OFDM, p_fd_tpsd_lock, + fd_tpsd_lock_pos, fd_tpsd_lock_len, &tmp); + if (ret) + goto error; + if (tmp) + *status |= FE_HAS_VITERBI | FE_HAS_CARRIER; + + /* MPEG2 lock */ + ret = af9033_read_reg_bits(state, OFDM, + r_mp2if_sync_byte_locked, mp2if_sync_byte_locked_pos, + mp2if_sync_byte_locked_len, &tmp); + if (ret) + goto error; + if (tmp) + *status |= FE_HAS_SYNC | FE_HAS_LOCK; + } + + /* update ber / ucblocks */ + ret = af9033_update_ber_ucblocks(fe); + +error: + if (ret) + deb_info("%s: failed:%d\n", __func__, ret); + + return ret; +} + +static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret; + deb_info("%s\n", __func__); + ret = af9033_update_ber_ucblocks(fe); + *ber = state->ber; + return ret; +} + +static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret; + deb_info("%s\n", __func__); + ret = af9033_update_signal_strength(fe); + if (ret) + goto error; + ret = af9033_update_ber_ucblocks(fe); + *strength = state->signal_strength; +error: + return ret; +} + +static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret; + deb_info("%s\n", __func__); + ret = af9033_update_snr(fe); + if (ret) + goto error; + ret = af9033_update_ber_ucblocks(fe); + *snr = state->snr; +error: + return ret; +} + +static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret; + deb_info("%s\n", __func__); + ret = af9033_update_ber_ucblocks(fe); + *ucblocks = state->ucblocks; + return ret; +} + +static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct af9033_state *state = fe->demodulator_priv; + deb_info("%s: enable:%d\n", __func__, enable); + + return af9033_write_reg_bits(state, LINK, p_reg_bypass_host2tuner, + reg_bypass_host2tuner_pos, reg_bypass_host2tuner_len, enable); +} + +static struct dvb_frontend_ops af9033_ops; + +struct dvb_frontend *af9033_attach(const struct af9033_config *config, + struct i2c_adapter *i2c) +{ + int ret; + struct af9033_state *state = NULL; + u8 buf[8]; + deb_info("%s:\n", __func__); + + /* allocate memory for the internal state */ + state = kzalloc(sizeof(struct af9033_state), GFP_KERNEL); + if (state == NULL) + goto error; + + /* setup the state */ + state->i2c = i2c; + memcpy(&state->config, config, sizeof(struct af9033_config)); + + /* firmware version */ + ret = af9033_read_regs(state, LINK, 0x83e9, &buf[0], sizeof(buf) / 2); + if (ret) + goto error; + + ret = af9033_read_regs(state, OFDM, 0x4191, &buf[4], sizeof(buf) / 2); + if (ret) + goto error; + + info("firmware version: LINK:%d.%d.%d.%d OFDM:%d.%d.%d.%d", + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); + + /* settings for mp2if */ + if (state->config.output_mode == AF9033_TS_MODE_USB) { + /* split 15 PSB to 1K + 1K and enable flow control */ + ret = af9033_write_reg_bits(state, OFDM, p_reg_mp2if2_half_psb, + reg_mp2if2_half_psb_pos, reg_mp2if2_half_psb_len, 0); + if (ret) + goto error; + ret = af9033_write_reg_bits(state, OFDM, p_reg_mp2if_stop_en, + reg_mp2if_stop_en_pos, reg_mp2if_stop_en_len, 1); + } else { + /* AF9033 set mpeg to full speed */ + ret = af9033_write_reg_bits(state, OFDM, p_reg_mpeg_full_speed, + reg_mpeg_full_speed_pos, reg_mpeg_full_speed_len, 0); + if (ret) + goto error; + ret = af9033_write_reg_bits(state, OFDM, p_reg_mp2if_stop_en, + reg_mp2if_stop_en_pos, reg_mp2if_stop_en_len, 0); + } + if (ret) + goto error; + + /* set to 0 as open drain for tuner i2c */ + ret = af9033_write_reg(state, LINK, p_reg_top_padodpu, 0); + if (ret) + goto error; + + /* set to 0 as push pull for tuner AGC */ + ret = af9033_write_reg(state, LINK, p_reg_top_agc_od, 0); + if (ret) + goto error; + + /* create dvb_frontend */ + memcpy(&state->frontend.ops, &af9033_ops, + sizeof(struct dvb_frontend_ops)); + state->frontend.demodulator_priv = state; + + return &state->frontend; +error: + kfree(state); + return NULL; +} +EXPORT_SYMBOL(af9033_attach); + +static struct dvb_frontend_ops af9033_ops = { + .info = { + .name = "Afatech AF9033 DVB-T", + .type = FE_OFDM, + .frequency_min = 44250000, + .frequency_max = 867250000, + .frequency_stepsize = 62500, + .frequency_tolerance = 0, + .caps = + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | + FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_QPSK | FE_CAN_QAM_16 | + FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | + FE_CAN_HIERARCHY_AUTO | + FE_CAN_RECOVER | + FE_CAN_MUTE_TS + }, + + .release = af9033_release, + + .init = af9033_init, + .sleep = af9033_sleep, + + .set_frontend = af9033_set_frontend, + .get_tune_settings = af9033_get_tune_settings, + + .get_frontend = af9033_get_frontend, + + .read_status = af9033_read_status, + .read_ber = af9033_read_ber, + .read_signal_strength = af9033_read_signal_strength, + .read_snr = af9033_read_snr, + .read_ucblocks = af9033_read_ucblocks, + + .i2c_gate_ctrl = af9033_i2c_gate_ctrl, +}; + +MODULE_AUTHOR("Antti Palosaari "); +MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver"); +MODULE_LICENSE("GPL"); diff -r 37581bb7e6f1 linux/drivers/media/dvb/frontends/af9033.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/linux/drivers/media/dvb/frontends/af9033.h Sat Feb 27 16:17:22 2010 +0100 @@ -0,0 +1,99 @@ +/* + * Afatech AF9033 demodulator driver + * + * Copyright (C) 2008 Afatech + * Copyright (C) 2009 Antti Palosaari + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Thanks to TerraTec for a support received. + */ + +#ifndef AF9033_H +#define AF9033_H + +#include + +enum af9033_ts_mode { + AF9033_TS_MODE_PARALLEL, + AF9033_TS_MODE_SERIAL, + AF9033_TS_MODE_USB, /* only for AF9035 */ +}; + +enum af9033_tuner { + AF9033_TUNER_TUA9001 = 0x27, /* Infineon TUA 9001 */ + AF9033_TUNER_FC0011 = 0x28, /* Fitipower FC0011 */ + AF9033_TUNER_MXL5007t = 0xa0, /* Maxlinear MXL5007t */ +}; + +/* clock setting table: + ================================= + adc_clock crystal_clock Xtal + ================================= + 20480000 20480000 FPGA + 16384000 20480000 16.38MHz + 20480000 20480000 20.48MHz + 36000000 20250000 36.00MHz + 30000000 20156250 30.00MHz + 26000000 20583333 26.00MHz + 28000000 20416667 28.00MHz + 32000000 20500000 32.00MHz + 34000000 20187500 34.00MHz + 24000000 20500000 24.00MHz + 22000000 20625000 22.00MHz + 12000000 20250000 12.00MHz +*/ + +struct af9033_config { + /* demodulator's I2C address */ + u8 demod_address; + + u8 tuner_address; + + /* xtal clock Hz */ + u32 crystal_clock; + + /* ADC clock Hz */ + u32 adc_clock; + + /* tuner ID */ + u8 tuner; + + /* intermediate frequency Hz */ + u32 if_freq; + + /* TS data output mode */ + u8 output_mode:2; + + /* RF spectrum inversion */ + u8 rf_spec_inv:1; +}; + + +#if defined(CONFIG_DVB_AF9033) || \ + (defined(CONFIG_DVB_AF9033_MODULE) && defined(MODULE)) +extern struct dvb_frontend *af9033_attach(const struct af9033_config *config, + struct i2c_adapter *i2c); +#else +static inline struct dvb_frontend *af9033_attach( +const struct af9033_config *config, struct i2c_adapter *i2c) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif /* CONFIG_DVB_AF9033 */ + +#endif /* AF9033_H */ diff -r 37581bb7e6f1 linux/drivers/media/dvb/frontends/af9033_priv.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/linux/drivers/media/dvb/frontends/af9033_priv.h Sat Feb 27 16:17:22 2010 +0100 @@ -0,0 +1,342 @@ +/* + * Afatech AF9033 demodulator driver + * + * Copyright (C) 2008 Afatech + * Copyright (C) 2009 Antti Palosaari + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Thanks to TerraTec for a support received. + */ + +#ifndef AF9033_PRIV_H +#define AF9033_PRIV_H + +#define LOG_PREFIX "af9033" + +#define dprintk(var, level, args...) \ + do { if ((var & level)) printk(args); } while (0) + +#define debug_dump(b, l, func) {\ + int loop_; \ + for (loop_ = 0; loop_ < l; loop_++) \ + func("%02x ", b[loop_]); \ + func("\n");\ +} + +#define deb_info(args...) dprintk(af9033_debug, 0x01, args) + +#undef err +#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg) +#undef info +#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg) +#undef warn +#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg) + +#define LINK 0x00 +#define OFDM 0x80 + +struct regdesc { + u16 addr; + u8 val; +}; + +struct snr_table { + u32 val; + u8 snr; +}; + +/* QPSK SNR lookup table */ +static struct snr_table qpsk_snr_table[] = { + {0x000b4771, 0}, + {0x000c1aed, 1}, + {0x000d0d27, 2}, + {0x000e4d19, 3}, + {0x000e5da8, 4}, + {0x00107097, 5}, + {0x00116975, 6}, + {0x001252d9, 7}, + {0x00131fa4, 8}, + {0x0013d5e1, 9}, + {0x00148e53, 10}, + {0x0015358b, 11}, + {0x0015dd29, 12}, + {0x00168112, 13}, + {0x00170b61, 14}, + {0x0017a532, 15}, + {0x00180f94, 16}, + {0x00186ed2, 17}, + {0x0018b271, 18}, + {0x0018e118, 19}, + {0x0018ff4b, 20}, + {0x00190af1, 21}, + {0x00191451, 22}, + {0xffffffff, 23}, +}; + +/* QAM16 SNR lookup table */ +static struct snr_table qam16_snr_table[] = { + {0x0004f0d5, 0}, + {0x0005387a, 1}, + {0x000573a4, 2}, + {0x0005a99e, 3}, + {0x0005cc80, 4}, + {0x0005eb62, 5}, + {0x0005fecf, 6}, + {0x00060b80, 7}, + {0x00062501, 8}, + {0x00064865, 9}, + {0x00069604, 10}, + {0x0006f356, 11}, + {0x0007706a, 12}, + {0x000804d3, 13}, + {0x00089d1a, 14}, + {0x00093e3d, 15}, + {0x0009e35d, 16}, + {0x000a7c3c, 17}, + {0x000afaf8, 18}, + {0x000b719d, 19}, + {0x000bda6a, 20}, + {0x000c0c75, 21}, + {0x000c3f7d, 22}, + {0x000c5e62, 23}, + {0x000c6c31, 24}, + {0x000c7925, 25}, + {0xffffffff, 26}, +}; + +/* QAM64 SNR lookup table */ +static struct snr_table qam64_snr_table[] = { + {0x000256d0, 0}, + {0x00027a65, 1}, + {0x00029873, 2}, + {0x0002b7fe, 3}, + {0x0002cf1e, 4}, + {0x0002e234, 5}, + {0x0002f409, 6}, + {0x00030046, 7}, + {0x00030844, 8}, + {0x00030a02, 9}, + {0x00030cde, 10}, + {0x00031031, 11}, + {0x0003144c, 12}, + {0x000315dd, 13}, + {0x00031920, 14}, + {0x000322d0, 15}, + {0x000339fc, 16}, + {0x000364a1, 17}, + {0x00038bcc, 18}, + {0x0003c7d3, 19}, + {0x000408cc, 20}, + {0x00043bed, 21}, + {0x00048061, 22}, + {0x0004be95, 23}, + {0x0004fa7d, 24}, + {0x00052405, 25}, + {0x0005570d, 26}, + {0x00059feb, 27}, + {0x0005bf38, 28}, + {0xffffffff, 29}, +}; + +static struct regdesc ofsm_init[] = { + {0x0051, 0x01}, + {0x0070, 0x0A}, + {0x007E, 0x04}, + {0x0081, 0x0A}, + {0x008A, 0x01}, + {0x008E, 0x01}, + {0x0092, 0x06}, + {0x0099, 0x01}, + {0x009F, 0xE1}, + {0x00A0, 0xCF}, + {0x00A3, 0x01}, + {0x00A5, 0x01}, + {0x00A6, 0x01}, + {0x00A9, 0x00}, + {0x00AA, 0x01}, + {0x00AB, 0x01}, + {0x00B0, 0x01}, + {0x00C0, 0x05}, + {0x00C4, 0x19}, + {0xF000, 0x0F}, + {0xF016, 0x10}, + {0xF017, 0x04}, + {0xF018, 0x05}, + {0xF019, 0x04}, + {0xF01A, 0x05}, + {0xF021, 0x03}, + {0xF022, 0x0A}, + {0xF023, 0x0A}, + {0xF02B, 0x00}, + {0xF02C, 0x01}, + {0xF064, 0x03}, + {0xF065, 0xF9}, + {0xF066, 0x03}, + {0xF067, 0x01}, + {0xF06F, 0xE0}, + {0xF070, 0x03}, + {0xF072, 0x0F}, + {0xF073, 0x03}, + {0xF078, 0x00}, + {0xF087, 0x00}, + {0xF09B, 0x3F}, + {0xF09C, 0x00}, + {0xF09D, 0x20}, + {0xF09E, 0x00}, + {0xF09F, 0x0C}, + {0xF0A0, 0x00}, + {0xF130, 0x04}, + {0xF132, 0x04}, + {0xF144, 0x1A}, + {0xF146, 0x00}, + {0xF14A, 0x01}, + {0xF14C, 0x00}, + {0xF14D, 0x00}, + {0xF14F, 0x04}, + {0xF158, 0x7F}, + {0xF15A, 0x00}, + {0xF15B, 0x08}, + {0xF15D, 0x03}, + {0xF15E, 0x05}, + {0xF163, 0x05}, + {0xF166, 0x01}, + {0xF167, 0x40}, + {0xF168, 0x0F}, + {0xF17A, 0x00}, + {0xF17B, 0x00}, + {0xF183, 0x01}, + {0xF19D, 0x40}, + {0xF1BC, 0x36}, + {0xF1BD, 0x00}, + {0xF1CB, 0xA0}, + {0xF1CC, 0x01}, + {0xF204, 0x10}, + {0xF214, 0x00}, + {0xF40E, 0x0A}, + {0xF40F, 0x40}, + {0xF410, 0x08}, + {0xF55F, 0x0A}, + {0xF561, 0x15}, + {0xF562, 0x20}, + {0xF5DF, 0xFB}, + {0xF5E0, 0x00}, + {0xF5E3, 0x09}, + {0xF5E4, 0x01}, + {0xF5E5, 0x01}, + {0xF5F8, 0x01}, + {0xF5FD, 0x01}, + {0xF600, 0x05}, + {0xF601, 0x08}, + {0xF602, 0x0B}, + {0xF603, 0x0E}, + {0xF604, 0x11}, + {0xF605, 0x14}, + {0xF606, 0x17}, + {0xF607, 0x1F}, + {0xF60E, 0x00}, + {0xF60F, 0x04}, + {0xF610, 0x32}, + {0xF611, 0x10}, + {0xF707, 0xFC}, + {0xF708, 0x00}, + {0xF709, 0x37}, + {0xF70A, 0x00}, + {0xF78B, 0x01}, + {0xF80F, 0x40}, + {0xF810, 0x54}, + {0xF811, 0x5A}, + {0xF905, 0x01}, + {0xFB06, 0x03}, + {0xFD8B, 0x00} +}; + +/* Infineon TUA 9001 tuner init + AF9033_TUNER_TUA9001 = 0x27 */ +static struct regdesc tuner_init_tua9001[] = { + {0x0046, 0x27}, + {0x0057, 0x00}, + {0x0058, 0x01}, + {0x005f, 0x00}, + {0x0060, 0x00}, + {0x006d, 0x00}, + {0x0071, 0x05}, + {0x0072, 0x02}, + {0x0074, 0x01}, + {0x0075, 0x03}, + {0x0076, 0x02}, + {0x0077, 0x00}, + {0x0078, 0x01}, + {0x0079, 0x00}, + {0x007a, 0x7E}, + {0x007b, 0x3E}, + {0x0093, 0x00}, + {0x0094, 0x01}, + {0x0095, 0x02}, + {0x0096, 0x01}, + {0x0098, 0x0A}, + {0x009b, 0x05}, + {0x009c, 0x80}, + {0x00b3, 0x00}, + {0x00c1, 0x01}, + {0x00c2, 0x00}, + {0xF007, 0x00}, + {0xF01F, 0x82}, + {0xF020, 0x00}, + {0xF029, 0x82}, + {0xF02A, 0x00}, + {0xF047, 0x00}, + {0xF054, 0x00}, + {0xF055, 0x00}, + {0xF077, 0x01}, + {0xF1E6, 0x00}, +}; + +static struct regdesc tuner_init_mxl5007t[] = { + {0x0046, 0x1b}, + {0x0057, 0x01}, + {0x0058, 0x01}, + {0x005f, 0x00}, + {0x0060, 0x00}, + {0x0068, 0x96}, + {0x0071, 0x05}, + {0x0072, 0x02}, + {0x0074, 0x01}, + {0x0079, 0x01}, + {0x0093, 0x00}, + {0x0094, 0x00}, + {0x0095, 0x00}, + {0x0096, 0x00}, + {0x00b3, 0x01}, + {0x00c1, 0x01}, + {0x00c2, 0x00}, + {0xF007, 0x00}, + {0xF00C, 0x19}, + {0xF00D, 0x1a}, + {0xF012, 0xda}, + {0xF013, 0x00}, + {0xF014, 0x00}, + {0xF015, 0x02}, + {0xF01F, 0x82}, + {0xF020, 0x00}, + {0xF029, 0x82}, + {0xF02A, 0x00}, + {0xF077, 0x02}, + {0xF1E6, 0x00}, +}; + +#endif /* AF9033_PRIV_H */ + diff -r 37581bb7e6f1 linux/drivers/media/dvb/frontends/af9033_reg.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/linux/drivers/media/dvb/frontends/af9033_reg.h Sat Feb 27 16:17:22 2010 +0100 @@ -0,0 +1,11006 @@ +/* + * Afatech AF9033 demodulator driver + * + * Copyright (C) 2008 Afatech + * Copyright (C) 2009 Antti Palosaari + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Thanks to TerraTec for a support received. + */ + +#ifndef AF9033_REG_H +#define AF9033_REG_H + +/* these variables are initialized by API */ +#define api_var_addr_base 0x418b +#define api_log_addr_base 0x418d +#define api_log_data_base 0x418f +#define api_LowerLocalRetrain 0x43bb + +#define api_trigger_ofsm 0x0000 +#define api_cfoe_NS_2048_coeff1_25_24 0x0001 +#define api_cfoe_NS_2048_coeff1_23_16 0x0002 +#define api_cfoe_NS_2048_coeff1_15_8 0x0003 +#define api_cfoe_NS_2048_coeff1_7_0 0x0004 +#define api_cfoe_NS_2k_coeff2_24 0x0005 +#define api_cfoe_NS_2k_coeff2_23_16 0x0006 +#define api_cfoe_NS_2k_coeff2_15_8 0x0007 +#define api_cfoe_NS_2k_coeff2_7_0 0x0008 +#define api_cfoe_NS_8191_coeff1_25_24 0x0009 +#define api_cfoe_NS_8191_coeff1_23_16 0x000a +#define api_cfoe_NS_8191_coeff1_15_8 0x000b +#define api_cfoe_NS_8191_coeff1_7_0 0x000c +#define api_cfoe_NS_8192_coeff1_25_24 0x000d +#define api_cfoe_NS_8192_coeff1_23_16 0x000e +#define api_cfoe_NS_8192_coeff1_15_8 0x000f +#define api_cfoe_NS_8192_coeff1_7_0 0x0010 +#define api_cfoe_NS_8193_coeff1_25_24 0x0011 +#define api_cfoe_NS_8193_coeff1_23_16 0x0012 +#define api_cfoe_NS_8193_coeff1_15_8 0x0013 +#define api_cfoe_NS_8193_coeff1_7_0 0x0014 +#define api_cfoe_NS_8k_coeff2_24 0x0015 +#define api_cfoe_NS_8k_coeff2_23_16 0x0016 +#define api_cfoe_NS_8k_coeff2_15_8 0x0017 +#define api_cfoe_NS_8k_coeff2_7_0 0x0018 +#define api_cfoe_NS_4096_coeff1_25_24 0x0019 +#define api_cfoe_NS_4096_coeff1_23_16 0x001a +#define api_cfoe_NS_4096_coeff1_15_8 0x001b +#define api_cfoe_NS_4096_coeff1_7_0 0x001c +#define api_cfoe_NS_4k_coeff2_24 0x001d +#define api_cfoe_NS_4k_coeff2_23_16 0x001e +#define api_cfoe_NS_4k_coeff2_15_8 0x001f +#define api_cfoe_NS_4k_coeff2_7_0 0x0020 + +#define api_bfsfcw_fftindex_ratio_7_0 0x0021 +#define api_bfsfcw_fftindex_ratio_15_8 0x0022 +#define api_fftindex_bfsfcw_ratio_7_0 0x0023 +#define api_fftindex_bfsfcw_ratio_15_8 0x0024 + +#define api_crystal_clk_7_0 0x0025 +#define api_crystal_clk_15_8 0x0026 +#define api_crystal_clk_23_16 0x0027 +#define api_crystal_clk_31_24 0x0028 + +#define api_bfs_fcw_7_0 0x0029 +#define api_bfs_fcw_15_8 0x002a +#define api_bfs_fcw_22_16 0x002b + +#define api_qnt_vbc_err_7_0 0x002c +#define api_qnt_vbc_err_15_8 0x002d +#define api_qnt_vbc_err_23_16 0x002e +#define api_r_qnt_vbc_sframe_num 0x002f +#define api_tpsd_const 0x0030 +#define api_tpsd_txmod 0x0031 + +#define api_rsd_abort_packet_cnt_7_0 0x0032 +#define api_rsd_abort_packet_cnt_15_8 0x0033 +#define api_rsd_bit_err_cnt_7_0 0x0034 +#define api_rsd_bit_err_cnt_15_8 0x0035 +#define api_rsd_bit_err_cnt_23_16 0x0036 +#define api_r_rsd_packet_unit_7_0 0x0037 +#define api_r_rsd_packet_unit_15_8 0x0038 + +#define api_qnt_vbc_sframe_num 0x0039 +#define api_rsd_packet_unit_7_0 0x003a +#define api_rsd_packet_unit_15_8 0x003b + +#define api_tpsd_lock 0x003c +#define api_mpeg_lock 0x003d +#define api_RsdSequence 0x003e +#define api_VtbSequence 0x003f + +#define api_Training_Mode 0x0040 +#define api_RESET_STATE 0x0041 +#define api_EXT_LNA_OFF 0x0042 +#define api_aci_0 0x0043 +#define api_aci_1 0x0044 + +#define api_adcx2 0x0045 +#define api_tuner_ID 0x0046 +#define api_empty_channel_status 0x0047 +#define api_signal_strength 0x0048 +#define api_signal_quality 0x0049 +#define api_est_rf_level_dbm 0x004a +#define api_FreBand 0x004b +#define api_suspend_flag 0x004c +#define api_SupportRelayCommandWrite 0x004d +#define api_RelayCommandWrite 0x004e + +#define api_OfdmGuiRCN_H 0x004f +#define api_OfdmGuiRCN_L 0x0050 +#define api_antenna_unplugged 0x0051 +#define api_strong_signal_detected 0x0052 +#define api_channelFlatnessInd 0x0053 +#define api_Flatness_Ind_nonCmb 0x0054 +#define api_AutoDetectedSpectrumInv 0x0055 +#define api_IsSpectrumInv 0x0056 +#define api_strong_detect_bypass 0x0057 +#define api_ss_dtop_bypass 0x0058 +#define api_retrain_dtop_bypass 0x0059 +#define api_EnableTimeSlice 0x005a +#define api_SynchronizationType 0x005b +#define api_ApplyFastSynchronizationToEchoChannel 0x005c +#define api_ApplyPwmToRfIf 0x005d +#define api_ChannelNo 0x005e + +#define api_csi_bypass 0x005f +#define api_mobile_bypass 0x0060 +#define api_EnableSpeedLog 0x0061 + +#define api_r_rsd_abort_total_packet_7_0 0x0062 +#define api_r_rsd_abort_total_packet_15_8 0x0063 +#define api_r_rsd_abort_total_packet_23_16 0x0064 +#define api_MaxRsdSequence 0x0065 +#define api_RsdFrameNo 0x0066 +#define api_MPESuperFrameNo 0x0067 + +#define api_AgcDesiredLevel 0x0068 +#define api_MinRfGain 0x0069 +#define api_MaxIfGain 0x006a +#define api_RssiOffset 0x006b +#define api_RssiResidual 0x006c + +#define api_strong_weak_signal_default 0x006d +#define api_PionDiodeDefaultResetInVHF 0x006e +#define api_afe_mem4_rssi_comp 0x006f + +#define api_aagc_speed_detect_count 0x0070 +#define api_aagc_mobile_thr 0x0071 +#define api_aagc_nonmobile_thr 0x0072 +#define api_agc_counter 0x0073 +#define api_DisableAagcTop 0x0074 +#define api_AgcReset 0x0075 +#define api_AgcUp 0x0076 +#define api_AgcDown 0x0077 +#define api_AgcHold 0x0078 +#define api_PwmCtrlHw 0x0079 +#define api_MaxAgcGain 0x007a +#define api_IniAgcGain 0x007b +#define api_mccid_bypass 0x007c +#define api_CdpfEnDefaultEchoRange 0x007d +#define api_CdpfIniTestNoSteady 0x007e +#define api_timing_err_level 0x007f +#define api_timing_retrain_cnt 0x0080 +#define api_ChannelDiffThrSteady 0x0081 + +#define api_adjacent_on 0x0082 +#define api_near_adjacent_on 0x0083 +#define api_adjacent_off 0x0084 +#define api_near_adjacent_off 0x0085 +#define api_max_rf_agc_7_0 0x0086 +#define api_max_rf_agc_9_8 0x0087 +#define api_rf_top_numerator_s_7_0 0x0088 +#define api_rf_top_numerator_s_9_8 0x0089 + +#define api_gui_tdi_lms_en 0x008a +#define api_fccid_strobe_scale 0x008b +#define api_fccid_strobe_numerator 0x008c +#define api_fccid_strobe_base 0x008d +#define api_use_fccid 0x008e +#define api_fft_ave_symbol_num 0x008f +#define api_large_tone_num_th_7_0 0x0090 +#define api_large_tone_num_th_15_8 0x0091 +#define api_use_3m_lpf_th 0x0092 +#define api_ce_var_min_8k 0x0093 +#define api_ce_var_min_4k 0x0094 +#define api_ce_var_min_2k 0x0095 +#define api_ce_var_min_8k_non_flat 0x0096 +#define api_flatness_thr 0x0097 +#define api_non_mobile_signal_level_offset 0x0098 +#define api_gui_ar_csi_en 0x0099 +#define api_h2_echo_detected 0x009a +#define api_gain_offset_O 0x009b +#define api_gain_slope_O 0x009c +#define api_pin_diode_gain_loss 0x009d +#define api_signal_strength_if_low 0x009e + +#define api_flatness_thr_high 0x009f +#define api_flatness_thr_low 0x00a0 + +#define api_sbq1 0x00a1 +#define api_sbq2 0x00a2 + +#define api_dyna_dca_offset_en 0x00a3 +#define api_dca_sbq_bad_th 0x00a4 +#define api_detect_timing_err_en 0x00a5 +#define api_flatness_from_h2_echo 0x00a6 + +#define api_timging_error_detection 0x00a7 +#define api_ce_forced_by_rotate 0x00a8 +#define api_fccid_fft_mask_en 0x00a9 +#define api_second_fctrl_unforce_en 0x00aa +#define api_force_fdi0_at_high_mobile_en 0x00ab +#define api_high_mobile_detected 0x00ac +#define api_flatness_detection_en 0x00ad +#define api_ChooseFsteCostFunctionFromCdpf 0x00ae +#define api_signal_level 0x00af +#define api_TryConf2En 0x00b0 +#define api_Lower_tpsd_lock 0x00b1 +#define api_Upper_tpsd_lock 0x00b2 + +#define api_AgcCtrlType 0x00b3 +#define api_opt_LNA_Rssi_scale 0x00b4 +#define api_StopByTcl 0x00b5 +#define api_RssiCalibration 0x00b6 +#define api_AciDesiredSignalLevel_h 0x00b7 +#define api_AciDesiredSignalLevel_l 0x00b8 +#define api_ECO_ASIC 0x00b9 +#define api_NXP_USE_I2C 0x00ba +#define api_rf_freqency_23_16 0x00bb +#define api_rf_freqency_15_8 0x00bc +#define api_rf_freqency_7_0 0x00bd +#define api_iqik_en 0x00be +#define api_dcc_en 0x00bf +#define api_CdpfIniTestNoMobile 0x00c0 +#define api_ACIdetection 0x00c1 +#define api_PinDiode 0x00c2 +#define api_LNA_Gain 0x00c3 +#define api_ChannelDiffThrMobile 0x00c4 +#define api_var_end 0x00c5 + +/* registers */ +#define p_reg_p_aagc_log_2_acc 0xF000 +#define reg_p_aagc_log_2_acc_pos 0 +#define reg_p_aagc_log_2_acc_len 4 +#define reg_p_aagc_log_2_acc_lsb 0 +#define p_reg_p_aagc_signal_level_rdy 0xF001 +#define reg_p_aagc_signal_level_rdy_pos 0 +#define reg_p_aagc_signal_level_rdy_len 1 +#define reg_p_aagc_signal_level_rdy_lsb 0 +#define r_reg_r_aagc_signal_level_7_0 0xF002 +#define reg_r_aagc_signal_level_7_0_pos 0 +#define reg_r_aagc_signal_level_7_0_len 8 +#define reg_r_aagc_signal_level_7_0_lsb 0 +#define r_reg_r_aagc_signal_level_9_8 0xF003 +#define reg_r_aagc_signal_level_9_8_pos 0 +#define reg_r_aagc_signal_level_9_8_len 2 +#define reg_r_aagc_signal_level_9_8_lsb 8 +#define p_reg_p_aagc_rf_if_swap 0xF004 +#define reg_p_aagc_rf_if_swap_pos 0 +#define reg_p_aagc_rf_if_swap_len 1 +#define reg_p_aagc_rf_if_swap_lsb 0 +#define p_reg_p_pwm_rf_if_from_hw 0xF006 +#define reg_p_pwm_rf_if_from_hw_pos 0 +#define reg_p_pwm_rf_if_from_hw_len 1 +#define reg_p_pwm_rf_if_from_hw_lsb 0 +#define p_reg_aagc_out_if_inv 0xF007 +#define reg_aagc_out_if_inv_pos 0 +#define reg_aagc_out_if_inv_len 1 +#define reg_aagc_out_if_inv_lsb 0 +#define p_reg_aagc_int_en 0xF008 +#define reg_aagc_int_en_pos 0 +#define reg_aagc_int_en_len 1 +#define reg_aagc_int_en_lsb 0 +#define p_reg_aagc_lock_change_flag 0xF009 +#define reg_aagc_lock_change_flag_pos 0 +#define reg_aagc_lock_change_flag_len 1 +#define reg_aagc_lock_change_flag_lsb 0 +#define p_reg_aagc_rf_loop_bw_scale_acquire 0xF00A +#define reg_aagc_rf_loop_bw_scale_acquire_pos 0 +#define reg_aagc_rf_loop_bw_scale_acquire_len 5 +#define reg_aagc_rf_loop_bw_scale_acquire_lsb 0 +#define p_reg_aagc_rf_loop_bw_scale_track 0xF00B +#define reg_aagc_rf_loop_bw_scale_track_pos 0 +#define reg_aagc_rf_loop_bw_scale_track_len 5 +#define reg_aagc_rf_loop_bw_scale_track_lsb 0 +#define p_reg_aagc_if_loop_bw_scale_acquire 0xF00C +#define reg_aagc_if_loop_bw_scale_acquire_pos 0 +#define reg_aagc_if_loop_bw_scale_acquire_len 5 +#define reg_aagc_if_loop_bw_scale_acquire_lsb 0 +#define p_reg_aagc_if_loop_bw_scale_track 0xF00D +#define reg_aagc_if_loop_bw_scale_track_pos 0 +#define reg_aagc_if_loop_bw_scale_track_len 5 +#define reg_aagc_if_loop_bw_scale_track_lsb 0 +#define p_reg_aagc_max_rf_agc_7_0 0xF00E +#define reg_aagc_max_rf_agc_7_0_pos 0 +#define reg_aagc_max_rf_agc_7_0_len 8 +#define reg_aagc_max_rf_agc_7_0_lsb 0 +#define p_reg_aagc_max_rf_agc_9_8 0xF00F +#define reg_aagc_max_rf_agc_9_8_pos 0 +#define reg_aagc_max_rf_agc_9_8_len 2 +#define reg_aagc_max_rf_agc_9_8_lsb 8 +#define p_reg_aagc_min_rf_agc_7_0 0xF010 +#define reg_aagc_min_rf_agc_7_0_pos 0 +#define reg_aagc_min_rf_agc_7_0_len 8 +#define reg_aagc_min_rf_agc_7_0_lsb 0 +#define p_reg_aagc_min_rf_agc_9_8 0xF011 +#define reg_aagc_min_rf_agc_9_8_pos 0 +#define reg_aagc_min_rf_agc_9_8_len 2 +#define reg_aagc_min_rf_agc_9_8_lsb 8 +#define p_reg_aagc_max_if_agc_7_0 0xF012 +#define reg_aagc_max_if_agc_7_0_pos 0 +#define reg_aagc_max_if_agc_7_0_len 8 +#define reg_aagc_max_if_agc_7_0_lsb 0 +#define p_reg_aagc_max_if_agc_9_8 0xF013 +#define reg_aagc_max_if_agc_9_8_pos 0 +#define reg_aagc_max_if_agc_9_8_len 2 +#define reg_aagc_max_if_agc_9_8_lsb 8 +#define p_reg_aagc_min_if_agc_7_0 0xF014 +#define reg_aagc_min_if_agc_7_0_pos 0 +#define reg_aagc_min_if_agc_7_0_len 8 +#define reg_aagc_min_if_agc_7_0_lsb 0 +#define p_reg_aagc_min_if_agc_9_8 0xF015 +#define reg_aagc_min_if_agc_9_8_pos 0 +#define reg_aagc_min_if_agc_9_8_len 2 +#define reg_aagc_min_if_agc_9_8_lsb 8 +#define p_reg_aagc_lock_sample_scale 0xF016 +#define reg_aagc_lock_sample_scale_pos 0 +#define reg_aagc_lock_sample_scale_len 5 +#define reg_aagc_lock_sample_scale_lsb 0 +#define p_reg_aagc_rf_agc_lock_scale_acquire 0xF017 +#define reg_aagc_rf_agc_lock_scale_acquire_pos 0 +#define reg_aagc_rf_agc_lock_scale_acquire_len 3 +#define reg_aagc_rf_agc_lock_scale_acquire_lsb 0 +#define p_reg_aagc_rf_agc_lock_scale_track 0xF018 +#define reg_aagc_rf_agc_lock_scale_track_pos 0 +#define reg_aagc_rf_agc_lock_scale_track_len 3 +#define reg_aagc_rf_agc_lock_scale_track_lsb 0 +#define p_reg_aagc_if_agc_lock_scale_acquire 0xF019 +#define reg_aagc_if_agc_lock_scale_acquire_pos 0 +#define reg_aagc_if_agc_lock_scale_acquire_len 3 +#define reg_aagc_if_agc_lock_scale_acquire_lsb 0 +#define p_reg_aagc_if_agc_lock_scale_track 0xF01A +#define reg_aagc_if_agc_lock_scale_track_pos 0 +#define reg_aagc_if_agc_lock_scale_track_len 3 +#define reg_aagc_if_agc_lock_scale_track_lsb 0 +#define p_reg_aagc_rf_top_numerator_s_7_0 0xF01B +#define reg_aagc_rf_top_numerator_s_7_0_pos 0 +#define reg_aagc_rf_top_numerator_s_7_0_len 8 +#define reg_aagc_rf_top_numerator_s_7_0_lsb 0 +#define p_reg_aagc_rf_top_numerator_s_9_8 0xF01C +#define reg_aagc_rf_top_numerator_s_9_8_pos 0 +#define reg_aagc_rf_top_numerator_s_9_8_len 2 +#define reg_aagc_rf_top_numerator_s_9_8_lsb 8 +#define p_reg_aagc_if_top_numerator_s_7_0 0xF01D +#define reg_aagc_if_top_numerator_s_7_0_pos 0 +#define reg_aagc_if_top_numerator_s_7_0_len 8 +#define reg_aagc_if_top_numerator_s_7_0_lsb 0 +#define p_reg_aagc_if_top_numerator_s_9_8 0xF01E +#define reg_aagc_if_top_numerator_s_9_8_pos 0 +#define reg_aagc_if_top_numerator_s_9_8_len 2 +#define reg_aagc_if_top_numerator_s_9_8_lsb 8 +#define p_reg_aagc_adc_out_desired_s_7_0 0xF01F +#define reg_aagc_adc_out_desired_s_7_0_pos 0 +#define reg_aagc_adc_out_desired_s_7_0_len 8 +#define reg_aagc_adc_out_desired_s_7_0_lsb 0 +#define p_reg_aagc_adc_out_desired_s_8 0xF020 +#define reg_aagc_adc_out_desired_s_8_pos 0 +#define reg_aagc_adc_out_desired_s_8_len 1 +#define reg_aagc_adc_out_desired_s_8_lsb 8 +#define p_reg_aagc_lock_count_th 0xF021 +#define reg_aagc_lock_count_th_pos 0 +#define reg_aagc_lock_count_th_len 4 +#define reg_aagc_lock_count_th_lsb 0 +#define p_reg_aagc_rf_agc_unlock_numerator 0xF022 +#define reg_aagc_rf_agc_unlock_numerator_pos 0 +#define reg_aagc_rf_agc_unlock_numerator_len 6 +#define reg_aagc_rf_agc_unlock_numerator_lsb 0 +#define p_reg_aagc_if_agc_unlock_numerator 0xF023 +#define reg_aagc_if_agc_unlock_numerator_pos 0 +#define reg_aagc_if_agc_unlock_numerator_len 6 +#define reg_aagc_if_agc_unlock_numerator_lsb 0 +#define p_reg_aagc_rf_top_numerator_m_7_0 0xF025 +#define reg_aagc_rf_top_numerator_m_7_0_pos 0 +#define reg_aagc_rf_top_numerator_m_7_0_len 8 +#define reg_aagc_rf_top_numerator_m_7_0_lsb 0 +#define p_reg_aagc_rf_top_numerator_m_9_8 0xF026 +#define reg_aagc_rf_top_numerator_m_9_8_pos 0 +#define reg_aagc_rf_top_numerator_m_9_8_len 2 +#define reg_aagc_rf_top_numerator_m_9_8_lsb 8 +#define p_reg_aagc_if_top_numerator_m_7_0 0xF027 +#define reg_aagc_if_top_numerator_m_7_0_pos 0 +#define reg_aagc_if_top_numerator_m_7_0_len 8 +#define reg_aagc_if_top_numerator_m_7_0_lsb 0 +#define p_reg_aagc_if_top_numerator_m_9_8 0xF028 +#define reg_aagc_if_top_numerator_m_9_8_pos 0 +#define reg_aagc_if_top_numerator_m_9_8_len 2 +#define reg_aagc_if_top_numerator_m_9_8_lsb 8 +#define p_reg_aagc_adc_out_desired_m_7_0 0xF029 +#define reg_aagc_adc_out_desired_m_7_0_pos 0 +#define reg_aagc_adc_out_desired_m_7_0_len 8 +#define reg_aagc_adc_out_desired_m_7_0_lsb 0 +#define p_reg_aagc_adc_out_desired_m_8 0xF02A +#define reg_aagc_adc_out_desired_m_8_pos 0 +#define reg_aagc_adc_out_desired_m_8_len 1 +#define reg_aagc_adc_out_desired_m_8_lsb 8 +#define p_reg_aagc_mobile_sel 0xF02B +#define reg_aagc_mobile_sel_pos 0 +#define reg_aagc_mobile_sel_len 1 +#define reg_aagc_mobile_sel_lsb 0 +#define p_reg_aagc_top_reload 0xF02C +#define reg_aagc_top_reload_pos 0 +#define reg_aagc_top_reload_len 1 +#define reg_aagc_top_reload_lsb 0 +#define p_reg_aagc_rf_delta_voltage_en 0xF02D +#define reg_aagc_rf_delta_voltage_en_pos 0 +#define reg_aagc_rf_delta_voltage_en_len 1 +#define reg_aagc_rf_delta_voltage_en_lsb 0 +#define p_reg_aagc_rf_voltage_inc 0xF02E +#define reg_aagc_rf_voltage_inc_pos 0 +#define reg_aagc_rf_voltage_inc_len 1 +#define reg_aagc_rf_voltage_inc_lsb 0 +#define p_reg_aagc_if_delta_voltage_en 0xF02F +#define reg_aagc_if_delta_voltage_en_pos 0 +#define reg_aagc_if_delta_voltage_en_len 1 +#define reg_aagc_if_delta_voltage_en_lsb 0 +#define p_reg_aagc_if_voltage_inc 0xF030 +#define reg_aagc_if_voltage_inc_pos 0 +#define reg_aagc_if_voltage_inc_len 1 +#define reg_aagc_if_voltage_inc_lsb 0 +#define p_reg_aagc_rf_delta_voltage_7_0 0xF032 +#define reg_aagc_rf_delta_voltage_7_0_pos 0 +#define reg_aagc_rf_delta_voltage_7_0_len 8 +#define reg_aagc_rf_delta_voltage_7_0_lsb 0 +#define p_reg_aagc_rf_delta_voltage_15_8 0xF033 +#define reg_aagc_rf_delta_voltage_15_8_pos 0 +#define reg_aagc_rf_delta_voltage_15_8_len 8 +#define reg_aagc_rf_delta_voltage_15_8_lsb 8 +#define p_reg_aagc_rf_delta_voltage_23_16 0xF034 +#define reg_aagc_rf_delta_voltage_23_16_pos 0 +#define reg_aagc_rf_delta_voltage_23_16_len 8 +#define reg_aagc_rf_delta_voltage_23_16_lsb 16 +#define p_reg_aagc_rf_delta_voltage_29_24 0xF035 +#define reg_aagc_rf_delta_voltage_29_24_pos 0 +#define reg_aagc_rf_delta_voltage_29_24_len 6 +#define reg_aagc_rf_delta_voltage_29_24_lsb 24 +#define p_reg_aagc_if_delta_voltage_7_0 0xF036 +#define reg_aagc_if_delta_voltage_7_0_pos 0 +#define reg_aagc_if_delta_voltage_7_0_len 8 +#define reg_aagc_if_delta_voltage_7_0_lsb 0 +#define p_reg_aagc_if_delta_voltage_15_8 0xF037 +#define reg_aagc_if_delta_voltage_15_8_pos 0 +#define reg_aagc_if_delta_voltage_15_8_len 8 +#define reg_aagc_if_delta_voltage_15_8_lsb 8 +#define p_reg_aagc_if_delta_voltage_23_16 0xF038 +#define reg_aagc_if_delta_voltage_23_16_pos 0 +#define reg_aagc_if_delta_voltage_23_16_len 8 +#define reg_aagc_if_delta_voltage_23_16_lsb 16 +#define p_reg_aagc_if_delta_voltage_29_24 0xF039 +#define reg_aagc_if_delta_voltage_29_24_pos 0 +#define reg_aagc_if_delta_voltage_29_24_len 6 +#define reg_aagc_if_delta_voltage_29_24_lsb 24 +#define p_reg_aagc_delta_voltage_hold_time 0xF03A +#define reg_aagc_delta_voltage_hold_time_pos 0 +#define reg_aagc_delta_voltage_hold_time_len 8 +#define reg_aagc_delta_voltage_hold_time_lsb 0 +#define p_reg_aagc_top_th_dis 0xF041 +#define reg_aagc_top_th_dis_pos 0 +#define reg_aagc_top_th_dis_len 1 +#define reg_aagc_top_th_dis_lsb 0 +#define p_reg_p_aagc_rf_floor_dca 0xF042 +#define reg_p_aagc_rf_floor_dca_pos 0 +#define reg_p_aagc_rf_floor_dca_len 8 +#define reg_p_aagc_rf_floor_dca_lsb 0 +#define p_reg_p_aagc_if_floor_dca 0xF043 +#define reg_p_aagc_if_floor_dca_pos 0 +#define reg_p_aagc_if_floor_dca_len 8 +#define reg_p_aagc_if_floor_dca_lsb 0 +#define p_reg_p_aagc_rf_gain_scale_dca 0xF044 +#define reg_p_aagc_rf_gain_scale_dca_pos 0 +#define reg_p_aagc_rf_gain_scale_dca_len 3 +#define reg_p_aagc_rf_gain_scale_dca_lsb 0 +#define p_reg_p_aagc_if_gain_scale_dca 0xF045 +#define reg_p_aagc_if_gain_scale_dca_pos 0 +#define reg_p_aagc_if_gain_scale_dca_len 3 +#define reg_p_aagc_if_gain_scale_dca_lsb 0 +#define r_reg_r_aagc_ufl_gain 0xF046 +#define reg_r_aagc_ufl_gain_pos 0 +#define reg_r_aagc_ufl_gain_len 8 +#define reg_r_aagc_ufl_gain_lsb 0 +#define p_reg_aagc_out_rf_inv 0xF047 +#define reg_aagc_out_rf_inv_pos 0 +#define reg_aagc_out_rf_inv_len 1 +#define reg_aagc_out_rf_inv_lsb 0 +#define p_reg_p_aagc_save_agc_control 0xF048 +#define reg_p_aagc_save_agc_control_pos 0 +#define reg_p_aagc_save_agc_control_len 1 +#define reg_p_aagc_save_agc_control_lsb 0 +#define p_reg_aagc_fw_sel 0xF049 +#define reg_aagc_fw_sel_pos 0 +#define reg_aagc_fw_sel_len 1 +#define reg_aagc_fw_sel_lsb 0 +#define r_reg_r_aagc_rf_control_7_0 0xF04A +#define reg_r_aagc_rf_control_7_0_pos 0 +#define reg_r_aagc_rf_control_7_0_len 8 +#define reg_r_aagc_rf_control_7_0_lsb 0 +#define r_reg_r_aagc_rf_control_9_8 0xF04B +#define reg_r_aagc_rf_control_9_8_pos 0 +#define reg_r_aagc_rf_control_9_8_len 2 +#define reg_r_aagc_rf_control_9_8_lsb 8 +#define r_reg_r_aagc_if_control_7_0 0xF04C +#define reg_r_aagc_if_control_7_0_pos 0 +#define reg_r_aagc_if_control_7_0_len 8 +#define reg_r_aagc_if_control_7_0_lsb 0 +#define r_reg_r_aagc_if_control_9_8 0xF04D +#define reg_r_aagc_if_control_9_8_pos 0 +#define reg_r_aagc_if_control_9_8_len 2 +#define reg_r_aagc_if_control_9_8_lsb 8 +#define p_reg_aagc_adc_out_desired_from_fw_7_0 0xF04E +#define reg_aagc_adc_out_desired_from_fw_7_0_pos 0 +#define reg_aagc_adc_out_desired_from_fw_7_0_len 8 +#define reg_aagc_adc_out_desired_from_fw_7_0_lsb 0 +#define p_reg_aagc_adc_out_desired_from_fw_8 0xF04F +#define reg_aagc_adc_out_desired_from_fw_8_pos 0 +#define reg_aagc_adc_out_desired_from_fw_8_len 1 +#define reg_aagc_adc_out_desired_from_fw_8_lsb 8 +#define p_reg_aagc_init_rf_agc_7_0 0xF050 +#define reg_aagc_init_rf_agc_7_0_pos 0 +#define reg_aagc_init_rf_agc_7_0_len 8 +#define reg_aagc_init_rf_agc_7_0_lsb 0 +#define p_reg_aagc_init_rf_agc_9_8 0xF051 +#define reg_aagc_init_rf_agc_9_8_pos 0 +#define reg_aagc_init_rf_agc_9_8_len 2 +#define reg_aagc_init_rf_agc_9_8_lsb 8 +#define p_reg_aagc_init_if_agc_7_0 0xF052 +#define reg_aagc_init_if_agc_7_0_pos 0 +#define reg_aagc_init_if_agc_7_0_len 8 +#define reg_aagc_init_if_agc_7_0_lsb 0 +#define p_reg_aagc_init_if_agc_9_8 0xF053 +#define reg_aagc_init_if_agc_9_8_pos 0 +#define reg_aagc_init_if_agc_9_8_len 2 +#define reg_aagc_init_if_agc_9_8_lsb 8 +#define p_reg_p_pwm_if_high_unit_num 0xF054 +#define reg_p_pwm_if_high_unit_num_pos 0 +#define reg_p_pwm_if_high_unit_num_len 8 +#define reg_p_pwm_if_high_unit_num_lsb 0 +#define p_reg_p_pwm_rf_high_unit_num 0xF055 +#define reg_p_pwm_rf_high_unit_num_pos 0 +#define reg_p_pwm_rf_high_unit_num_len 8 +#define reg_p_pwm_rf_high_unit_num_lsb 0 +#define p_reg_p_pwm_rf_gpio 0xF058 +#define reg_p_pwm_rf_gpio_pos 0 +#define reg_p_pwm_rf_gpio_len 1 +#define reg_p_pwm_rf_gpio_lsb 0 +#define p_reg_p_pwm_if_gpio 0xF058 +#define reg_p_pwm_if_gpio_pos 1 +#define reg_p_pwm_if_gpio_len 1 +#define reg_p_pwm_if_gpio_lsb 0 +#define p_reg_aagc_in_sat_cnt_7_0 0xF05A +#define reg_aagc_in_sat_cnt_7_0_pos 0 +#define reg_aagc_in_sat_cnt_7_0_len 8 +#define reg_aagc_in_sat_cnt_7_0_lsb 0 +#define p_reg_aagc_in_sat_cnt_15_8 0xF05B +#define reg_aagc_in_sat_cnt_15_8_pos 0 +#define reg_aagc_in_sat_cnt_15_8_len 8 +#define reg_aagc_in_sat_cnt_15_8_lsb 8 +#define p_reg_aagc_in_sat_cnt_23_16 0xF05C +#define reg_aagc_in_sat_cnt_23_16_pos 0 +#define reg_aagc_in_sat_cnt_23_16_len 8 +#define reg_aagc_in_sat_cnt_23_16_lsb 16 +#define p_reg_aagc_in_sat_cnt_31_24 0xF05D +#define reg_aagc_in_sat_cnt_31_24_pos 0 +#define reg_aagc_in_sat_cnt_31_24_len 8 +#define reg_aagc_in_sat_cnt_31_24_lsb 24 +#define p_reg_p_pwm_cycle_unit 0xF05E +#define reg_p_pwm_cycle_unit_pos 0 +#define reg_p_pwm_cycle_unit_len 4 +#define reg_p_pwm_cycle_unit_lsb 0 +#define p_reg_p_pwm_en 0xF05F +#define reg_p_pwm_en_pos 0 +#define reg_p_pwm_en_len 1 +#define reg_p_pwm_en_lsb 0 +#define r_reg_aagc_rf_gain 0xF060 +#define reg_aagc_rf_gain_pos 0 +#define reg_aagc_rf_gain_len 8 +#define reg_aagc_rf_gain_lsb 0 +#define r_reg_aagc_if_gain 0xF061 +#define reg_aagc_if_gain_pos 0 +#define reg_aagc_if_gain_len 8 +#define reg_aagc_if_gain_lsb 0 +#define r_reg_aagc_current_desired_level_7_0 0xF062 +#define reg_aagc_current_desired_level_7_0_pos 0 +#define reg_aagc_current_desired_level_7_0_len 8 +#define reg_aagc_current_desired_level_7_0_lsb 0 +#define r_reg_aagc_current_desired_level_8 0xF063 +#define reg_aagc_current_desired_level_8_pos 0 +#define reg_aagc_current_desired_level_8_len 1 +#define reg_aagc_current_desired_level_8_lsb 8 +#define p_reg_tinr_fifo_size 0xF064 +#define reg_tinr_fifo_size_pos 0 +#define reg_tinr_fifo_size_len 5 +#define reg_tinr_fifo_size_lsb 0 +#define p_reg_tinr_saturation_th_7_0 0xF065 +#define reg_tinr_saturation_th_7_0_pos 0 +#define reg_tinr_saturation_th_7_0_len 8 +#define reg_tinr_saturation_th_7_0_lsb 0 +#define p_reg_tinr_saturation_th_9_8 0xF066 +#define reg_tinr_saturation_th_9_8_pos 0 +#define reg_tinr_saturation_th_9_8_len 2 +#define reg_tinr_saturation_th_9_8_lsb 8 +#define p_reg_tinr_saturation_cnt_th 0xF067 +#define reg_tinr_saturation_cnt_th_pos 0 +#define reg_tinr_saturation_cnt_th_len 4 +#define reg_tinr_saturation_cnt_th_lsb 0 +#define r_reg_tinr_counter_7_0 0xF068 +#define reg_tinr_counter_7_0_pos 0 +#define reg_tinr_counter_7_0_len 8 +#define reg_tinr_counter_7_0_lsb 0 +#define r_reg_tinr_counter_15_8 0xF069 +#define reg_tinr_counter_15_8_pos 0 +#define reg_tinr_counter_15_8_len 8 +#define reg_tinr_counter_15_8_lsb 8 +#define p_reg_tinr_counter_rst 0xF06C +#define reg_tinr_counter_rst_pos 0 +#define reg_tinr_counter_rst_len 1 +#define reg_tinr_counter_rst_lsb 0 +#define p_reg_tinr_ins_th_7_0 0xF06F +#define reg_tinr_ins_th_7_0_pos 0 +#define reg_tinr_ins_th_7_0_len 8 +#define reg_tinr_ins_th_7_0_lsb 0 +#define p_reg_tinr_ins_th_9_8 0xF070 +#define reg_tinr_ins_th_9_8_pos 0 +#define reg_tinr_ins_th_9_8_len 2 +#define reg_tinr_ins_th_9_8_lsb 8 +#define p_reg_tinr_ins_en 0xF071 +#define reg_tinr_ins_en_pos 0 +#define reg_tinr_ins_en_len 1 +#define reg_tinr_ins_en_lsb 0 +#define p_reg_tinr_ins_size 0xF072 +#define reg_tinr_ins_size_pos 0 +#define reg_tinr_ins_size_len 4 +#define reg_tinr_ins_size_lsb 0 +#define p_reg_tinr_ins_hnum 0xF073 +#define reg_tinr_ins_hnum_pos 0 +#define reg_tinr_ins_hnum_len 4 +#define reg_tinr_ins_hnum_lsb 0 +#define r_reg_tinr_ins_hcnt_7_0 0xF074 +#define reg_tinr_ins_hcnt_7_0_pos 0 +#define reg_tinr_ins_hcnt_7_0_len 8 +#define reg_tinr_ins_hcnt_7_0_lsb 0 +#define r_reg_tinr_ins_hcnt_15_8 0xF075 +#define reg_tinr_ins_hcnt_15_8_pos 0 +#define reg_tinr_ins_hcnt_15_8_len 8 +#define reg_tinr_ins_hcnt_15_8_lsb 8 +#define p_reg_tinr_in_conj 0xF076 +#define reg_tinr_in_conj_pos 0 +#define reg_tinr_in_conj_len 1 +#define reg_tinr_in_conj_lsb 0 +#define p_reg_tinr_in_zero_if 0xF077 +#define reg_tinr_in_zero_if_pos 0 +#define reg_tinr_in_zero_if_len 2 +#define reg_tinr_in_zero_if_lsb 0 +#define p_reg_tinr_in_shift 0xF078 +#define reg_tinr_in_shift_pos 0 +#define reg_tinr_in_shift_len 1 +#define reg_tinr_in_shift_lsb 0 +#define p_reg_tinr_in_conj_sat_counter_rst 0xF079 +#define reg_tinr_in_conj_sat_counter_rst_pos 0 +#define reg_tinr_in_conj_sat_counter_rst_len 1 +#define reg_tinr_in_conj_sat_counter_rst_lsb 0 +#define r_reg_tinr_in_conj_sat_counter_7_0 0xF07A +#define reg_tinr_in_conj_sat_counter_7_0_pos 0 +#define reg_tinr_in_conj_sat_counter_7_0_len 8 +#define reg_tinr_in_conj_sat_counter_7_0_lsb 0 +#define r_reg_tinr_in_conj_sat_counter_14_8 0xF07B +#define reg_tinr_in_conj_sat_counter_14_8_pos 0 +#define reg_tinr_in_conj_sat_counter_14_8_len 7 +#define reg_tinr_in_conj_sat_counter_14_8_lsb 8 +#define p_reg_p_antif_en 0xF07C +#define reg_p_antif_en_pos 0 +#define reg_p_antif_en_len 1 +#define reg_p_antif_en_lsb 0 +#define p_reg_p_antif_rst 0xF07D +#define reg_p_antif_rst_pos 0 +#define reg_p_antif_rst_len 1 +#define reg_p_antif_rst_lsb 0 +#define p_reg_p_antif_byp 0xF07E +#define reg_p_antif_byp_pos 0 +#define reg_p_antif_byp_len 1 +#define reg_p_antif_byp_lsb 0 +#define p_reg_p_antif_mode 0xF07F +#define reg_p_antif_mode_pos 0 +#define reg_p_antif_mode_len 1 +#define reg_p_antif_mode_lsb 0 +#define p_reg_p_ds_byp 0xF080 +#define reg_p_ds_byp_pos 0 +#define reg_p_ds_byp_len 1 +#define reg_p_ds_byp_lsb 0 +#define p_reg_p_antif_dagc5_mode 0xF081 +#define reg_p_antif_dagc5_mode_pos 0 +#define reg_p_antif_dagc5_mode_len 2 +#define reg_p_antif_dagc5_mode_lsb 0 +#define p_reg_p_antif_dagc5_desired_level_7_0 0xF082 +#define reg_p_antif_dagc5_desired_level_7_0_pos 0 +#define reg_p_antif_dagc5_desired_level_7_0_len 8 +#define reg_p_antif_dagc5_desired_level_7_0_lsb 0 +#define p_reg_p_antif_dagc5_desired_level_8 0xF083 +#define reg_p_antif_dagc5_desired_level_8_pos 0 +#define reg_p_antif_dagc5_desired_level_8_len 1 +#define reg_p_antif_dagc5_desired_level_8_lsb 8 +#define p_reg_p_antif_dagc5_apply_delay 0xF084 +#define reg_p_antif_dagc5_apply_delay_pos 0 +#define reg_p_antif_dagc5_apply_delay_len 7 +#define reg_p_antif_dagc5_apply_delay_lsb 0 +#define p_reg_p_antif_dagc5_fixed_gain_7_0 0xF085 +#define reg_p_antif_dagc5_fixed_gain_7_0_pos 0 +#define reg_p_antif_dagc5_fixed_gain_7_0_len 8 +#define reg_p_antif_dagc5_fixed_gain_7_0_lsb 0 +#define p_reg_p_antif_dagc5_fixed_gain_11_8 0xF086 +#define reg_p_antif_dagc5_fixed_gain_11_8_pos 0 +#define reg_p_antif_dagc5_fixed_gain_11_8_len 4 +#define reg_p_antif_dagc5_fixed_gain_11_8_lsb 8 +#define p_reg_p_antif_dagc5_use_despow 0xF087 +#define reg_p_antif_dagc5_use_despow_pos 0 +#define reg_p_antif_dagc5_use_despow_len 1 +#define reg_p_antif_dagc5_use_despow_lsb 0 +#define p_reg_p_antif_dagc5_log_2_accumulate_num 0xF088 +#define reg_p_antif_dagc5_log_2_accumulate_num_pos 0 +#define reg_p_antif_dagc5_log_2_accumulate_num_len 5 +#define reg_p_antif_dagc5_log_2_accumulate_num_lsb 0 +#define p_reg_p_antif_dagc5_in_sat_cnt_7_0 0xF089 +#define reg_p_antif_dagc5_in_sat_cnt_7_0_pos 0 +#define reg_p_antif_dagc5_in_sat_cnt_7_0_len 8 +#define reg_p_antif_dagc5_in_sat_cnt_7_0_lsb 0 +#define p_reg_p_antif_dagc5_in_sat_cnt_15_8 0xF08A +#define reg_p_antif_dagc5_in_sat_cnt_15_8_pos 0 +#define reg_p_antif_dagc5_in_sat_cnt_15_8_len 8 +#define reg_p_antif_dagc5_in_sat_cnt_15_8_lsb 8 +#define p_reg_p_antif_dagc5_in_sat_cnt_23_16 0xF08B +#define reg_p_antif_dagc5_in_sat_cnt_23_16_pos 0 +#define reg_p_antif_dagc5_in_sat_cnt_23_16_len 8 +#define reg_p_antif_dagc5_in_sat_cnt_23_16_lsb 16 +#define p_reg_p_antif_dagc5_in_sat_cnt_31_24 0xF08C +#define reg_p_antif_dagc5_in_sat_cnt_31_24_pos 0 +#define reg_p_antif_dagc5_in_sat_cnt_31_24_len 8 +#define reg_p_antif_dagc5_in_sat_cnt_31_24_lsb 24 +#define p_reg_p_antif_dagc5_out_sat_cnt_7_0 0xF08D +#define reg_p_antif_dagc5_out_sat_cnt_7_0_pos 0 +#define reg_p_antif_dagc5_out_sat_cnt_7_0_len 8 +#define reg_p_antif_dagc5_out_sat_cnt_7_0_lsb 0 +#define p_reg_p_antif_dagc5_out_sat_cnt_15_8 0xF08E +#define reg_p_antif_dagc5_out_sat_cnt_15_8_pos 0 +#define reg_p_antif_dagc5_out_sat_cnt_15_8_len 8 +#define reg_p_antif_dagc5_out_sat_cnt_15_8_lsb 8 +#define p_reg_p_antif_dagc5_out_sat_cnt_23_16 0xF08F +#define reg_p_antif_dagc5_out_sat_cnt_23_16_pos 0 +#define reg_p_antif_dagc5_out_sat_cnt_23_16_len 8 +#define reg_p_antif_dagc5_out_sat_cnt_23_16_lsb 16 +#define p_reg_p_antif_dagc5_out_sat_cnt_31_24 0xF090 +#define reg_p_antif_dagc5_out_sat_cnt_31_24_pos 0 +#define reg_p_antif_dagc5_out_sat_cnt_31_24_len 8 +#define reg_p_antif_dagc5_out_sat_cnt_31_24_lsb 24 +#define p_reg_p_antif_dagc5_rst 0xF091 +#define reg_p_antif_dagc5_rst_pos 0 +#define reg_p_antif_dagc5_rst_len 1 +#define reg_p_antif_dagc5_rst_lsb 0 +#define p_reg_p_antif_dagc5_en 0xF092 +#define reg_p_antif_dagc5_en_pos 0 +#define reg_p_antif_dagc5_en_len 1 +#define reg_p_antif_dagc5_en_lsb 0 +#define p_reg_p_antif_sc_mode 0xF093 +#define reg_p_antif_sc_mode_pos 0 +#define reg_p_antif_sc_mode_len 4 +#define reg_p_antif_sc_mode_lsb 0 +#define p_reg_p_antif_dagc5_done 0xF094 +#define reg_p_antif_dagc5_done_pos 0 +#define reg_p_antif_dagc5_done_len 1 +#define reg_p_antif_dagc5_done_lsb 0 +#define r_reg_r_antif_sc_7_0 0xF095 +#define reg_r_antif_sc_7_0_pos 0 +#define reg_r_antif_sc_7_0_len 8 +#define reg_r_antif_sc_7_0_lsb 0 +#define r_reg_r_antif_sc_15_8 0xF096 +#define reg_r_antif_sc_15_8_pos 0 +#define reg_r_antif_sc_15_8_len 8 +#define reg_r_antif_sc_15_8_lsb 8 +#define r_reg_r_antif_dagc5_multiplier_7_0 0xF097 +#define reg_r_antif_dagc5_multiplier_7_0_pos 0 +#define reg_r_antif_dagc5_multiplier_7_0_len 8 +#define reg_r_antif_dagc5_multiplier_7_0_lsb 0 +#define r_reg_r_antif_dagc5_multiplier_15_8 0xF098 +#define reg_r_antif_dagc5_multiplier_15_8_pos 0 +#define reg_r_antif_dagc5_multiplier_15_8_len 8 +#define reg_r_antif_dagc5_multiplier_15_8_lsb 8 +#define r_reg_r_antif_dagc5_right_shift_bits 0xF099 +#define reg_r_antif_dagc5_right_shift_bits_pos 0 +#define reg_r_antif_dagc5_right_shift_bits_len 4 +#define reg_r_antif_dagc5_right_shift_bits_lsb 0 +#define p_reg_p_antif_dagc5_bypass_scale_ctl 0xF09A +#define reg_p_antif_dagc5_bypass_scale_ctl_pos 0 +#define reg_p_antif_dagc5_bypass_scale_ctl_len 3 +#define reg_p_antif_dagc5_bypass_scale_ctl_lsb 0 +#define p_reg_mccid_ccirunno_7_0 0xF09B +#define reg_mccid_ccirunno_7_0_pos 0 +#define reg_mccid_ccirunno_7_0_len 8 +#define reg_mccid_ccirunno_7_0_lsb 0 +#define p_reg_mccid_ccirunno_8 0xF09C +#define reg_mccid_ccirunno_8_pos 0 +#define reg_mccid_ccirunno_8_len 1 +#define reg_mccid_ccirunno_8_lsb 8 +#define p_reg_mccid_acirunno_7_0 0xF09D +#define reg_mccid_acirunno_7_0_pos 0 +#define reg_mccid_acirunno_7_0_len 8 +#define reg_mccid_acirunno_7_0_lsb 0 +#define p_reg_mccid_acirunno_8 0xF09E +#define reg_mccid_acirunno_8_pos 0 +#define reg_mccid_acirunno_8_len 1 +#define reg_mccid_acirunno_8_lsb 8 +#define p_reg_mccid_maxtonenearrange_7_0 0xF09F +#define reg_mccid_maxtonenearrange_7_0_pos 0 +#define reg_mccid_maxtonenearrange_7_0_len 8 +#define reg_mccid_maxtonenearrange_7_0_lsb 0 +#define p_reg_mccid_maxtonenearrange_8 0xF0A0 +#define reg_mccid_maxtonenearrange_8_pos 0 +#define reg_mccid_maxtonenearrange_8_len 1 +#define reg_mccid_maxtonenearrange_8_lsb 8 +#define r_reg_mccid_maxacipower_7_0 0xF0A1 +#define reg_mccid_maxacipower_7_0_pos 0 +#define reg_mccid_maxacipower_7_0_len 8 +#define reg_mccid_maxacipower_7_0_lsb 0 +#define r_reg_mccid_maxacipower_15_8 0xF0A2 +#define reg_mccid_maxacipower_15_8_pos 0 +#define reg_mccid_maxacipower_15_8_len 8 +#define reg_mccid_maxacipower_15_8_lsb 8 +#define r_reg_mccid_maxacipower_19_16 0xF0A3 +#define reg_mccid_maxacipower_19_16_pos 0 +#define reg_mccid_maxacipower_19_16_len 4 +#define reg_mccid_maxacipower_19_16_lsb 16 +#define p_reg_p_dcoe_en 0xF0D5 +#define reg_p_dcoe_en_pos 0 +#define reg_p_dcoe_en_len 1 +#define reg_p_dcoe_en_lsb 0 +#define p_reg_p_dcoe_rst 0xF0D6 +#define reg_p_dcoe_rst_pos 0 +#define reg_p_dcoe_rst_len 1 +#define reg_p_dcoe_rst_lsb 0 +#define p_reg_p_dcoe_clear 0xF0D7 +#define reg_p_dcoe_clear_pos 0 +#define reg_p_dcoe_clear_len 1 +#define reg_p_dcoe_clear_lsb 0 +#define p_reg_p_dcoe_applyloc_7_0 0xF0D8 +#define reg_p_dcoe_applyloc_7_0_pos 0 +#define reg_p_dcoe_applyloc_7_0_len 8 +#define reg_p_dcoe_applyloc_7_0_lsb 0 +#define p_reg_p_dcoe_applyloc_12_8 0xF0D9 +#define reg_p_dcoe_applyloc_12_8_pos 0 +#define reg_p_dcoe_applyloc_12_8_len 5 +#define reg_p_dcoe_applyloc_12_8_lsb 8 +#define p_reg_p_dcoe_accnums 0xF0DA +#define reg_p_dcoe_accnums_pos 0 +#define reg_p_dcoe_accnums_len 3 +#define reg_p_dcoe_accnums_lsb 0 +#define p_reg_p_dcoe_accweightsum_sh 0xF0DB +#define reg_p_dcoe_accweightsum_sh_pos 0 +#define reg_p_dcoe_accweightsum_sh_len 3 +#define reg_p_dcoe_accweightsum_sh_lsb 0 +#define p_reg_p_dcoe_accweightcurr 0xF0DC +#define reg_p_dcoe_accweightcurr_pos 0 +#define reg_p_dcoe_accweightcurr_len 8 +#define reg_p_dcoe_accweightcurr_lsb 0 +#define p_reg_dcoe_apply_rd 0xF0DF +#define reg_dcoe_apply_rd_pos 0 +#define reg_dcoe_apply_rd_len 1 +#define reg_dcoe_apply_rd_lsb 0 +#define r_reg_dcoe_apply_i 0xF0E0 +#define reg_dcoe_apply_i_pos 0 +#define reg_dcoe_apply_i_len 8 +#define reg_dcoe_apply_i_lsb 0 +#define r_reg_dcoe_apply_q 0xF0E1 +#define reg_dcoe_apply_q_pos 0 +#define reg_dcoe_apply_q_len 8 +#define reg_dcoe_apply_q_lsb 0 +#define p_reg_p_dcrm_en 0xF0E2 +#define reg_p_dcrm_en_pos 0 +#define reg_p_dcrm_en_len 1 +#define reg_p_dcrm_en_lsb 0 +#define p_reg_p_dcrm_fir 0xF0E3 +#define reg_p_dcrm_fir_pos 0 +#define reg_p_dcrm_fir_len 1 +#define reg_p_dcrm_fir_lsb 0 +#define p_reg_p_dcrm_log2_firlen 0xF0E4 +#define reg_p_dcrm_log2_firlen_pos 0 +#define reg_p_dcrm_log2_firlen_len 3 +#define reg_p_dcrm_log2_firlen_lsb 0 +#define r_reg_dcoe_apply_fir_i 0xF0E5 +#define reg_dcoe_apply_fir_i_pos 0 +#define reg_dcoe_apply_fir_i_len 8 +#define reg_dcoe_apply_fir_i_lsb 0 +#define r_reg_dcoe_apply_fir_q 0xF0E6 +#define reg_dcoe_apply_fir_q_pos 0 +#define reg_dcoe_apply_fir_q_len 8 +#define reg_dcoe_apply_fir_q_lsb 0 +#define p_reg_p_dcrm_force_en 0xF0E7 +#define reg_p_dcrm_force_en_pos 0 +#define reg_p_dcrm_force_en_len 1 +#define reg_p_dcrm_force_en_lsb 0 +#define p_reg_p_dcrm_force_value_i 0xF0E8 +#define reg_p_dcrm_force_value_i_pos 0 +#define reg_p_dcrm_force_value_i_len 8 +#define reg_p_dcrm_force_value_i_lsb 0 +#define p_reg_p_dcrm_force_value_q 0xF0E9 +#define reg_p_dcrm_force_value_q_pos 0 +#define reg_p_dcrm_force_value_q_len 8 +#define reg_p_dcrm_force_value_q_lsb 0 +#define p_reg_p_iqip_en 0xF0EA +#define reg_p_iqip_en_pos 0 +#define reg_p_iqip_en_len 1 +#define reg_p_iqip_en_lsb 0 +#define p_reg_p_iqip_rst 0xF0EB +#define reg_p_iqip_rst_pos 0 +#define reg_p_iqip_rst_len 1 +#define reg_p_iqip_rst_lsb 0 +#define p_reg_iqip_mu_ld 0xF0EC +#define reg_iqip_mu_ld_pos 0 +#define reg_iqip_mu_ld_len 1 +#define reg_iqip_mu_ld_lsb 0 +#define p_reg_p_iqip_mu_7_0 0xF0ED +#define reg_p_iqip_mu_7_0_pos 0 +#define reg_p_iqip_mu_7_0_len 8 +#define reg_p_iqip_mu_7_0_lsb 0 +#define p_reg_p_iqip_mu_11_8 0xF0EE +#define reg_p_iqip_mu_11_8_pos 0 +#define reg_p_iqip_mu_11_8_len 4 +#define reg_p_iqip_mu_11_8_lsb 8 +#define p_reg_iqip_gs_ld 0xF0EF +#define reg_iqip_gs_ld_pos 0 +#define reg_iqip_gs_ld_len 1 +#define reg_iqip_gs_ld_lsb 0 +#define p_reg_p_iqip_gsnums 0xF0F0 +#define reg_p_iqip_gsnums_pos 0 +#define reg_p_iqip_gsnums_len 4 +#define reg_p_iqip_gsnums_lsb 0 +#define p_reg_p_iqip_gsites_7_0 0xF0F1 +#define reg_p_iqip_gsites_7_0_pos 0 +#define reg_p_iqip_gsites_7_0_len 8 +#define reg_p_iqip_gsites_7_0_lsb 0 +#define p_reg_p_iqip_gsites_15_8 0xF0F2 +#define reg_p_iqip_gsites_15_8_pos 0 +#define reg_p_iqip_gsites_15_8_len 8 +#define reg_p_iqip_gsites_15_8_lsb 8 +#define p_reg_iqip_w_ld 0xF0F3 +#define reg_iqip_w_ld_pos 0 +#define reg_iqip_w_ld_len 1 +#define reg_iqip_w_ld_lsb 0 +#define p_reg_p_iqip_w_re_7_0 0xF0F4 +#define reg_p_iqip_w_re_7_0_pos 0 +#define reg_p_iqip_w_re_7_0_len 8 +#define reg_p_iqip_w_re_7_0_lsb 0 +#define p_reg_p_iqip_w_re_15_8 0xF0F5 +#define reg_p_iqip_w_re_15_8_pos 0 +#define reg_p_iqip_w_re_15_8_len 8 +#define reg_p_iqip_w_re_15_8_lsb 8 +#define p_reg_p_iqip_w_re_16 0xF0F6 +#define reg_p_iqip_w_re_16_pos 0 +#define reg_p_iqip_w_re_16_len 1 +#define reg_p_iqip_w_re_16_lsb 16 +#define p_reg_p_iqip_w_im_7_0 0xF0F7 +#define reg_p_iqip_w_im_7_0_pos 0 +#define reg_p_iqip_w_im_7_0_len 8 +#define reg_p_iqip_w_im_7_0_lsb 0 +#define p_reg_p_iqip_w_im_15_8 0xF0F8 +#define reg_p_iqip_w_im_15_8_pos 0 +#define reg_p_iqip_w_im_15_8_len 8 +#define reg_p_iqip_w_im_15_8_lsb 8 +#define p_reg_p_iqip_w_im_16 0xF0F9 +#define reg_p_iqip_w_im_16_pos 0 +#define reg_p_iqip_w_im_16_len 1 +#define reg_p_iqip_w_im_16_lsb 16 +#define p_reg_iqip_accnums_rd 0xF0FA +#define reg_iqip_accnums_rd_pos 0 +#define reg_iqip_accnums_rd_len 1 +#define reg_iqip_accnums_rd_lsb 0 +#define p_reg_p_iqip_accnums 0xF0FB +#define reg_p_iqip_accnums_pos 0 +#define reg_p_iqip_accnums_len 2 +#define reg_p_iqip_accnums_lsb 0 +#define p_reg_iqip_accnums_rdy 0xF0FC +#define reg_iqip_accnums_rdy_pos 0 +#define reg_iqip_accnums_rdy_len 1 +#define reg_iqip_accnums_rdy_lsb 0 +#define r_reg_r_iqip_wacc_re_7_0 0xF0FD +#define reg_r_iqip_wacc_re_7_0_pos 0 +#define reg_r_iqip_wacc_re_7_0_len 8 +#define reg_r_iqip_wacc_re_7_0_lsb 0 +#define r_reg_r_iqip_wacc_re_15_8 0xF0FE +#define reg_r_iqip_wacc_re_15_8_pos 0 +#define reg_r_iqip_wacc_re_15_8_len 8 +#define reg_r_iqip_wacc_re_15_8_lsb 8 +#define r_reg_r_iqip_wacc_re_16 0xF0FF +#define reg_r_iqip_wacc_re_16_pos 0 +#define reg_r_iqip_wacc_re_16_len 1 +#define reg_r_iqip_wacc_re_16_lsb 16 +#define r_reg_r_iqip_wacc_im_7_0 0xF100 +#define reg_r_iqip_wacc_im_7_0_pos 0 +#define reg_r_iqip_wacc_im_7_0_len 8 +#define reg_r_iqip_wacc_im_7_0_lsb 0 +#define r_reg_r_iqip_wacc_im_15_8 0xF101 +#define reg_r_iqip_wacc_im_15_8_pos 0 +#define reg_r_iqip_wacc_im_15_8_len 8 +#define reg_r_iqip_wacc_im_15_8_lsb 8 +#define r_reg_r_iqip_wacc_im_16 0xF102 +#define reg_r_iqip_wacc_im_16_pos 0 +#define reg_r_iqip_wacc_im_16_len 1 +#define reg_r_iqip_wacc_im_16_lsb 16 +#define r_reg_r_iqip_out2cacc_re_7_0 0xF103 +#define reg_r_iqip_out2cacc_re_7_0_pos 0 +#define reg_r_iqip_out2cacc_re_7_0_len 8 +#define reg_r_iqip_out2cacc_re_7_0_lsb 0 +#define r_reg_r_iqip_out2cacc_re_15_8 0xF104 +#define reg_r_iqip_out2cacc_re_15_8_pos 0 +#define reg_r_iqip_out2cacc_re_15_8_len 8 +#define reg_r_iqip_out2cacc_re_15_8_lsb 8 +#define r_reg_r_iqip_out2cacc_re_21_16 0xF105 +#define reg_r_iqip_out2cacc_re_21_16_pos 0 +#define reg_r_iqip_out2cacc_re_21_16_len 6 +#define reg_r_iqip_out2cacc_re_21_16_lsb 16 +#define r_reg_r_iqip_out2cacc_im_7_0 0xF106 +#define reg_r_iqip_out2cacc_im_7_0_pos 0 +#define reg_r_iqip_out2cacc_im_7_0_len 8 +#define reg_r_iqip_out2cacc_im_7_0_lsb 0 +#define r_reg_r_iqip_out2cacc_im_15_8 0xF107 +#define reg_r_iqip_out2cacc_im_15_8_pos 0 +#define reg_r_iqip_out2cacc_im_15_8_len 8 +#define reg_r_iqip_out2cacc_im_15_8_lsb 8 +#define r_reg_r_iqip_out2cacc_im_21_16 0xF108 +#define reg_r_iqip_out2cacc_im_21_16_pos 0 +#define reg_r_iqip_out2cacc_im_21_16_len 6 +#define reg_r_iqip_out2cacc_im_21_16_lsb 16 +#define p_reg_mccid_ccif0_scstrobe 0xF109 +#define reg_mccid_ccif0_scstrobe_pos 0 +#define reg_mccid_ccif0_scstrobe_len 7 +#define reg_mccid_ccif0_scstrobe_lsb 0 +#define p_reg_mccid_cciftrigger 0xF10A +#define reg_mccid_cciftrigger_pos 0 +#define reg_mccid_cciftrigger_len 1 +#define reg_mccid_cciftrigger_lsb 0 +#define p_reg_mccid_ccif1_scstrobe 0xF10B +#define reg_mccid_ccif1_scstrobe_pos 0 +#define reg_mccid_ccif1_scstrobe_len 7 +#define reg_mccid_ccif1_scstrobe_lsb 0 +#define p_reg_mccid_ccif0_fcwccif_7_0 0xF10E +#define reg_mccid_ccif0_fcwccif_7_0_pos 0 +#define reg_mccid_ccif0_fcwccif_7_0_len 8 +#define reg_mccid_ccif0_fcwccif_7_0_lsb 0 +#define p_reg_mccid_ccif0_fcwccif_13_8 0xF10F +#define reg_mccid_ccif0_fcwccif_13_8_pos 0 +#define reg_mccid_ccif0_fcwccif_13_8_len 6 +#define reg_mccid_ccif0_fcwccif_13_8_lsb 8 +#define p_reg_mccid_ccif0_state 0xF110 +#define reg_mccid_ccif0_state_pos 0 +#define reg_mccid_ccif0_state_len 1 +#define reg_mccid_ccif0_state_lsb 0 +#define p_reg_mccid_ccif0_acistate 0xF111 +#define reg_mccid_ccif0_acistate_pos 0 +#define reg_mccid_ccif0_acistate_len 1 +#define reg_mccid_ccif0_acistate_lsb 0 +#define p_reg_mccid_ccif1_fcwccif_7_0 0xF112 +#define reg_mccid_ccif1_fcwccif_7_0_pos 0 +#define reg_mccid_ccif1_fcwccif_7_0_len 8 +#define reg_mccid_ccif1_fcwccif_7_0_lsb 0 +#define p_reg_mccid_ccif1_fcwccif_13_8 0xF113 +#define reg_mccid_ccif1_fcwccif_13_8_pos 0 +#define reg_mccid_ccif1_fcwccif_13_8_len 6 +#define reg_mccid_ccif1_fcwccif_13_8_lsb 8 +#define p_reg_mccid_ccif1_state 0xF114 +#define reg_mccid_ccif1_state_pos 0 +#define reg_mccid_ccif1_state_len 1 +#define reg_mccid_ccif1_state_lsb 0 +#define p_reg_mccid_ccif1_acistate 0xF115 +#define reg_mccid_ccif1_acistate_pos 0 +#define reg_mccid_ccif1_acistate_len 1 +#define reg_mccid_ccif1_acistate_lsb 0 +#define r_reg_r_acif_saturate 0xF117 +#define reg_r_acif_saturate_pos 0 +#define reg_r_acif_saturate_len 8 +#define reg_r_acif_saturate_lsb 0 +#define p_reg_tmr_timer0_threshold_7_0 0xF118 +#define reg_tmr_timer0_threshold_7_0_pos 0 +#define reg_tmr_timer0_threshold_7_0_len 8 +#define reg_tmr_timer0_threshold_7_0_lsb 0 +#define p_reg_tmr_timer0_threshold_15_8 0xF119 +#define reg_tmr_timer0_threshold_15_8_pos 0 +#define reg_tmr_timer0_threshold_15_8_len 8 +#define reg_tmr_timer0_threshold_15_8_lsb 8 +#define p_reg_tmr_timer0_enable 0xF11A +#define reg_tmr_timer0_enable_pos 0 +#define reg_tmr_timer0_enable_len 1 +#define reg_tmr_timer0_enable_lsb 0 +#define p_reg_tmr_timer0_clk_sel 0xF11B +#define reg_tmr_timer0_clk_sel_pos 0 +#define reg_tmr_timer0_clk_sel_len 1 +#define reg_tmr_timer0_clk_sel_lsb 0 +#define p_reg_tmr_timer0_int 0xF11C +#define reg_tmr_timer0_int_pos 0 +#define reg_tmr_timer0_int_len 1 +#define reg_tmr_timer0_int_lsb 0 +#define p_reg_tmr_timer0_rst 0xF11D +#define reg_tmr_timer0_rst_pos 0 +#define reg_tmr_timer0_rst_len 1 +#define reg_tmr_timer0_rst_lsb 0 +#define r_reg_tmr_timer0_count_7_0 0xF11E +#define reg_tmr_timer0_count_7_0_pos 0 +#define reg_tmr_timer0_count_7_0_len 8 +#define reg_tmr_timer0_count_7_0_lsb 0 +#define r_reg_tmr_timer0_count_15_8 0xF11F +#define reg_tmr_timer0_count_15_8_pos 0 +#define reg_tmr_timer0_count_15_8_len 8 +#define reg_tmr_timer0_count_15_8_lsb 8 +#define p_reg_suspend 0xF120 +#define reg_suspend_pos 0 +#define reg_suspend_len 1 +#define reg_suspend_lsb 0 +#define p_reg_suspend_rdy 0xF121 +#define reg_suspend_rdy_pos 0 +#define reg_suspend_rdy_len 1 +#define reg_suspend_rdy_lsb 0 +#define p_reg_resume 0xF122 +#define reg_resume_pos 0 +#define reg_resume_len 1 +#define reg_resume_lsb 0 +#define p_reg_resume_rdy 0xF123 +#define reg_resume_rdy_pos 0 +#define reg_resume_rdy_len 1 +#define reg_resume_rdy_lsb 0 +#define p_reg_gp_trigger 0xF124 +#define reg_gp_trigger_pos 0 +#define reg_gp_trigger_len 1 +#define reg_gp_trigger_lsb 0 +#define p_reg_trigger_sel 0xF125 +#define reg_trigger_sel_pos 0 +#define reg_trigger_sel_len 2 +#define reg_trigger_sel_lsb 0 +#define p_reg_debug_ofdm 0xF126 +#define reg_debug_ofdm_pos 0 +#define reg_debug_ofdm_len 2 +#define reg_debug_ofdm_lsb 0 +#define p_reg_trigger_module_sel 0xF127 +#define reg_trigger_module_sel_pos 0 +#define reg_trigger_module_sel_len 6 +#define reg_trigger_module_sel_lsb 0 +#define p_reg_trigger_set_sel 0xF128 +#define reg_trigger_set_sel_pos 0 +#define reg_trigger_set_sel_len 6 +#define reg_trigger_set_sel_lsb 0 +#define p_reg_fw_int_mask_n 0xF129 +#define reg_fw_int_mask_n_pos 0 +#define reg_fw_int_mask_n_len 1 +#define reg_fw_int_mask_n_lsb 0 +#define p_reg_dioif_rst 0xF12A +#define reg_dioif_rst_pos 0 +#define reg_dioif_rst_len 1 +#define reg_dioif_rst_lsb 0 +#define p_reg_debug_group 0xF12B +#define reg_debug_group_pos 0 +#define reg_debug_group_len 4 +#define reg_debug_group_lsb 0 +#define p_reg_odbg_clk_sel 0xF12C +#define reg_odbg_clk_sel_pos 0 +#define reg_odbg_clk_sel_len 3 +#define reg_odbg_clk_sel_lsb 0 +#define p_reg_p_ccif_shift_fre 0xF12F +#define reg_p_ccif_shift_fre_pos 0 +#define reg_p_ccif_shift_fre_len 1 +#define reg_p_ccif_shift_fre_lsb 0 +#define p_reg_p_ccif_bandwidth_factor 0xF130 +#define reg_p_ccif_bandwidth_factor_pos 0 +#define reg_p_ccif_bandwidth_factor_len 3 +#define reg_p_ccif_bandwidth_factor_lsb 0 +#define p_reg_ccif_rst 0xF131 +#define reg_ccif_rst_pos 0 +#define reg_ccif_rst_len 1 +#define reg_ccif_rst_lsb 0 +#define p_reg_p_ccif_min_bandwidth 0xF132 +#define reg_p_ccif_min_bandwidth_pos 0 +#define reg_p_ccif_min_bandwidth_len 7 +#define reg_p_ccif_min_bandwidth_lsb 0 +#define p_reg_ccif_bq0_state 0xF133 +#define reg_ccif_bq0_state_pos 0 +#define reg_ccif_bq0_state_len 1 +#define reg_ccif_bq0_state_lsb 0 +#define p_reg_ccif_bq0_outputscaling 0xF134 +#define reg_ccif_bq0_outputscaling_pos 0 +#define reg_ccif_bq0_outputscaling_len 5 +#define reg_ccif_bq0_outputscaling_lsb 0 +#define p_reg_ccif_bq1_state 0xF135 +#define reg_ccif_bq1_state_pos 0 +#define reg_ccif_bq1_state_len 1 +#define reg_ccif_bq1_state_lsb 0 +#define p_reg_ccif_bq1_outputscaling 0xF136 +#define reg_ccif_bq1_outputscaling_pos 0 +#define reg_ccif_bq1_outputscaling_len 5 +#define reg_ccif_bq1_outputscaling_lsb 0 +#define p_reg_ccif_bq0_a1_7_0 0xF137 +#define reg_ccif_bq0_a1_7_0_pos 0 +#define reg_ccif_bq0_a1_7_0_len 8 +#define reg_ccif_bq0_a1_7_0_lsb 0 +#define p_reg_ccif_bq0_a1_13_8 0xF138 +#define reg_ccif_bq0_a1_13_8_pos 0 +#define reg_ccif_bq0_a1_13_8_len 6 +#define reg_ccif_bq0_a1_13_8_lsb 8 +#define p_reg_ccif_bq1_a1_7_0 0xF139 +#define reg_ccif_bq1_a1_7_0_pos 0 +#define reg_ccif_bq1_a1_7_0_len 8 +#define reg_ccif_bq1_a1_7_0_lsb 0 +#define p_reg_ccif_bq1_a1_13_8 0xF13A +#define reg_ccif_bq1_a1_13_8_pos 0 +#define reg_ccif_bq1_a1_13_8_len 6 +#define reg_ccif_bq1_a1_13_8_lsb 8 +#define p_reg_ccif_bq0_b1_7_0 0xF13B +#define reg_ccif_bq0_b1_7_0_pos 0 +#define reg_ccif_bq0_b1_7_0_len 8 +#define reg_ccif_bq0_b1_7_0_lsb 0 +#define p_reg_ccif_bq0_b1_13_8 0xF13C +#define reg_ccif_bq0_b1_13_8_pos 0 +#define reg_ccif_bq0_b1_13_8_len 6 +#define reg_ccif_bq0_b1_13_8_lsb 8 +#define p_reg_ccif_bq1_b1_7_0 0xF13D +#define reg_ccif_bq1_b1_7_0_pos 0 +#define reg_ccif_bq1_b1_7_0_len 8 +#define reg_ccif_bq1_b1_7_0_lsb 0 +#define p_reg_ccif_bq1_b1_13_8 0xF13E +#define reg_ccif_bq1_b1_13_8_pos 0 +#define reg_ccif_bq1_b1_13_8_len 6 +#define reg_ccif_bq1_b1_13_8_lsb 8 +#define p_reg_ccif_bq0_b2_7_0 0xF13F +#define reg_ccif_bq0_b2_7_0_pos 0 +#define reg_ccif_bq0_b2_7_0_len 8 +#define reg_ccif_bq0_b2_7_0_lsb 0 +#define p_reg_ccif_bq0_b2_13_8 0xF140 +#define reg_ccif_bq0_b2_13_8_pos 0 +#define reg_ccif_bq0_b2_13_8_len 6 +#define reg_ccif_bq0_b2_13_8_lsb 8 +#define p_reg_ccif_bq1_b2_7_0 0xF141 +#define reg_ccif_bq1_b2_7_0_pos 0 +#define reg_ccif_bq1_b2_7_0_len 8 +#define reg_ccif_bq1_b2_7_0_lsb 0 +#define p_reg_ccif_bq1_b2_13_8 0xF142 +#define reg_ccif_bq1_b2_13_8_pos 0 +#define reg_ccif_bq1_b2_13_8_len 6 +#define reg_ccif_bq1_b2_13_8_lsb 8 +#define p_reg_ccif_debug_rst 0xF143 +#define reg_ccif_debug_rst_pos 0 +#define reg_ccif_debug_rst_len 1 +#define reg_ccif_debug_rst_lsb 0 +#define p_reg_mccid_defaultccifscstrobe 0xF144 +#define reg_mccid_defaultccifscstrobe_pos 0 +#define reg_mccid_defaultccifscstrobe_len 7 +#define reg_mccid_defaultccifscstrobe_lsb 0 +#define p_reg_mccid_monitoringaci 0xF145 +#define reg_mccid_monitoringaci_pos 0 +#define reg_mccid_monitoringaci_len 1 +#define reg_mccid_monitoringaci_lsb 0 +#define p_reg_mccid_ispassmode 0xF146 +#define reg_mccid_ispassmode_pos 0 +#define reg_mccid_ispassmode_len 1 +#define reg_mccid_ispassmode_lsb 0 +#define p_reg_mccid_issteadystatemode 0xF147 +#define reg_mccid_issteadystatemode_pos 0 +#define reg_mccid_issteadystatemode_len 1 +#define reg_mccid_issteadystatemode_lsb 0 +#define p_reg_mccid_fixedgaincmp 0xF148 +#define reg_mccid_fixedgaincmp_pos 0 +#define reg_mccid_fixedgaincmp_len 1 +#define reg_mccid_fixedgaincmp_lsb 0 +#define p_reg_mccid_misscounter_reset 0xF149 +#define reg_mccid_misscounter_reset_pos 0 +#define reg_mccid_misscounter_reset_len 1 +#define reg_mccid_misscounter_reset_lsb 0 +#define p_reg_mccid_acwgcheckcciexist 0xF14A +#define reg_mccid_acwgcheckcciexist_pos 0 +#define reg_mccid_acwgcheckcciexist_len 1 +#define reg_mccid_acwgcheckcciexist_lsb 0 +#define p_reg_mccid_acidone 0xF14B +#define reg_mccid_acidone_pos 0 +#define reg_mccid_acidone_len 1 +#define reg_mccid_acidone_lsb 0 +#define p_reg_mccid_sxdesiredpower_7_0 0xF14C +#define reg_mccid_sxdesiredpower_7_0_pos 0 +#define reg_mccid_sxdesiredpower_7_0_len 8 +#define reg_mccid_sxdesiredpower_7_0_lsb 0 +#define p_reg_mccid_sxdesiredpower_9_8 0xF14D +#define reg_mccid_sxdesiredpower_9_8_pos 0 +#define reg_mccid_sxdesiredpower_9_8_len 2 +#define reg_mccid_sxdesiredpower_9_8_lsb 8 +#define p_reg_mccid_defaultccitimertriggerno 0xF14E +#define reg_mccid_defaultccitimertriggerno_pos 0 +#define reg_mccid_defaultccitimertriggerno_len 8 +#define reg_mccid_defaultccitimertriggerno_lsb 0 +#define p_reg_mccid_detectedmaxtonecountshift 0xF14F +#define reg_mccid_detectedmaxtonecountshift_pos 0 +#define reg_mccid_detectedmaxtonecountshift_len 3 +#define reg_mccid_detectedmaxtonecountshift_lsb 0 +#define p_reg_mccid_moveffttoccif_en 0xF151 +#define reg_mccid_moveffttoccif_en_pos 0 +#define reg_mccid_moveffttoccif_en_len 1 +#define reg_mccid_moveffttoccif_en_lsb 0 +#define p_reg_mccid_fftindextobfsfcwfactor_7_0 0xF152 +#define reg_mccid_fftindextobfsfcwfactor_7_0_pos 0 +#define reg_mccid_fftindextobfsfcwfactor_7_0_len 8 +#define reg_mccid_fftindextobfsfcwfactor_7_0_lsb 0 +#define p_reg_mccid_fftindextobfsfcwfactor_9_8 0xF153 +#define reg_mccid_fftindextobfsfcwfactor_9_8_pos 0 +#define reg_mccid_fftindextobfsfcwfactor_9_8_len 2 +#define reg_mccid_fftindextobfsfcwfactor_9_8_lsb 8 +#define p_reg_mccid_bfsfcwffttoindexfactor_7_0 0xF154 +#define reg_mccid_bfsfcwffttoindexfactor_7_0_pos 0 +#define reg_mccid_bfsfcwffttoindexfactor_7_0_len 8 +#define reg_mccid_bfsfcwffttoindexfactor_7_0_lsb 0 +#define p_reg_mccid_bfsfcwffttoindexfactor_10_8 0xF155 +#define reg_mccid_bfsfcwffttoindexfactor_10_8_pos 0 +#define reg_mccid_bfsfcwffttoindexfactor_10_8_len 3 +#define reg_mccid_bfsfcwffttoindexfactor_10_8_lsb 8 +#define p_reg_mccid_detectedaci 0xF156 +#define reg_mccid_detectedaci_pos 0 +#define reg_mccid_detectedaci_len 1 +#define reg_mccid_detectedaci_lsb 0 +#define r_reg_mccid_filter_enable 0xF157 +#define reg_mccid_filter_enable_pos 0 +#define reg_mccid_filter_enable_len 1 +#define reg_mccid_filter_enable_lsb 0 +#define p_reg_mccid_aciscstrobe 0xF158 +#define reg_mccid_aciscstrobe_pos 0 +#define reg_mccid_aciscstrobe_len 7 +#define reg_mccid_aciscstrobe_lsb 0 +#define p_reg_mccid_scanningaci 0xF159 +#define reg_mccid_scanningaci_pos 0 +#define reg_mccid_scanningaci_len 1 +#define reg_mccid_scanningaci_lsb 0 +#define p_reg_mccid_windowsizeacciwdcount_7_0 0xF15A +#define reg_mccid_windowsizeacciwdcount_7_0_pos 0 +#define reg_mccid_windowsizeacciwdcount_7_0_len 8 +#define reg_mccid_windowsizeacciwdcount_7_0_lsb 0 +#define p_reg_mccid_windowsizeacciwdcount_12_8 0xF15B +#define reg_mccid_windowsizeacciwdcount_12_8_pos 0 +#define reg_mccid_windowsizeacciwdcount_12_8_len 5 +#define reg_mccid_windowsizeacciwdcount_12_8_lsb 8 +#define p_reg_mccid_scannedacionly 0xF15C +#define reg_mccid_scannedacionly_pos 0 +#define reg_mccid_scannedacionly_len 1 +#define reg_mccid_scannedacionly_lsb 0 +#define p_reg_mccid_scfactor 0xF15D +#define reg_mccid_scfactor_pos 0 +#define reg_mccid_scfactor_len 5 +#define reg_mccid_scfactor_lsb 0 +#define p_reg_mccid_defaultevaluatingbandwidthfactor 0xF15E +#define reg_mccid_defaultevaluatingbandwidthfactor_pos 0 +#define reg_mccid_defaultevaluatingbandwidthfactor_len 3 +#define reg_mccid_defaultevaluatingbandwidthfactor_lsb 0 +#define p_reg_mccid_defaultacipowerlevel 0xF15F +#define reg_mccid_defaultacipowerlevel_pos 0 +#define reg_mccid_defaultacipowerlevel_len 3 +#define reg_mccid_defaultacipowerlevel_lsb 0 +#define r_reg_mccid_outputdagc1gain_7_0 0xF160 +#define reg_mccid_outputdagc1gain_7_0_pos 0 +#define reg_mccid_outputdagc1gain_7_0_len 8 +#define reg_mccid_outputdagc1gain_7_0_lsb 0 +#define r_reg_mccid_outputdagc1gain_9_8 0xF161 +#define reg_mccid_outputdagc1gain_9_8_pos 0 +#define reg_mccid_outputdagc1gain_9_8_len 2 +#define reg_mccid_outputdagc1gain_9_8_lsb 8 +#define r_reg_mccid_outputdagc1gainshift 0xF162 +#define reg_mccid_outputdagc1gainshift_pos 0 +#define reg_mccid_outputdagc1gainshift_len 4 +#define reg_mccid_outputdagc1gainshift_lsb 0 +#define p_reg_mccid_defaultacwgcheckccipowerlevel 0xF163 +#define reg_mccid_defaultacwgcheckccipowerlevel_pos 0 +#define reg_mccid_defaultacwgcheckccipowerlevel_len 3 +#define reg_mccid_defaultacwgcheckccipowerlevel_lsb 0 +#define p_reg_mccid_ccipowerlevelfactor 0xF166 +#define reg_mccid_ccipowerlevelfactor_pos 0 +#define reg_mccid_ccipowerlevelfactor_len 3 +#define reg_mccid_ccipowerlevelfactor_lsb 0 +#define p_reg_mccid_scstrobesearchingrange 0xF167 +#define reg_mccid_scstrobesearchingrange_pos 0 +#define reg_mccid_scstrobesearchingrange_len 8 +#define reg_mccid_scstrobesearchingrange_lsb 0 +#define p_reg_mccid_searchingno 0xF168 +#define reg_mccid_searchingno_pos 0 +#define reg_mccid_searchingno_len 6 +#define reg_mccid_searchingno_lsb 0 +#define p_reg_mccid_scannedacifrequencyresolution 0xF169 +#define reg_mccid_scannedacifrequencyresolution_pos 0 +#define reg_mccid_scannedacifrequencyresolution_len 4 +#define reg_mccid_scannedacifrequencyresolution_lsb 0 +#define p_reg_mccid_fft0_maskmaxtoneindex_7_0 0xF16A +#define reg_mccid_fft0_maskmaxtoneindex_7_0_pos 0 +#define reg_mccid_fft0_maskmaxtoneindex_7_0_len 8 +#define reg_mccid_fft0_maskmaxtoneindex_7_0_lsb 0 +#define p_reg_mccid_fft0_maskmaxtoneindex_12_8 0xF16B +#define reg_mccid_fft0_maskmaxtoneindex_12_8_pos 0 +#define reg_mccid_fft0_maskmaxtoneindex_12_8_len 5 +#define reg_mccid_fft0_maskmaxtoneindex_12_8_lsb 8 +#define p_reg_mccid_fft0_state 0xF16C +#define reg_mccid_fft0_state_pos 0 +#define reg_mccid_fft0_state_len 1 +#define reg_mccid_fft0_state_lsb 0 +#define p_reg_mccid_fft1_state 0xF16D +#define reg_mccid_fft1_state_pos 0 +#define reg_mccid_fft1_state_len 1 +#define reg_mccid_fft1_state_lsb 0 +#define p_reg_mccid_fft0_maskmintoneindex_7_0 0xF16E +#define reg_mccid_fft0_maskmintoneindex_7_0_pos 0 +#define reg_mccid_fft0_maskmintoneindex_7_0_len 8 +#define reg_mccid_fft0_maskmintoneindex_7_0_lsb 0 +#define p_reg_mccid_fft0_maskmintoneindex_12_8 0xF16F +#define reg_mccid_fft0_maskmintoneindex_12_8_pos 0 +#define reg_mccid_fft0_maskmintoneindex_12_8_len 5 +#define reg_mccid_fft0_maskmintoneindex_12_8_lsb 8 +#define p_reg_mccid_acipowerlevelfactor 0xF170 +#define reg_mccid_acipowerlevelfactor_pos 0 +#define reg_mccid_acipowerlevelfactor_len 3 +#define reg_mccid_acipowerlevelfactor_lsb 0 +#define p_reg_mccid_fft1_maskmaxtoneindex_7_0 0xF171 +#define reg_mccid_fft1_maskmaxtoneindex_7_0_pos 0 +#define reg_mccid_fft1_maskmaxtoneindex_7_0_len 8 +#define reg_mccid_fft1_maskmaxtoneindex_7_0_lsb 0 +#define p_reg_mccid_fft1_maskmaxtoneindex_12_8 0xF172 +#define reg_mccid_fft1_maskmaxtoneindex_12_8_pos 0 +#define reg_mccid_fft1_maskmaxtoneindex_12_8_len 5 +#define reg_mccid_fft1_maskmaxtoneindex_12_8_lsb 8 +#define p_reg_mccid_fft1_maskmintoneindex_7_0 0xF173 +#define reg_mccid_fft1_maskmintoneindex_7_0_pos 0 +#define reg_mccid_fft1_maskmintoneindex_7_0_len 8 +#define reg_mccid_fft1_maskmintoneindex_7_0_lsb 0 +#define p_reg_mccid_fft1_maskmintoneindex_12_8 0xF174 +#define reg_mccid_fft1_maskmintoneindex_12_8_pos 0 +#define reg_mccid_fft1_maskmintoneindex_12_8_len 5 +#define reg_mccid_fft1_maskmintoneindex_12_8_lsb 8 +#define p_reg_mccid_reset 0xF175 +#define reg_mccid_reset_pos 0 +#define reg_mccid_reset_len 1 +#define reg_mccid_reset_lsb 0 +#define p_reg_mccid_gaincmpreset 0xF176 +#define reg_mccid_gaincmpreset_pos 0 +#define reg_mccid_gaincmpreset_len 1 +#define reg_mccid_gaincmpreset_lsb 0 +#define p_reg_mccid_acwgreset 0xF177 +#define reg_mccid_acwgreset_pos 0 +#define reg_mccid_acwgreset_len 1 +#define reg_mccid_acwgreset_lsb 0 +#define p_reg_mccid_ccif0_ofsmstateenable 0xF178 +#define reg_mccid_ccif0_ofsmstateenable_pos 0 +#define reg_mccid_ccif0_ofsmstateenable_len 1 +#define reg_mccid_ccif0_ofsmstateenable_lsb 0 +#define p_reg_mccid_ccif1_ofsmstateenable 0xF179 +#define reg_mccid_ccif1_ofsmstateenable_pos 0 +#define reg_mccid_ccif1_ofsmstateenable_len 1 +#define reg_mccid_ccif1_ofsmstateenable_lsb 0 +#define p_reg_mccid_fft0_ofsmstateenable 0xF17A +#define reg_mccid_fft0_ofsmstateenable_pos 0 +#define reg_mccid_fft0_ofsmstateenable_len 1 +#define reg_mccid_fft0_ofsmstateenable_lsb 0 +#define p_reg_mccid_fft1_ofsmstateenable 0xF17B +#define reg_mccid_fft1_ofsmstateenable_pos 0 +#define reg_mccid_fft1_ofsmstateenable_len 1 +#define reg_mccid_fft1_ofsmstateenable_lsb 0 +#define p_reg_mccid_fftfiltermaskchange 0xF17C +#define reg_mccid_fftfiltermaskchange_pos 0 +#define reg_mccid_fftfiltermaskchange_len 1 +#define reg_mccid_fftfiltermaskchange_lsb 0 +#define r_reg_mccid_maxacipowertone_7_0 0xF17D +#define reg_mccid_maxacipowertone_7_0_pos 0 +#define reg_mccid_maxacipowertone_7_0_len 8 +#define reg_mccid_maxacipowertone_7_0_lsb 0 +#define r_reg_mccid_maxacipowertone_12_8 0xF17E +#define reg_mccid_maxacipowertone_12_8_pos 0 +#define reg_mccid_maxacipowertone_12_8_len 5 +#define reg_mccid_maxacipowertone_12_8_lsb 8 +#define r_reg_mccid_ccidisappear 0xF17F +#define reg_mccid_ccidisappear_pos 0 +#define reg_mccid_ccidisappear_len 1 +#define reg_mccid_ccidisappear_lsb 0 +#define r_reg_mccid_ccilocatordone 0xF182 +#define reg_mccid_ccilocatordone_pos 0 +#define reg_mccid_ccilocatordone_len 1 +#define reg_mccid_ccilocatordone_lsb 0 +#define p_reg_mccid_enablecciftrigger 0xF183 +#define reg_mccid_enablecciftrigger_pos 0 +#define reg_mccid_enablecciftrigger_len 1 +#define reg_mccid_enablecciftrigger_lsb 0 +#define p_reg_mccid_disableacwglaunchevaluationbandwidthtrigger 0xF184 +#define reg_mccid_disableacwglaunchevaluationbandwidthtrigger_pos 0 +#define reg_mccid_disableacwglaunchevaluationbandwidthtrigger_len 1 +#define reg_mccid_disableacwglaunchevaluationbandwidthtrigger_lsb 0 +#define p_reg_mccid_control_by_ofsm 0xF185 +#define reg_mccid_control_by_ofsm_pos 0 +#define reg_mccid_control_by_ofsm_len 1 +#define reg_mccid_control_by_ofsm_lsb 0 +#define p_reg_mccid_ofsmcontrolccilocator 0xF186 +#define reg_mccid_ofsmcontrolccilocator_pos 0 +#define reg_mccid_ofsmcontrolccilocator_len 1 +#define reg_mccid_ofsmcontrolccilocator_lsb 0 +#define p_reg_mccid_disablepotentialccitriggerccilocator 0xF187 +#define reg_mccid_disablepotentialccitriggerccilocator_pos 0 +#define reg_mccid_disablepotentialccitriggerccilocator_len 1 +#define reg_mccid_disablepotentialccitriggerccilocator_lsb 0 +#define p_reg_mccid_ofsmcontrolccitesting 0xF188 +#define reg_mccid_ofsmcontrolccitesting_pos 0 +#define reg_mccid_ofsmcontrolccitesting_len 1 +#define reg_mccid_ofsmcontrolccitesting_lsb 0 +#define p_reg_mccid_disableccitestingtriggercheckcci 0xF189 +#define reg_mccid_disableccitestingtriggercheckcci_pos 0 +#define reg_mccid_disableccitestingtriggercheckcci_len 1 +#define reg_mccid_disableccitestingtriggercheckcci_lsb 0 +#define p_reg_mccid_ofsmcontrolacwgsetccifscstrobe 0xF18A +#define reg_mccid_ofsmcontrolacwgsetccifscstrobe_pos 0 +#define reg_mccid_ofsmcontrolacwgsetccifscstrobe_len 1 +#define reg_mccid_ofsmcontrolacwgsetccifscstrobe_lsb 0 +#define p_reg_mccid_disableacwgevaluatingbandwidthtrigger 0xF18B +#define reg_mccid_disableacwgevaluatingbandwidthtrigger_pos 0 +#define reg_mccid_disableacwgevaluatingbandwidthtrigger_len 1 +#define reg_mccid_disableacwgevaluatingbandwidthtrigger_lsb 0 +#define p_reg_mccid_ofsmcontrolevaluatingbandwidth 0xF18C +#define reg_mccid_ofsmcontrolevaluatingbandwidth_pos 0 +#define reg_mccid_ofsmcontrolevaluatingbandwidth_len 1 +#define reg_mccid_ofsmcontrolevaluatingbandwidth_lsb 0 +#define p_reg_mccid_ofsmcontrolscanningaci 0xF18D +#define reg_mccid_ofsmcontrolscanningaci_pos 0 +#define reg_mccid_ofsmcontrolscanningaci_len 1 +#define reg_mccid_ofsmcontrolscanningaci_lsb 0 +#define p_reg_mccid_disablescanningaci 0xF18E +#define reg_mccid_disablescanningaci_pos 0 +#define reg_mccid_disablescanningaci_len 1 +#define reg_mccid_disablescanningaci_lsb 0 +#define p_reg_mccid_disableacwgccidetecting 0xF18F +#define reg_mccid_disableacwgccidetecting_pos 0 +#define reg_mccid_disableacwgccidetecting_len 1 +#define reg_mccid_disableacwgccidetecting_lsb 0 +#define p_reg_mccid_ofsmcontrolccitimertrigger 0xF190 +#define reg_mccid_ofsmcontrolccitimertrigger_pos 0 +#define reg_mccid_ofsmcontrolccitimertrigger_len 1 +#define reg_mccid_ofsmcontrolccitimertrigger_lsb 0 +#define p_reg_mccid_disableccitimertrigger 0xF191 +#define reg_mccid_disableccitimertrigger_pos 0 +#define reg_mccid_disableccitimertrigger_len 1 +#define reg_mccid_disableccitimertrigger_lsb 0 +#define p_reg_mccid_ofsmdisableccitriggercounting 0xF192 +#define reg_mccid_ofsmdisableccitriggercounting_pos 0 +#define reg_mccid_ofsmdisableccitriggercounting_len 1 +#define reg_mccid_ofsmdisableccitriggercounting_lsb 0 +#define p_reg_mccid_enableccifilteraci 0xF193 +#define reg_mccid_enableccifilteraci_pos 0 +#define reg_mccid_enableccifilteraci_len 1 +#define reg_mccid_enableccifilteraci_lsb 0 +#define p_reg_mccid_scannedfcwbfs_7_0 0xF194 +#define reg_mccid_scannedfcwbfs_7_0_pos 0 +#define reg_mccid_scannedfcwbfs_7_0_len 8 +#define reg_mccid_scannedfcwbfs_7_0_lsb 0 +#define p_reg_mccid_scannedfcwbfs_13_8 0xF195 +#define reg_mccid_scannedfcwbfs_13_8_pos 0 +#define reg_mccid_scannedfcwbfs_13_8_len 6 +#define reg_mccid_scannedfcwbfs_13_8_lsb 8 +#define p_reg_mccid_acwgevaluatingbandwidth 0xF196 +#define reg_mccid_acwgevaluatingbandwidth_pos 0 +#define reg_mccid_acwgevaluatingbandwidth_len 1 +#define reg_mccid_acwgevaluatingbandwidth_lsb 0 +#define p_reg_mccid_acwglaunchevaluationbandwidth 0xF197 +#define reg_mccid_acwglaunchevaluationbandwidth_pos 0 +#define reg_mccid_acwglaunchevaluationbandwidth_len 1 +#define reg_mccid_acwglaunchevaluationbandwidth_lsb 0 +#define p_reg_mccid_scannedcandidate 0xF198 +#define reg_mccid_scannedcandidate_pos 0 +#define reg_mccid_scannedcandidate_len 3 +#define reg_mccid_scannedcandidate_lsb 0 +#define p_reg_mccid_scstrobesearchingcandidate 0xF199 +#define reg_mccid_scstrobesearchingcandidate_pos 0 +#define reg_mccid_scstrobesearchingcandidate_len 2 +#define reg_mccid_scstrobesearchingcandidate_lsb 0 +#define p_reg_mccid_potentialcci 0xF19A +#define reg_mccid_potentialcci_pos 0 +#define reg_mccid_potentialcci_len 1 +#define reg_mccid_potentialcci_lsb 0 +#define p_reg_mccid_cciftimertrigger 0xF19B +#define reg_mccid_cciftimertrigger_pos 0 +#define reg_mccid_cciftimertrigger_len 1 +#define reg_mccid_cciftimertrigger_lsb 0 +#define p_reg_mccid_ccitesting 0xF19C +#define reg_mccid_ccitesting_pos 0 +#define reg_mccid_ccitesting_len 1 +#define reg_mccid_ccitesting_lsb 0 +#define p_reg_mccid_defaultccilocatormissno 0xF19D +#define reg_mccid_defaultccilocatormissno_pos 0 +#define reg_mccid_defaultccilocatormissno_len 8 +#define reg_mccid_defaultccilocatormissno_lsb 0 +#define p_reg_mccid_dagc1_use_despow 0xF19E +#define reg_mccid_dagc1_use_despow_pos 0 +#define reg_mccid_dagc1_use_despow_len 1 +#define reg_mccid_dagc1_use_despow_lsb 0 +#define p_reg_mccid_scannedacifrequencybegin_7_0 0xF19F +#define reg_mccid_scannedacifrequencybegin_7_0_pos 0 +#define reg_mccid_scannedacifrequencybegin_7_0_len 8 +#define reg_mccid_scannedacifrequencybegin_7_0_lsb 0 +#define p_reg_mccid_scannedacifrequencybegin_13_8 0xF1A0 +#define reg_mccid_scannedacifrequencybegin_13_8_pos 0 +#define reg_mccid_scannedacifrequencybegin_13_8_len 6 +#define reg_mccid_scannedacifrequencybegin_13_8_lsb 8 +#define p_reg_mccid_scannedacifrequencyend_7_0 0xF1A1 +#define reg_mccid_scannedacifrequencyend_7_0_pos 0 +#define reg_mccid_scannedacifrequencyend_7_0_len 8 +#define reg_mccid_scannedacifrequencyend_7_0_lsb 0 +#define p_reg_mccid_scannedacifrequencyend_13_8 0xF1A2 +#define reg_mccid_scannedacifrequencyend_13_8_pos 0 +#define reg_mccid_scannedacifrequencyend_13_8_len 6 +#define reg_mccid_scannedacifrequencyend_13_8_lsb 8 +#define p_reg_bfs_fcw_7_0 0xF1A3 +#define reg_bfs_fcw_7_0_pos 0 +#define reg_bfs_fcw_7_0_len 8 +#define reg_bfs_fcw_7_0_lsb 0 +#define p_reg_bfs_fcw_15_8 0xF1A4 +#define reg_bfs_fcw_15_8_pos 0 +#define reg_bfs_fcw_15_8_len 8 +#define reg_bfs_fcw_15_8_lsb 8 +#define p_reg_bfs_fcw_22_16 0xF1A5 +#define reg_bfs_fcw_22_16_pos 0 +#define reg_bfs_fcw_22_16_len 7 +#define reg_bfs_fcw_22_16_lsb 16 +#define p_reg_cfoe_fcw_inv 0xF1A6 +#define reg_cfoe_fcw_inv_pos 0 +#define reg_cfoe_fcw_inv_len 1 +#define reg_cfoe_fcw_inv_lsb 0 +#define p_reg_bfs_0if 0xF1A7 +#define reg_bfs_0if_pos 0 +#define reg_bfs_0if_len 1 +#define reg_bfs_0if_lsb 0 +#define p_reg_sadc_clk 0xF1A9 +#define reg_sadc_clk_pos 0 +#define reg_sadc_clk_len 1 +#define reg_sadc_clk_lsb 0 +#define p_reg_sadc_tx 0xF1AA +#define reg_sadc_tx_pos 0 +#define reg_sadc_tx_len 1 +#define reg_sadc_tx_lsb 0 +#define p_reg_sadc_rx 0xF1AB +#define reg_sadc_rx_pos 0 +#define reg_sadc_rx_len 1 +#define reg_sadc_rx_lsb 0 +#define p_reg_sadc_cs 0xF1AC +#define reg_sadc_cs_pos 0 +#define reg_sadc_cs_len 1 +#define reg_sadc_cs_lsb 0 +#define p_reg_fix_fcw_7_0 0xF1AD +#define reg_fix_fcw_7_0_pos 0 +#define reg_fix_fcw_7_0_len 8 +#define reg_fix_fcw_7_0_lsb 0 +#define p_reg_fix_fcw_15_8 0xF1AE +#define reg_fix_fcw_15_8_pos 0 +#define reg_fix_fcw_15_8_len 8 +#define reg_fix_fcw_15_8_lsb 8 +#define p_reg_fix_fcw_22_16 0xF1AF +#define reg_fix_fcw_22_16_pos 0 +#define reg_fix_fcw_22_16_len 7 +#define reg_fix_fcw_22_16_lsb 16 +#define r_reg_bfs_fcw_offset_7_0 0xF1B0 +#define reg_bfs_fcw_offset_7_0_pos 0 +#define reg_bfs_fcw_offset_7_0_len 8 +#define reg_bfs_fcw_offset_7_0_lsb 0 +#define r_reg_bfs_fcw_offset_15_8 0xF1B1 +#define reg_bfs_fcw_offset_15_8_pos 0 +#define reg_bfs_fcw_offset_15_8_len 8 +#define reg_bfs_fcw_offset_15_8_lsb 8 +#define r_reg_bfs_fcw_offset_22_16 0xF1B2 +#define reg_bfs_fcw_offset_22_16_pos 0 +#define reg_bfs_fcw_offset_22_16_len 7 +#define reg_bfs_fcw_offset_22_16_lsb 16 +#define r_bfs_fcw_q_7_0 0xF1B3 +#define bfs_fcw_q_7_0_pos 0 +#define bfs_fcw_q_7_0_len 8 +#define bfs_fcw_q_7_0_lsb 0 +#define r_bfs_fcw_q_15_8 0xF1B4 +#define bfs_fcw_q_15_8_pos 0 +#define bfs_fcw_q_15_8_len 8 +#define bfs_fcw_q_15_8_lsb 8 +#define r_bfs_fcw_q_22_16 0xF1B5 +#define bfs_fcw_q_22_16_pos 0 +#define bfs_fcw_q_22_16_len 7 +#define bfs_fcw_q_22_16_lsb 16 +#define p_reg_dagc3_use_despow 0xF1B6 +#define reg_dagc3_use_despow_pos 0 +#define reg_dagc3_use_despow_len 1 +#define reg_dagc3_use_despow_lsb 0 +#define p_reg_dagc3_log_2_accumulate 0xF1B7 +#define reg_dagc3_log_2_accumulate_pos 0 +#define reg_dagc3_log_2_accumulate_len 5 +#define reg_dagc3_log_2_accumulate_lsb 0 +#define p_reg_dagc3_desired_level_7_0 0xF1BC +#define reg_dagc3_desired_level_7_0_pos 0 +#define reg_dagc3_desired_level_7_0_len 8 +#define reg_dagc3_desired_level_7_0_lsb 0 +#define p_reg_dagc3_desired_level_8 0xF1BD +#define reg_dagc3_desired_level_8_pos 0 +#define reg_dagc3_desired_level_8_len 1 +#define reg_dagc3_desired_level_8_lsb 8 +#define p_reg_dagc3_apply_delay 0xF1BE +#define reg_dagc3_apply_delay_pos 0 +#define reg_dagc3_apply_delay_len 7 +#define reg_dagc3_apply_delay_lsb 0 +#define p_reg_dagc3_bp_scale 0xF1BF +#define reg_dagc3_bp_scale_pos 0 +#define reg_dagc3_bp_scale_len 3 +#define reg_dagc3_bp_scale_lsb 0 +#define p_reg_dagc3_in_sat_cnt_7_0 0xF1C0 +#define reg_dagc3_in_sat_cnt_7_0_pos 0 +#define reg_dagc3_in_sat_cnt_7_0_len 8 +#define reg_dagc3_in_sat_cnt_7_0_lsb 0 +#define p_reg_dagc3_in_sat_cnt_15_8 0xF1C1 +#define reg_dagc3_in_sat_cnt_15_8_pos 0 +#define reg_dagc3_in_sat_cnt_15_8_len 8 +#define reg_dagc3_in_sat_cnt_15_8_lsb 8 +#define p_reg_dagc3_in_sat_cnt_23_16 0xF1C2 +#define reg_dagc3_in_sat_cnt_23_16_pos 0 +#define reg_dagc3_in_sat_cnt_23_16_len 8 +#define reg_dagc3_in_sat_cnt_23_16_lsb 16 +#define p_reg_dagc3_in_sat_cnt_31_24 0xF1C3 +#define reg_dagc3_in_sat_cnt_31_24_pos 0 +#define reg_dagc3_in_sat_cnt_31_24_len 8 +#define reg_dagc3_in_sat_cnt_31_24_lsb 24 +#define p_reg_dagc3_out_sat_cnt_7_0 0xF1C4 +#define reg_dagc3_out_sat_cnt_7_0_pos 0 +#define reg_dagc3_out_sat_cnt_7_0_len 8 +#define reg_dagc3_out_sat_cnt_7_0_lsb 0 +#define p_reg_dagc3_out_sat_cnt_15_8 0xF1C5 +#define reg_dagc3_out_sat_cnt_15_8_pos 0 +#define reg_dagc3_out_sat_cnt_15_8_len 8 +#define reg_dagc3_out_sat_cnt_15_8_lsb 8 +#define p_reg_dagc3_out_sat_cnt_23_16 0xF1C6 +#define reg_dagc3_out_sat_cnt_23_16_pos 0 +#define reg_dagc3_out_sat_cnt_23_16_len 8 +#define reg_dagc3_out_sat_cnt_23_16_lsb 16 +#define p_reg_dagc3_out_sat_cnt_31_24 0xF1C7 +#define reg_dagc3_out_sat_cnt_31_24_pos 0 +#define reg_dagc3_out_sat_cnt_31_24_len 8 +#define reg_dagc3_out_sat_cnt_31_24_lsb 24 +#define r_bfs_dagc3_multiplier_7_0 0xF1C8 +#define bfs_dagc3_multiplier_7_0_pos 0 +#define bfs_dagc3_multiplier_7_0_len 8 +#define bfs_dagc3_multiplier_7_0_lsb 0 +#define r_bfs_dagc3_multiplier_15_8 0xF1C9 +#define bfs_dagc3_multiplier_15_8_pos 0 +#define bfs_dagc3_multiplier_15_8_len 8 +#define bfs_dagc3_multiplier_15_8_lsb 8 +#define r_bfs_dagc3_right_shift_bits 0xF1CA +#define bfs_dagc3_right_shift_bits_pos 0 +#define bfs_dagc3_right_shift_bits_len 4 +#define bfs_dagc3_right_shift_bits_lsb 0 +#define p_reg_dagc3_fixed_gain_7_0 0xF1CB +#define reg_dagc3_fixed_gain_7_0_pos 0 +#define reg_dagc3_fixed_gain_7_0_len 8 +#define reg_dagc3_fixed_gain_7_0_lsb 0 +#define p_reg_dagc3_fixed_gain_11_8 0xF1CC +#define reg_dagc3_fixed_gain_11_8_pos 0 +#define reg_dagc3_fixed_gain_11_8_len 4 +#define reg_dagc3_fixed_gain_11_8_lsb 8 +#define p_reg_f_adc_7_0 0xF1CD +#define reg_f_adc_7_0_pos 0 +#define reg_f_adc_7_0_len 8 +#define reg_f_adc_7_0_lsb 0 +#define p_reg_f_adc_15_8 0xF1CE +#define reg_f_adc_15_8_pos 0 +#define reg_f_adc_15_8_len 8 +#define reg_f_adc_15_8_lsb 8 +#define p_reg_f_adc_23_16 0xF1CF +#define reg_f_adc_23_16_pos 0 +#define reg_f_adc_23_16_len 8 +#define reg_f_adc_23_16_lsb 16 +#define p_reg_fste_frac_step_size_7_0 0xF1D0 +#define reg_fste_frac_step_size_7_0_pos 0 +#define reg_fste_frac_step_size_7_0_len 8 +#define reg_fste_frac_step_size_7_0_lsb 0 +#define p_reg_fste_frac_step_size_15_8 0xF1D1 +#define reg_fste_frac_step_size_15_8_pos 0 +#define reg_fste_frac_step_size_15_8_len 8 +#define reg_fste_frac_step_size_15_8_lsb 8 +#define p_reg_fste_frac_step_size_19_16 0xF1D2 +#define reg_fste_frac_step_size_19_16_pos 0 +#define reg_fste_frac_step_size_19_16_len 4 +#define reg_fste_frac_step_size_19_16_lsb 16 +#define r_intp_mu_7_0 0xF1D3 +#define intp_mu_7_0_pos 0 +#define intp_mu_7_0_len 8 +#define intp_mu_7_0_lsb 0 +#define r_intp_mu_15_8 0xF1D4 +#define intp_mu_15_8_pos 0 +#define intp_mu_15_8_len 8 +#define intp_mu_15_8_lsb 8 +#define r_intp_mu_23_16 0xF1D5 +#define intp_mu_23_16_pos 0 +#define intp_mu_23_16_len 8 +#define intp_mu_23_16_lsb 16 +#define r_intp_mu_25_24 0xF1D6 +#define intp_mu_25_24_pos 0 +#define intp_mu_25_24_len 2 +#define intp_mu_25_24_lsb 24 +#define p_intp_muq_7_0 0xF1D7 +#define intp_muq_7_0_pos 0 +#define intp_muq_7_0_len 8 +#define intp_muq_7_0_lsb 0 +#define p_intp_muq_15_8 0xF1D8 +#define intp_muq_15_8_pos 0 +#define intp_muq_15_8_len 8 +#define intp_muq_15_8_lsb 8 +#define p_intp_muq_23_16 0xF1D9 +#define intp_muq_23_16_pos 0 +#define intp_muq_23_16_len 8 +#define intp_muq_23_16_lsb 16 +#define p_reg_sfoe_inv 0xF1DA +#define reg_sfoe_inv_pos 0 +#define reg_sfoe_inv_len 1 +#define reg_sfoe_inv_lsb 0 +#define p_intp_ext_en 0xF1DB +#define intp_ext_en_pos 0 +#define intp_ext_en_len 1 +#define intp_ext_en_lsb 0 +#define r_intp_ext_done 0xF1DC +#define intp_ext_done_pos 0 +#define intp_ext_done_len 1 +#define intp_ext_done_lsb 0 +#define p_intp_ext_in_7_0 0xF1DD +#define intp_ext_in_7_0_pos 0 +#define intp_ext_in_7_0_len 8 +#define intp_ext_in_7_0_lsb 0 +#define p_intp_ext_in_15_8 0xF1DE +#define intp_ext_in_15_8_pos 0 +#define intp_ext_in_15_8_len 8 +#define intp_ext_in_15_8_lsb 8 +#define p_intp_ext_in_23_16 0xF1DF +#define intp_ext_in_23_16_pos 0 +#define intp_ext_in_23_16_len 8 +#define intp_ext_in_23_16_lsb 16 +#define p_intp_ext_in_25_24 0xF1E0 +#define intp_ext_in_25_24_pos 0 +#define intp_ext_in_25_24_len 2 +#define intp_ext_in_25_24_lsb 24 +#define r_intp_ext_out_7_0 0xF1E1 +#define intp_ext_out_7_0_pos 0 +#define intp_ext_out_7_0_len 8 +#define intp_ext_out_7_0_lsb 0 +#define r_intp_ext_out_15_8 0xF1E2 +#define intp_ext_out_15_8_pos 0 +#define intp_ext_out_15_8_len 8 +#define intp_ext_out_15_8_lsb 8 +#define r_intp_ext_out_23_16 0xF1E3 +#define intp_ext_out_23_16_pos 0 +#define intp_ext_out_23_16_len 8 +#define intp_ext_out_23_16_lsb 16 +#define r_intp_ext_out_28_24 0xF1E4 +#define intp_ext_out_28_24_pos 0 +#define intp_ext_out_28_24_len 5 +#define intp_ext_out_28_24_lsb 24 +#define p_reg_agc_rst 0xF1E5 +#define reg_agc_rst_pos 0 +#define reg_agc_rst_len 1 +#define reg_agc_rst_lsb 0 +#define p_rf_agc_en 0xF1E6 +#define rf_agc_en_pos 0 +#define rf_agc_en_len 1 +#define rf_agc_en_lsb 0 +#define p_agc_lock 0xF1E7 +#define agc_lock_pos 0 +#define agc_lock_len 1 +#define agc_lock_lsb 0 +#define p_reg_tinr_rst 0xF1E8 +#define reg_tinr_rst_pos 0 +#define reg_tinr_rst_len 1 +#define reg_tinr_rst_lsb 0 +#define p_reg_tinr_en 0xF1E9 +#define reg_tinr_en_pos 0 +#define reg_tinr_en_len 1 +#define reg_tinr_en_lsb 0 +#define p_reg_bfs_en 0xF1EA +#define reg_bfs_en_pos 0 +#define reg_bfs_en_len 1 +#define reg_bfs_en_lsb 0 +#define p_reg_bfs_rst 0xF1EB +#define reg_bfs_rst_pos 0 +#define reg_bfs_rst_len 1 +#define reg_bfs_rst_lsb 0 +#define p_reg_bfs_byp 0xF1EC +#define reg_bfs_byp_pos 0 +#define reg_bfs_byp_len 1 +#define reg_bfs_byp_lsb 0 +#define p_intp_en 0xF1EF +#define intp_en_pos 0 +#define intp_en_len 1 +#define intp_en_lsb 0 +#define p_intp_rst 0xF1F0 +#define intp_rst_pos 0 +#define intp_rst_len 1 +#define intp_rst_lsb 0 +#define p_reg_p_acif_en 0xF1F2 +#define reg_p_acif_en_pos 0 +#define reg_p_acif_en_len 1 +#define reg_p_acif_en_lsb 0 +#define p_reg_p_acif_rst 0xF1F3 +#define reg_p_acif_rst_pos 0 +#define reg_p_acif_rst_len 1 +#define reg_p_acif_rst_lsb 0 +#define p_reg_p_acif_byp 0xF1F4 +#define reg_p_acif_byp_pos 0 +#define reg_p_acif_byp_len 1 +#define reg_p_acif_byp_lsb 0 +#define p_dagc2_rst 0xF1F6 +#define dagc2_rst_pos 0 +#define dagc2_rst_len 1 +#define dagc2_rst_lsb 0 +#define p_dagc2_en 0xF1F7 +#define dagc2_en_pos 0 +#define dagc2_en_len 1 +#define dagc2_en_lsb 0 +#define p_dagc2_mode 0xF1F8 +#define dagc2_mode_pos 0 +#define dagc2_mode_len 2 +#define dagc2_mode_lsb 0 +#define p_dagc2_done 0xF1F9 +#define dagc2_done_pos 0 +#define dagc2_done_len 1 +#define dagc2_done_lsb 0 +#define p_dagc3_rst 0xF1FA +#define dagc3_rst_pos 0 +#define dagc3_rst_len 1 +#define dagc3_rst_lsb 0 +#define p_dagc3_en 0xF1FB +#define dagc3_en_pos 0 +#define dagc3_en_len 1 +#define dagc3_en_lsb 0 +#define p_dagc3_mode 0xF1FC +#define dagc3_mode_pos 0 +#define dagc3_mode_len 2 +#define dagc3_mode_lsb 0 +#define p_dagc3_done 0xF1FD +#define dagc3_done_pos 0 +#define dagc3_done_len 1 +#define dagc3_done_lsb 0 +#define p_reg_dagc2_desired_level_7_0 0xF202 +#define reg_dagc2_desired_level_7_0_pos 0 +#define reg_dagc2_desired_level_7_0_len 8 +#define reg_dagc2_desired_level_7_0_lsb 0 +#define p_reg_dagc2_desired_level_8 0xF203 +#define reg_dagc2_desired_level_8_pos 0 +#define reg_dagc2_desired_level_8_len 1 +#define reg_dagc2_desired_level_8_lsb 8 +#define p_reg_dagc2_apply_delay 0xF204 +#define reg_dagc2_apply_delay_pos 0 +#define reg_dagc2_apply_delay_len 7 +#define reg_dagc2_apply_delay_lsb 0 +#define p_reg_dagc2_bypass_scale_ctl 0xF205 +#define reg_dagc2_bypass_scale_ctl_pos 0 +#define reg_dagc2_bypass_scale_ctl_len 3 +#define reg_dagc2_bypass_scale_ctl_lsb 0 +#define p_reg_dagc2_programmable_shift2 0xF206 +#define reg_dagc2_programmable_shift2_pos 0 +#define reg_dagc2_programmable_shift2_len 8 +#define reg_dagc2_programmable_shift2_lsb 0 +#define p_reg_dagc2_in_sat_cnt_7_0 0xF207 +#define reg_dagc2_in_sat_cnt_7_0_pos 0 +#define reg_dagc2_in_sat_cnt_7_0_len 8 +#define reg_dagc2_in_sat_cnt_7_0_lsb 0 +#define p_reg_dagc2_in_sat_cnt_15_8 0xF208 +#define reg_dagc2_in_sat_cnt_15_8_pos 0 +#define reg_dagc2_in_sat_cnt_15_8_len 8 +#define reg_dagc2_in_sat_cnt_15_8_lsb 8 +#define p_reg_dagc2_in_sat_cnt_23_16 0xF209 +#define reg_dagc2_in_sat_cnt_23_16_pos 0 +#define reg_dagc2_in_sat_cnt_23_16_len 8 +#define reg_dagc2_in_sat_cnt_23_16_lsb 16 +#define p_reg_dagc2_in_sat_cnt_31_24 0xF20A +#define reg_dagc2_in_sat_cnt_31_24_pos 0 +#define reg_dagc2_in_sat_cnt_31_24_len 8 +#define reg_dagc2_in_sat_cnt_31_24_lsb 24 +#define p_reg_dagc2_out_sat_cnt_7_0 0xF20B +#define reg_dagc2_out_sat_cnt_7_0_pos 0 +#define reg_dagc2_out_sat_cnt_7_0_len 8 +#define reg_dagc2_out_sat_cnt_7_0_lsb 0 +#define p_reg_dagc2_out_sat_cnt_15_8 0xF20C +#define reg_dagc2_out_sat_cnt_15_8_pos 0 +#define reg_dagc2_out_sat_cnt_15_8_len 8 +#define reg_dagc2_out_sat_cnt_15_8_lsb 8 +#define p_reg_dagc2_out_sat_cnt_23_16 0xF20D +#define reg_dagc2_out_sat_cnt_23_16_pos 0 +#define reg_dagc2_out_sat_cnt_23_16_len 8 +#define reg_dagc2_out_sat_cnt_23_16_lsb 16 +#define p_reg_dagc2_out_sat_cnt_31_24 0xF20E +#define reg_dagc2_out_sat_cnt_31_24_pos 0 +#define reg_dagc2_out_sat_cnt_31_24_len 8 +#define reg_dagc2_out_sat_cnt_31_24_lsb 24 +#define r_reg_dagc2_multiplier_7_0 0xF20F +#define reg_dagc2_multiplier_7_0_pos 0 +#define reg_dagc2_multiplier_7_0_len 8 +#define reg_dagc2_multiplier_7_0_lsb 0 +#define r_reg_dagc2_multiplier_15_8 0xF210 +#define reg_dagc2_multiplier_15_8_pos 0 +#define reg_dagc2_multiplier_15_8_len 8 +#define reg_dagc2_multiplier_15_8_lsb 8 +#define r_reg_dagc2_right_shift_bits 0xF211 +#define reg_dagc2_right_shift_bits_pos 0 +#define reg_dagc2_right_shift_bits_len 4 +#define reg_dagc2_right_shift_bits_lsb 0 +#define p_reg_dagc2_smbuf_err 0xF212 +#define reg_dagc2_smbuf_err_pos 0 +#define reg_dagc2_smbuf_err_len 1 +#define reg_dagc2_smbuf_err_lsb 0 +#define p_reg_dagc2_cplxconj 0xF213 +#define reg_dagc2_cplxconj_pos 0 +#define reg_dagc2_cplxconj_len 1 +#define reg_dagc2_cplxconj_lsb 0 +#define p_reg_dagc2_use_despow 0xF214 +#define reg_dagc2_use_despow_pos 0 +#define reg_dagc2_use_despow_len 1 +#define reg_dagc2_use_despow_lsb 0 +#define p_reg_dagc2_log_2_accumulate 0xF215 +#define reg_dagc2_log_2_accumulate_pos 0 +#define reg_dagc2_log_2_accumulate_len 5 +#define reg_dagc2_log_2_accumulate_lsb 0 +#define r_dagc2_dca_gain 0xF216 +#define dagc2_dca_gain_pos 0 +#define dagc2_dca_gain_len 8 +#define dagc2_dca_gain_lsb 0 +#define p_reg_dca_gain_offset 0xF217 +#define reg_dca_gain_offset_pos 0 +#define reg_dca_gain_offset_len 8 +#define reg_dca_gain_offset_lsb 0 +#define p_reg_dagc2_FG_mode 0xF218 +#define reg_dagc2_FG_mode_pos 0 +#define reg_dagc2_FG_mode_len 1 +#define reg_dagc2_FG_mode_lsb 0 +#define p_reg_dagc2_fixed_gain_7_0 0xF219 +#define reg_dagc2_fixed_gain_7_0_pos 0 +#define reg_dagc2_fixed_gain_7_0_len 8 +#define reg_dagc2_fixed_gain_7_0_lsb 0 +#define p_reg_dagc2_fixed_gain_11_8 0xF21A +#define reg_dagc2_fixed_gain_11_8_pos 0 +#define reg_dagc2_fixed_gain_11_8_len 4 +#define reg_dagc2_fixed_gain_11_8_lsb 8 +#define p_reg_td_debug_7_0 0xF21B +#define reg_td_debug_7_0_pos 0 +#define reg_td_debug_7_0_len 8 +#define reg_td_debug_7_0_lsb 0 +#define p_reg_td_debug_15_8 0xF21C +#define reg_td_debug_15_8_pos 0 +#define reg_td_debug_15_8_len 8 +#define reg_td_debug_15_8_lsb 8 +#define p_reg_td_debug_23_16 0xF21D +#define reg_td_debug_23_16_pos 0 +#define reg_td_debug_23_16_len 8 +#define reg_td_debug_23_16_lsb 16 +#define p_reg_td_debug_30_24 0xF21E +#define reg_td_debug_30_24_pos 0 +#define reg_td_debug_30_24_len 7 +#define reg_td_debug_30_24_lsb 24 +#define g_reg_clk_sys40 0xF90E +#define reg_clk_sys40_pos 0 +#define reg_clk_sys40_len 1 +#define reg_clk_sys40_lsb 0 +#define g_reg_intp_sys_polarity 0xF90F +#define reg_intp_sys_polarity_pos 0 +#define reg_intp_sys_polarity_len 1 +#define reg_intp_sys_polarity_lsb 0 +#define g_reg_intp_sys_sc_7_0 0xF910 +#define reg_intp_sys_sc_7_0_pos 0 +#define reg_intp_sys_sc_7_0_len 8 +#define reg_intp_sys_sc_7_0_lsb 0 +#define g_reg_intp_sys_sc_15_8 0xF911 +#define reg_intp_sys_sc_15_8_pos 0 +#define reg_intp_sys_sc_15_8_len 8 +#define reg_intp_sys_sc_15_8_lsb 8 +#define g_reg_intp_sys_sc_23_16 0xF912 +#define reg_intp_sys_sc_23_16_pos 0 +#define reg_intp_sys_sc_23_16_len 8 +#define reg_intp_sys_sc_23_16_lsb 16 +#define g_reg_intp_sys_sc_26_24 0xF913 +#define reg_intp_sys_sc_26_24_pos 0 +#define reg_intp_sys_sc_26_24_len 3 +#define reg_intp_sys_sc_26_24_lsb 24 +#define g_reg_ofsm_clk 0xF914 +#define reg_ofsm_clk_pos 0 +#define reg_ofsm_clk_len 3 +#define reg_ofsm_clk_lsb 0 +#define g_reg_fclk_cfg 0xF915 +#define reg_fclk_cfg_pos 0 +#define reg_fclk_cfg_len 1 +#define reg_fclk_cfg_lsb 0 +#define g_reg_fclk_idi 0xF916 +#define reg_fclk_idi_pos 0 +#define reg_fclk_idi_len 1 +#define reg_fclk_idi_lsb 0 +#define g_reg_fclk_odi 0xF917 +#define reg_fclk_odi_pos 0 +#define reg_fclk_odi_len 1 +#define reg_fclk_odi_lsb 0 +#define g_reg_fclk_rsd 0xF918 +#define reg_fclk_rsd_pos 0 +#define reg_fclk_rsd_len 1 +#define reg_fclk_rsd_lsb 0 +#define g_reg_fclk_vtb 0xF919 +#define reg_fclk_vtb_pos 0 +#define reg_fclk_vtb_len 1 +#define reg_fclk_vtb_lsb 0 +#define g_reg_fclk_cste 0xF91A +#define reg_fclk_cste_pos 0 +#define reg_fclk_cste_len 1 +#define reg_fclk_cste_lsb 0 +#define g_reg_fclk_mp2if 0xF91B +#define reg_fclk_mp2if_pos 0 +#define reg_fclk_mp2if_len 1 +#define reg_fclk_mp2if_lsb 0 +#define p_reg_adcout_sync 0xFA00 +#define reg_adcout_sync_pos 0 +#define reg_adcout_sync_len 1 +#define reg_adcout_sync_lsb 0 +#define p_reg_dagc2o_edge1 0xFA01 +#define reg_dagc2o_edge1_pos 0 +#define reg_dagc2o_edge1_len 1 +#define reg_dagc2o_edge1_lsb 0 +#define p_reg_dagc2o_edge0 0xFA02 +#define reg_dagc2o_edge0_pos 0 +#define reg_dagc2o_edge0_len 1 +#define reg_dagc2o_edge0_lsb 0 +#define p_reg_second_rom_on 0xFA03 +#define reg_second_rom_on_pos 0 +#define reg_second_rom_on_len 1 +#define reg_second_rom_on_lsb 0 +#define p_reg_bypass_host2tuner 0xFA04 +#define reg_bypass_host2tuner_pos 0 +#define reg_bypass_host2tuner_len 1 +#define reg_bypass_host2tuner_lsb 0 +#define p_cfoe_NS_coeff1_7_0 0xF400 +#define cfoe_NS_coeff1_7_0_pos 0 +#define cfoe_NS_coeff1_7_0_len 8 +#define cfoe_NS_coeff1_7_0_lsb 0 +#define p_cfoe_NS_coeff1_15_8 0xF401 +#define cfoe_NS_coeff1_15_8_pos 0 +#define cfoe_NS_coeff1_15_8_len 8 +#define cfoe_NS_coeff1_15_8_lsb 8 +#define p_cfoe_NS_coeff1_23_16 0xF402 +#define cfoe_NS_coeff1_23_16_pos 0 +#define cfoe_NS_coeff1_23_16_len 8 +#define cfoe_NS_coeff1_23_16_lsb 16 +#define p_cfoe_NS_coeff1_25_24 0xF403 +#define cfoe_NS_coeff1_25_24_pos 0 +#define cfoe_NS_coeff1_25_24_len 2 +#define cfoe_NS_coeff1_25_24_lsb 24 +#define p_cfoe_NS_coeff2_7_0 0xF404 +#define cfoe_NS_coeff2_7_0_pos 0 +#define cfoe_NS_coeff2_7_0_len 8 +#define cfoe_NS_coeff2_7_0_lsb 0 +#define p_cfoe_NS_coeff2_15_8 0xF405 +#define cfoe_NS_coeff2_15_8_pos 0 +#define cfoe_NS_coeff2_15_8_len 8 +#define cfoe_NS_coeff2_15_8_lsb 8 +#define p_cfoe_NS_coeff2_23_16 0xF406 +#define cfoe_NS_coeff2_23_16_pos 0 +#define cfoe_NS_coeff2_23_16_len 8 +#define cfoe_NS_coeff2_23_16_lsb 16 +#define p_cfoe_NS_coeff2_24 0xF407 +#define cfoe_NS_coeff2_24_pos 0 +#define cfoe_NS_coeff2_24_len 1 +#define cfoe_NS_coeff2_24_lsb 24 +#define p_cfoe_lf_c1_7_0 0xF408 +#define cfoe_lf_c1_7_0_pos 0 +#define cfoe_lf_c1_7_0_len 8 +#define cfoe_lf_c1_7_0_lsb 0 +#define p_cfoe_lf_c1_9_8 0xF409 +#define cfoe_lf_c1_9_8_pos 0 +#define cfoe_lf_c1_9_8_len 2 +#define cfoe_lf_c1_9_8_lsb 8 +#define p_cfoe_lf_c2_7_0 0xF40A +#define cfoe_lf_c2_7_0_pos 0 +#define cfoe_lf_c2_7_0_len 8 +#define cfoe_lf_c2_7_0_lsb 0 +#define p_cfoe_lf_c2_9_8 0xF40B +#define cfoe_lf_c2_9_8_pos 0 +#define cfoe_lf_c2_9_8_len 2 +#define cfoe_lf_c2_9_8_lsb 8 +#define p_cfoe_ifod_7_0 0xF40C +#define cfoe_ifod_7_0_pos 0 +#define cfoe_ifod_7_0_len 8 +#define cfoe_ifod_7_0_lsb 0 +#define p_cfoe_ifod_10_8 0xF40D +#define cfoe_ifod_10_8_pos 0 +#define cfoe_ifod_10_8_len 3 +#define cfoe_ifod_10_8_lsb 8 +#define p_cfoe_Divg_ctr_th 0xF40E +#define cfoe_Divg_ctr_th_pos 0 +#define cfoe_Divg_ctr_th_len 4 +#define cfoe_Divg_ctr_th_lsb 0 +#define p_cfoe_FOT_divg_th 0xF40F +#define cfoe_FOT_divg_th_pos 0 +#define cfoe_FOT_divg_th_len 8 +#define cfoe_FOT_divg_th_lsb 0 +#define p_cfoe_FOT_cnvg_th 0xF410 +#define cfoe_FOT_cnvg_th_pos 0 +#define cfoe_FOT_cnvg_th_len 8 +#define cfoe_FOT_cnvg_th_lsb 0 +#define p_reg_cfoe_offset_7_0 0xF411 +#define reg_cfoe_offset_7_0_pos 0 +#define reg_cfoe_offset_7_0_len 8 +#define reg_cfoe_offset_7_0_lsb 0 +#define p_reg_cfoe_offset_10_8 0xF412 +#define reg_cfoe_offset_10_8_pos 0 +#define reg_cfoe_offset_10_8_len 3 +#define reg_cfoe_offset_10_8_lsb 8 +#define p_reg_cfoe_ifoe_sign_corr 0xF413 +#define reg_cfoe_ifoe_sign_corr_pos 0 +#define reg_cfoe_ifoe_sign_corr_len 1 +#define reg_cfoe_ifoe_sign_corr_lsb 0 +#define p_cfoe_FOT_pullin_cnt_clr 0xF414 +#define cfoe_FOT_pullin_cnt_clr_pos 0 +#define cfoe_FOT_pullin_cnt_clr_len 1 +#define cfoe_FOT_pullin_cnt_clr_lsb 0 +#define p_cfoe_FOT_spec_inv 0xF415 +#define cfoe_FOT_spec_inv_pos 0 +#define cfoe_FOT_spec_inv_len 1 +#define cfoe_FOT_spec_inv_lsb 0 +#define p_cfoe_FOT_pullin_ctr_th 0xF416 +#define cfoe_FOT_pullin_ctr_th_pos 0 +#define cfoe_FOT_pullin_ctr_th_len 4 +#define cfoe_FOT_pullin_ctr_th_lsb 0 +#define p_cfoe_FOT_sf_ctr_th 0xF417 +#define cfoe_FOT_sf_ctr_th_pos 0 +#define cfoe_FOT_sf_ctr_th_len 4 +#define cfoe_FOT_sf_ctr_th_lsb 0 +#define p_cfoe_FOT_pullin_th 0xF418 +#define cfoe_FOT_pullin_th_pos 0 +#define cfoe_FOT_pullin_th_len 8 +#define cfoe_FOT_pullin_th_lsb 0 +#define p_cfoe_FOT_kalman_cnt 0xF419 +#define cfoe_FOT_kalman_cnt_pos 0 +#define cfoe_FOT_kalman_cnt_len 4 +#define cfoe_FOT_kalman_cnt_lsb 0 +#define p_cfoe_FOT_fsm_info 0xF41A +#define cfoe_FOT_fsm_info_pos 0 +#define cfoe_FOT_fsm_info_len 4 +#define cfoe_FOT_fsm_info_lsb 0 +#define r_cfoe_FOT_pullin_cnt 0xF41B +#define cfoe_FOT_pullin_cnt_pos 0 +#define cfoe_FOT_pullin_cnt_len 4 +#define cfoe_FOT_pullin_cnt_lsb 0 +#define r_cfoe_FOT_sf_cnt 0xF41C +#define cfoe_FOT_sf_cnt_pos 0 +#define cfoe_FOT_sf_cnt_len 4 +#define cfoe_FOT_sf_cnt_lsb 0 +#define r_reg_r_cfoe_ifoe_ifo_metric 0xF41D +#define reg_r_cfoe_ifoe_ifo_metric_pos 0 +#define reg_r_cfoe_ifoe_ifo_metric_len 8 +#define reg_r_cfoe_ifoe_ifo_metric_lsb 0 +#define r_reg_r_cfoe_ifoe_cos2num_7_0 0xF41E +#define reg_r_cfoe_ifoe_cos2num_7_0_pos 0 +#define reg_r_cfoe_ifoe_cos2num_7_0_len 8 +#define reg_r_cfoe_ifoe_cos2num_7_0_lsb 0 +#define r_reg_r_cfoe_ifoe_cos2num_15_8 0xF41F +#define reg_r_cfoe_ifoe_cos2num_15_8_pos 0 +#define reg_r_cfoe_ifoe_cos2num_15_8_len 8 +#define reg_r_cfoe_ifoe_cos2num_15_8_lsb 8 +#define r_reg_r_cfoe_ifoe_cos2num_19_16 0xF420 +#define reg_r_cfoe_ifoe_cos2num_19_16_pos 0 +#define reg_r_cfoe_ifoe_cos2num_19_16_len 4 +#define reg_r_cfoe_ifoe_cos2num_19_16_lsb 16 +#define p_ste_Nu 0xF460 +#define ste_Nu_pos 0 +#define ste_Nu_len 3 +#define ste_Nu_lsb 0 +#define p_ste_GI 0xF461 +#define ste_GI_pos 0 +#define ste_GI_len 3 +#define ste_GI_lsb 0 +#define p_ste_symbol_num 0xF463 +#define ste_symbol_num_pos 0 +#define ste_symbol_num_len 3 +#define ste_symbol_num_lsb 0 +#define p_ste_sample_num 0xF464 +#define ste_sample_num_pos 0 +#define ste_sample_num_len 2 +#define ste_sample_num_lsb 0 +#define p_ste_symbol_num_4K 0xF465 +#define ste_symbol_num_4K_pos 0 +#define ste_symbol_num_4K_len 3 +#define ste_symbol_num_4K_lsb 0 +#define p_ste_FFT_offset_7_0 0xF466 +#define ste_FFT_offset_7_0_pos 0 +#define ste_FFT_offset_7_0_len 8 +#define ste_FFT_offset_7_0_lsb 0 +#define p_ste_FFT_offset_13_8 0xF467 +#define ste_FFT_offset_13_8_pos 0 +#define ste_FFT_offset_13_8_len 6 +#define ste_FFT_offset_13_8_lsb 8 +#define p_ste_sample_num_4K 0xF468 +#define ste_sample_num_4K_pos 0 +#define ste_sample_num_4K_len 2 +#define ste_sample_num_4K_lsb 0 +#define p_ste_adv_start_7_0 0xF469 +#define ste_adv_start_7_0_pos 0 +#define ste_adv_start_7_0_len 8 +#define ste_adv_start_7_0_lsb 0 +#define p_ste_adv_start_10_8 0xF46A +#define ste_adv_start_10_8_pos 0 +#define ste_adv_start_10_8_len 3 +#define ste_adv_start_10_8_lsb 8 +#define p_ste_symbol_num_8K 0xF46B +#define ste_symbol_num_8K_pos 0 +#define ste_symbol_num_8K_len 3 +#define ste_symbol_num_8K_lsb 0 +#define p_ste_sample_num_8K 0xF46C +#define ste_sample_num_8K_pos 0 +#define ste_sample_num_8K_len 2 +#define ste_sample_num_8K_lsb 0 +#define p_ste_adv_stop 0xF46D +#define ste_adv_stop_pos 0 +#define ste_adv_stop_len 8 +#define ste_adv_stop_lsb 0 +#define r_ste_P_value_7_0 0xF46E +#define ste_P_value_7_0_pos 0 +#define ste_P_value_7_0_len 8 +#define ste_P_value_7_0_lsb 0 +#define r_ste_P_value_10_8 0xF46F +#define ste_P_value_10_8_pos 0 +#define ste_P_value_10_8_len 3 +#define ste_P_value_10_8_lsb 8 +#define p_reg_ste_tstmod 0xF470 +#define reg_ste_tstmod_pos 0 +#define reg_ste_tstmod_len 1 +#define reg_ste_tstmod_lsb 0 +#define p_reg_ste_buf_en 0xF471 +#define reg_ste_buf_en_pos 0 +#define reg_ste_buf_en_len 1 +#define reg_ste_buf_en_lsb 0 +#define r_ste_M_value_7_0 0xF472 +#define ste_M_value_7_0_pos 0 +#define ste_M_value_7_0_len 8 +#define ste_M_value_7_0_lsb 0 +#define r_ste_M_value_10_8 0xF473 +#define ste_M_value_10_8_pos 0 +#define ste_M_value_10_8_len 3 +#define ste_M_value_10_8_lsb 8 +#define r_ste_H1 0xF474 +#define ste_H1_pos 0 +#define ste_H1_len 7 +#define ste_H1_lsb 0 +#define r_ste_H2 0xF475 +#define ste_H2_pos 0 +#define ste_H2_len 7 +#define ste_H2_lsb 0 +#define r_ste_H3 0xF476 +#define ste_H3_pos 0 +#define ste_H3_len 7 +#define ste_H3_lsb 0 +#define r_ste_H4 0xF477 +#define ste_H4_pos 0 +#define ste_H4_len 7 +#define ste_H4_lsb 0 +#define r_ste_Corr_value_I_7_0 0xF478 +#define ste_Corr_value_I_7_0_pos 0 +#define ste_Corr_value_I_7_0_len 8 +#define ste_Corr_value_I_7_0_lsb 0 +#define r_ste_Corr_value_I_15_8 0xF479 +#define ste_Corr_value_I_15_8_pos 0 +#define ste_Corr_value_I_15_8_len 8 +#define ste_Corr_value_I_15_8_lsb 8 +#define r_ste_Corr_value_I_23_16 0xF47A +#define ste_Corr_value_I_23_16_pos 0 +#define ste_Corr_value_I_23_16_len 8 +#define ste_Corr_value_I_23_16_lsb 16 +#define r_ste_Corr_value_I_27_24 0xF47B +#define ste_Corr_value_I_27_24_pos 0 +#define ste_Corr_value_I_27_24_len 4 +#define ste_Corr_value_I_27_24_lsb 24 +#define r_ste_Corr_value_Q_7_0 0xF47C +#define ste_Corr_value_Q_7_0_pos 0 +#define ste_Corr_value_Q_7_0_len 8 +#define ste_Corr_value_Q_7_0_lsb 0 +#define r_ste_Corr_value_Q_15_8 0xF47D +#define ste_Corr_value_Q_15_8_pos 0 +#define ste_Corr_value_Q_15_8_len 8 +#define ste_Corr_value_Q_15_8_lsb 8 +#define r_ste_Corr_value_Q_23_16 0xF47E +#define ste_Corr_value_Q_23_16_pos 0 +#define ste_Corr_value_Q_23_16_len 8 +#define ste_Corr_value_Q_23_16_lsb 16 +#define r_ste_Corr_value_Q_27_24 0xF47F +#define ste_Corr_value_Q_27_24_pos 0 +#define ste_Corr_value_Q_27_24_len 4 +#define ste_Corr_value_Q_27_24_lsb 24 +#define r_ste_J_num_7_0 0xF480 +#define ste_J_num_7_0_pos 0 +#define ste_J_num_7_0_len 8 +#define ste_J_num_7_0_lsb 0 +#define r_ste_J_num_15_8 0xF481 +#define ste_J_num_15_8_pos 0 +#define ste_J_num_15_8_len 8 +#define ste_J_num_15_8_lsb 8 +#define r_ste_J_num_23_16 0xF482 +#define ste_J_num_23_16_pos 0 +#define ste_J_num_23_16_len 8 +#define ste_J_num_23_16_lsb 16 +#define r_ste_J_num_31_24 0xF483 +#define ste_J_num_31_24_pos 0 +#define ste_J_num_31_24_len 8 +#define ste_J_num_31_24_lsb 24 +#define r_ste_J_den_7_0 0xF484 +#define ste_J_den_7_0_pos 0 +#define ste_J_den_7_0_len 8 +#define ste_J_den_7_0_lsb 0 +#define r_ste_J_den_15_8 0xF485 +#define ste_J_den_15_8_pos 0 +#define ste_J_den_15_8_len 8 +#define ste_J_den_15_8_lsb 8 +#define r_ste_J_den_18_16 0xF486 +#define ste_J_den_18_16_pos 0 +#define ste_J_den_18_16_len 3 +#define ste_J_den_18_16_lsb 16 +#define r_ste_Beacon_Indicator 0xF488 +#define ste_Beacon_Indicator_pos 0 +#define ste_Beacon_Indicator_len 1 +#define ste_Beacon_Indicator_lsb 0 +#define p_ste_got_sntc_bcn 0xF48B +#define ste_got_sntc_bcn_pos 0 +#define ste_got_sntc_bcn_len 1 +#define ste_got_sntc_bcn_lsb 0 +#define r_tpsd_Frame_Num 0xF4C0 +#define tpsd_Frame_Num_pos 0 +#define tpsd_Frame_Num_len 2 +#define tpsd_Frame_Num_lsb 0 +#define r_tpsd_Constel 0xF4C1 +#define tpsd_Constel_pos 0 +#define tpsd_Constel_len 2 +#define tpsd_Constel_lsb 0 +#define r_tpsd_GI 0xF4C2 +#define tpsd_GI_pos 0 +#define tpsd_GI_len 2 +#define tpsd_GI_lsb 0 +#define r_tpsd_Mode 0xF4C3 +#define tpsd_Mode_pos 0 +#define tpsd_Mode_len 2 +#define tpsd_Mode_lsb 0 +#define r_tpsd_CR_HP 0xF4C4 +#define tpsd_CR_HP_pos 0 +#define tpsd_CR_HP_len 3 +#define tpsd_CR_HP_lsb 0 +#define r_tpsd_CR_LP 0xF4C5 +#define tpsd_CR_LP_pos 0 +#define tpsd_CR_LP_len 3 +#define tpsd_CR_LP_lsb 0 +#define r_tpsd_Hie 0xF4C6 +#define tpsd_Hie_pos 0 +#define tpsd_Hie_len 3 +#define tpsd_Hie_lsb 0 +#define r_tpsd_Res_Bits 0xF4C7 +#define tpsd_Res_Bits_pos 0 +#define tpsd_Res_Bits_len 5 +#define tpsd_Res_Bits_lsb 0 +#define r_tpsd_Res_Bits_0 0xF4C8 +#define tpsd_Res_Bits_0_pos 0 +#define tpsd_Res_Bits_0_len 1 +#define tpsd_Res_Bits_0_lsb 0 +#define r_tpsd_LengthInd 0xF4C9 +#define tpsd_LengthInd_pos 0 +#define tpsd_LengthInd_len 6 +#define tpsd_LengthInd_lsb 0 +#define r_tpsd_Cell_Id_7_0 0xF4CA +#define tpsd_Cell_Id_7_0_pos 0 +#define tpsd_Cell_Id_7_0_len 8 +#define tpsd_Cell_Id_7_0_lsb 0 +#define r_tpsd_Cell_Id_15_8 0xF4CB +#define tpsd_Cell_Id_15_8_pos 0 +#define tpsd_Cell_Id_15_8_len 8 +#define tpsd_Cell_Id_15_8_lsb 0 +#define r_tpsd_use_InDepthInt 0xF4CC +#define tpsd_use_InDepthInt_pos 0 +#define tpsd_use_InDepthInt_len 1 +#define tpsd_use_InDepthInt_lsb 0 +#define r_tpsd_use_TimeSlicing_HP 0xF4CD +#define tpsd_use_TimeSlicing_HP_pos 0 +#define tpsd_use_TimeSlicing_HP_len 1 +#define tpsd_use_TimeSlicing_HP_lsb 0 +#define r_tpsd_use_mpe_fec_HP 0xF4CE +#define tpsd_use_mpe_fec_HP_pos 0 +#define tpsd_use_mpe_fec_HP_len 1 +#define tpsd_use_mpe_fec_HP_lsb 0 +#define r_tpsd_use_TimeSlicing_LP 0xF4CF +#define tpsd_use_TimeSlicing_LP_pos 0 +#define tpsd_use_TimeSlicing_LP_len 1 +#define tpsd_use_TimeSlicing_LP_lsb 0 +#define r_tpsd_use_mpe_fec_LP 0xF4D0 +#define tpsd_use_mpe_fec_LP_pos 0 +#define tpsd_use_mpe_fec_LP_len 1 +#define tpsd_use_mpe_fec_LP_lsb 0 +#define r_tpsd_leng23_ind_return 0xF4D1 +#define tpsd_leng23_ind_return_pos 0 +#define tpsd_leng23_ind_return_len 1 +#define tpsd_leng23_ind_return_lsb 0 +#define p_reg_fft_re_exp 0xF500 +#define reg_fft_re_exp_pos 0 +#define reg_fft_re_exp_len 4 +#define reg_fft_re_exp_lsb 0 +#define p_reg_fft_re_mts 0xF501 +#define reg_fft_re_mts_pos 0 +#define reg_fft_re_mts_len 8 +#define reg_fft_re_mts_lsb 0 +#define p_reg_fft_im_exp 0xF502 +#define reg_fft_im_exp_pos 0 +#define reg_fft_im_exp_len 4 +#define reg_fft_im_exp_lsb 0 +#define p_reg_fft_im_mts 0xF503 +#define reg_fft_im_mts_pos 0 +#define reg_fft_im_mts_len 8 +#define reg_fft_im_mts_lsb 0 +#define p_reg_fft_conjugate 0xF504 +#define reg_fft_conjugate_pos 0 +#define reg_fft_conjugate_len 1 +#define reg_fft_conjugate_lsb 0 +#define p_reg_fft_power_en 0xF505 +#define reg_fft_power_en_pos 0 +#define reg_fft_power_en_len 1 +#define reg_fft_power_en_lsb 0 +#define p_reg_fft_power_factor 0xF506 +#define reg_fft_power_factor_pos 0 +#define reg_fft_power_factor_len 6 +#define reg_fft_power_factor_lsb 0 +#define p_reg_fft_power_in 0xF507 +#define reg_fft_power_in_pos 0 +#define reg_fft_power_in_len 8 +#define reg_fft_power_in_lsb 0 +#define p_reg_fft_mask_from0_7_0 0xF508 +#define reg_fft_mask_from0_7_0_pos 0 +#define reg_fft_mask_from0_7_0_len 8 +#define reg_fft_mask_from0_7_0_lsb 0 +#define p_reg_fft_mask_from0_12_8 0xF509 +#define reg_fft_mask_from0_12_8_pos 0 +#define reg_fft_mask_from0_12_8_len 5 +#define reg_fft_mask_from0_12_8_lsb 8 +#define p_reg_fft_mask_to0_7_0 0xF50A +#define reg_fft_mask_to0_7_0_pos 0 +#define reg_fft_mask_to0_7_0_len 8 +#define reg_fft_mask_to0_7_0_lsb 0 +#define p_reg_fft_mask_to0_12_8 0xF50B +#define reg_fft_mask_to0_12_8_pos 0 +#define reg_fft_mask_to0_12_8_len 5 +#define reg_fft_mask_to0_12_8_lsb 8 +#define p_reg_fft_mask_from1_7_0 0xF50C +#define reg_fft_mask_from1_7_0_pos 0 +#define reg_fft_mask_from1_7_0_len 8 +#define reg_fft_mask_from1_7_0_lsb 0 +#define p_reg_fft_mask_from1_12_8 0xF50D +#define reg_fft_mask_from1_12_8_pos 0 +#define reg_fft_mask_from1_12_8_len 5 +#define reg_fft_mask_from1_12_8_lsb 8 +#define p_reg_fft_mask_to1_7_0 0xF50E +#define reg_fft_mask_to1_7_0_pos 0 +#define reg_fft_mask_to1_7_0_len 8 +#define reg_fft_mask_to1_7_0_lsb 0 +#define p_reg_fft_mask_to1_12_8 0xF50F +#define reg_fft_mask_to1_12_8_pos 0 +#define reg_fft_mask_to1_12_8_len 5 +#define reg_fft_mask_to1_12_8_lsb 8 +#define p_reg_fft_mask_from2_7_0 0xF510 +#define reg_fft_mask_from2_7_0_pos 0 +#define reg_fft_mask_from2_7_0_len 8 +#define reg_fft_mask_from2_7_0_lsb 0 +#define p_reg_fft_mask_from2_12_8 0xF511 +#define reg_fft_mask_from2_12_8_pos 0 +#define reg_fft_mask_from2_12_8_len 5 +#define reg_fft_mask_from2_12_8_lsb 8 +#define p_reg_fft_mask_to2_7_0 0xF512 +#define reg_fft_mask_to2_7_0_pos 0 +#define reg_fft_mask_to2_7_0_len 8 +#define reg_fft_mask_to2_7_0_lsb 0 +#define p_reg_fft_mask_to2_12_8 0xF513 +#define reg_fft_mask_to2_12_8_pos 0 +#define reg_fft_mask_to2_12_8_len 5 +#define reg_fft_mask_to2_12_8_lsb 8 +#define p_reg_fft_mask_from3_7_0 0xF514 +#define reg_fft_mask_from3_7_0_pos 0 +#define reg_fft_mask_from3_7_0_len 8 +#define reg_fft_mask_from3_7_0_lsb 0 +#define p_reg_fft_mask_from3_12_8 0xF515 +#define reg_fft_mask_from3_12_8_pos 0 +#define reg_fft_mask_from3_12_8_len 5 +#define reg_fft_mask_from3_12_8_lsb 8 +#define p_reg_fft_mask_to3_7_0 0xF516 +#define reg_fft_mask_to3_7_0_pos 0 +#define reg_fft_mask_to3_7_0_len 8 +#define reg_fft_mask_to3_7_0_lsb 0 +#define p_reg_fft_mask_to3_12_8 0xF517 +#define reg_fft_mask_to3_12_8_pos 0 +#define reg_fft_mask_to3_12_8_len 5 +#define reg_fft_mask_to3_12_8_lsb 8 +#define r_fd_sntc_frame_num 0xF518 +#define fd_sntc_frame_num_pos 0 +#define fd_sntc_frame_num_len 2 +#define fd_sntc_frame_num_lsb 0 +#define r_fd_sntc_symbol_count 0xF519 +#define fd_sntc_symbol_count_pos 0 +#define fd_sntc_symbol_count_len 7 +#define fd_sntc_symbol_count_lsb 0 +#define p_reg_sntc_cnt_lo 0xF51A +#define reg_sntc_cnt_lo_pos 0 +#define reg_sntc_cnt_lo_len 8 +#define reg_sntc_cnt_lo_lsb 0 +#define p_reg_sntc_cnt_hi 0xF51B +#define reg_sntc_cnt_hi_pos 0 +#define reg_sntc_cnt_hi_len 7 +#define reg_sntc_cnt_hi_lsb 0 +#define p_reg_sntc_fft_in 0xF51C +#define reg_sntc_fft_in_pos 0 +#define reg_sntc_fft_in_len 1 +#define reg_sntc_fft_in_lsb 0 +#define r_fd_sntc_en 0xF51D +#define fd_sntc_en_pos 0 +#define fd_sntc_en_len 1 +#define fd_sntc_en_lsb 0 +#define p_reg_sntc_x2 0xF51E +#define reg_sntc_x2_pos 0 +#define reg_sntc_x2_len 1 +#define reg_sntc_x2_lsb 0 +#define p_reg_cge_en_7_0 0xF51F +#define reg_cge_en_7_0_pos 0 +#define reg_cge_en_7_0_len 8 +#define reg_cge_en_7_0_lsb 0 +#define p_reg_cge_en_15_8 0xF520 +#define reg_cge_en_15_8_pos 0 +#define reg_cge_en_15_8_len 8 +#define reg_cge_en_15_8_lsb 8 +#define p_reg_cge_en_23_16 0xF521 +#define reg_cge_en_23_16_pos 0 +#define reg_cge_en_23_16_len 8 +#define reg_cge_en_23_16_lsb 16 +#define p_reg_cge_en_31_24 0xF522 +#define reg_cge_en_31_24_pos 0 +#define reg_cge_en_31_24_len 8 +#define reg_cge_en_31_24_lsb 24 +#define p_reg_cge_en_39_32 0xF523 +#define reg_cge_en_39_32_pos 0 +#define reg_cge_en_39_32_len 8 +#define reg_cge_en_39_32_lsb 32 +#define p_reg_cge_en_43_40 0xF524 +#define reg_cge_en_43_40_pos 0 +#define reg_cge_en_43_40_len 4 +#define reg_cge_en_43_40_lsb 40 +#define p_reg_fft_sat_en 0xF525 +#define reg_fft_sat_en_pos 0 +#define reg_fft_sat_en_len 1 +#define reg_fft_sat_en_lsb 0 +#define p_reg_fft_sat_count_clr 0xF526 +#define reg_fft_sat_count_clr_pos 0 +#define reg_fft_sat_count_clr_len 1 +#define reg_fft_sat_count_clr_lsb 0 +#define p_reg_fft_rescale_round 0xF527 +#define reg_fft_rescale_round_pos 0 +#define reg_fft_rescale_round_len 1 +#define reg_fft_rescale_round_lsb 0 +#define r_reg_fft_sat_count_12_7_0 0xF528 +#define reg_fft_sat_count_12_7_0_pos 0 +#define reg_fft_sat_count_12_7_0_len 8 +#define reg_fft_sat_count_12_7_0_lsb 0 +#define r_reg_fft_sat_count_12_15_8 0xF529 +#define reg_fft_sat_count_12_15_8_pos 0 +#define reg_fft_sat_count_12_15_8_len 8 +#define reg_fft_sat_count_12_15_8_lsb 8 +#define r_reg_fft_sat_count_10_7_0 0xF52A +#define reg_fft_sat_count_10_7_0_pos 0 +#define reg_fft_sat_count_10_7_0_len 8 +#define reg_fft_sat_count_10_7_0_lsb 0 +#define r_reg_fft_sat_count_10_15_8 0xF52B +#define reg_fft_sat_count_10_15_8_pos 0 +#define reg_fft_sat_count_10_15_8_len 8 +#define reg_fft_sat_count_10_15_8_lsb 8 +#define p_reg_fft_capture_idx_7_0 0xF52C +#define reg_fft_capture_idx_7_0_pos 0 +#define reg_fft_capture_idx_7_0_len 8 +#define reg_fft_capture_idx_7_0_lsb 0 +#define p_reg_fft_capture_idx_12_8 0xF52D +#define reg_fft_capture_idx_12_8_pos 0 +#define reg_fft_capture_idx_12_8_len 5 +#define reg_fft_capture_idx_12_8_lsb 8 +#define p_reg_fft_capture 0xF52E +#define reg_fft_capture_pos 0 +#define reg_fft_capture_len 1 +#define reg_fft_capture_lsb 0 +#define p_reg_gp_trigger_fd 0xF52F +#define reg_gp_trigger_fd_pos 0 +#define reg_gp_trigger_fd_len 1 +#define reg_gp_trigger_fd_lsb 0 +#define p_reg_trigger_sel_fd 0xF530 +#define reg_trigger_sel_fd_pos 0 +#define reg_trigger_sel_fd_len 2 +#define reg_trigger_sel_fd_lsb 0 +#define p_reg_trigger_module_sel_fd 0xF531 +#define reg_trigger_module_sel_fd_pos 0 +#define reg_trigger_module_sel_fd_len 6 +#define reg_trigger_module_sel_fd_lsb 0 +#define p_reg_trigger_set_sel_fd 0xF532 +#define reg_trigger_set_sel_fd_pos 0 +#define reg_trigger_set_sel_fd_len 6 +#define reg_trigger_set_sel_fd_lsb 0 +#define r_reg_fft_idx_pre_max_7_0 0xF533 +#define reg_fft_idx_pre_max_7_0_pos 0 +#define reg_fft_idx_pre_max_7_0_len 8 +#define reg_fft_idx_pre_max_7_0_lsb 0 +#define r_reg_fft_idx_pre_max_12_8 0xF534 +#define reg_fft_idx_pre_max_12_8_pos 0 +#define reg_fft_idx_pre_max_12_8_len 5 +#define reg_fft_idx_pre_max_12_8_lsb 8 +#define r_reg_fft_crc 0xF535 +#define reg_fft_crc_pos 0 +#define reg_fft_crc_len 8 +#define reg_fft_crc_lsb 0 +#define p_fd_fft_shift_max 0xF536 +#define fd_fft_shift_max_pos 0 +#define fd_fft_shift_max_len 4 +#define fd_fft_shift_max_lsb 0 +#define p_fd_fft_frame_num 0xF537 +#define fd_fft_frame_num_pos 0 +#define fd_fft_frame_num_len 2 +#define fd_fft_frame_num_lsb 0 +#define p_fd_fft_symbol_count 0xF538 +#define fd_fft_symbol_count_pos 0 +#define fd_fft_symbol_count_len 7 +#define fd_fft_symbol_count_lsb 0 +#define r_reg_fft_idx_max_7_0 0xF539 +#define reg_fft_idx_max_7_0_pos 0 +#define reg_fft_idx_max_7_0_len 8 +#define reg_fft_idx_max_7_0_lsb 0 +#define r_reg_fft_idx_max_12_8 0xF53A +#define reg_fft_idx_max_12_8_pos 0 +#define reg_fft_idx_max_12_8_len 5 +#define reg_fft_idx_max_12_8_lsb 8 +#define p_reg_fft_rotate_en 0xF53B +#define reg_fft_rotate_en_pos 0 +#define reg_fft_rotate_en_len 1 +#define reg_fft_rotate_en_lsb 0 +#define p_reg_fft_rotate_base_7_0 0xF53C +#define reg_fft_rotate_base_7_0_pos 0 +#define reg_fft_rotate_base_7_0_len 8 +#define reg_fft_rotate_base_7_0_lsb 0 +#define p_reg_fft_rotate_base_12_8 0xF53D +#define reg_fft_rotate_base_12_8_pos 0 +#define reg_fft_rotate_base_12_8_len 5 +#define reg_fft_rotate_base_12_8_lsb 8 +#define r_fd_fpcc_cp_corr_signn 0xF53E +#define fd_fpcc_cp_corr_signn_pos 0 +#define fd_fpcc_cp_corr_signn_len 8 +#define fd_fpcc_cp_corr_signn_lsb 0 +#define p_reg_feq_s1 0xF53F +#define reg_feq_s1_pos 0 +#define reg_feq_s1_len 5 +#define reg_feq_s1_lsb 0 +#define p_reg_feq_sat_ind 0xF540 +#define reg_feq_sat_ind_pos 0 +#define reg_feq_sat_ind_len 3 +#define reg_feq_sat_ind_lsb 0 +#define p_reg_p_csi_cal_en 0xF541 +#define reg_p_csi_cal_en_pos 0 +#define reg_p_csi_cal_en_len 1 +#define reg_p_csi_cal_en_lsb 0 +#define p_reg_p_csi_ar_mode 0xF542 +#define reg_p_csi_ar_mode_pos 0 +#define reg_p_csi_ar_mode_len 2 +#define reg_p_csi_ar_mode_lsb 0 +#define p_reg_p_csi_accu_sym_num 0xF543 +#define reg_p_csi_accu_sym_num_pos 0 +#define reg_p_csi_accu_sym_num_len 8 +#define reg_p_csi_accu_sym_num_lsb 0 +#define p_reg_p_csi_eh2_shift_thr 0xF544 +#define reg_p_csi_eh2_shift_thr_pos 0 +#define reg_p_csi_eh2_shift_thr_len 4 +#define reg_p_csi_eh2_shift_thr_lsb 0 +#define p_reg_p_feq_protect_eh2_shift_thr 0xF545 +#define reg_p_feq_protect_eh2_shift_thr_pos 0 +#define reg_p_feq_protect_eh2_shift_thr_len 4 +#define reg_p_feq_protect_eh2_shift_thr_lsb 0 +#define p_reg_p_csi_error_accu_s1 0xF546 +#define reg_p_csi_error_accu_s1_pos 0 +#define reg_p_csi_error_accu_s1_len 6 +#define reg_p_csi_error_accu_s1_lsb 0 +#define p_reg_p_csi_shift2 0xF547 +#define reg_p_csi_shift2_pos 0 +#define reg_p_csi_shift2_len 4 +#define reg_p_csi_shift2_lsb 0 +#define p_reg_p_csi_mul2 0xF548 +#define reg_p_csi_mul2_pos 0 +#define reg_p_csi_mul2_len 8 +#define reg_p_csi_mul2_lsb 0 +#define p_reg_p_csi_level2_7_0 0xF549 +#define reg_p_csi_level2_7_0_pos 0 +#define reg_p_csi_level2_7_0_len 8 +#define reg_p_csi_level2_7_0_lsb 0 +#define p_reg_p_csi_level2_8 0xF54A +#define reg_p_csi_level2_8_pos 0 +#define reg_p_csi_level2_8_len 1 +#define reg_p_csi_level2_8_lsb 8 +#define p_reg_p_feq_protect_ratio 0xF54B +#define reg_p_feq_protect_ratio_pos 0 +#define reg_p_feq_protect_ratio_len 8 +#define reg_p_feq_protect_ratio_lsb 0 +#define r_reg_csi_rdy 0xF54C +#define reg_csi_rdy_pos 0 +#define reg_csi_rdy_len 1 +#define reg_csi_rdy_lsb 0 +#define p_reg_p_feq_h2protect_en 0xF54D +#define reg_p_feq_h2protect_en_pos 0 +#define reg_p_feq_h2protect_en_len 1 +#define reg_p_feq_h2protect_en_lsb 0 +#define r_reg_tpsd_lock_f0 0xF54E +#define reg_tpsd_lock_f0_pos 0 +#define reg_tpsd_lock_f0_len 1 +#define reg_tpsd_lock_f0_lsb 0 +#define r_reg_tpsd_lock_f1 0xF54F +#define reg_tpsd_lock_f1_pos 0 +#define reg_tpsd_lock_f1_len 1 +#define reg_tpsd_lock_f1_lsb 0 +#define p_reg_p_csi_sp_idx_7_0 0xF550 +#define reg_p_csi_sp_idx_7_0_pos 0 +#define reg_p_csi_sp_idx_7_0_len 8 +#define reg_p_csi_sp_idx_7_0_lsb 0 +#define p_reg_p_csi_sp_idx_11_8 0xF551 +#define reg_p_csi_sp_idx_11_8_pos 0 +#define reg_p_csi_sp_idx_11_8_len 4 +#define reg_p_csi_sp_idx_11_8_lsb 8 +#define p_fd_fpcc_cp_corr_tone_th 0xF552 +#define fd_fpcc_cp_corr_tone_th_pos 0 +#define fd_fpcc_cp_corr_tone_th_len 6 +#define fd_fpcc_cp_corr_tone_th_lsb 0 +#define p_fd_fpcc_cp_corr_symbol_log_th 0xF553 +#define fd_fpcc_cp_corr_symbol_log_th_pos 0 +#define fd_fpcc_cp_corr_symbol_log_th_len 4 +#define fd_fpcc_cp_corr_symbol_log_th_lsb 0 +#define p_fd_fpcc_cp_corr_int 0xF554 +#define fd_fpcc_cp_corr_int_pos 0 +#define fd_fpcc_cp_corr_int_len 1 +#define fd_fpcc_cp_corr_int_lsb 0 +#define p_reg_fpcc_cp_memidx 0xF555 +#define reg_fpcc_cp_memidx_pos 0 +#define reg_fpcc_cp_memidx_len 8 +#define reg_fpcc_cp_memidx_lsb 0 +#define p_reg_fpcc_cpmask_en 0xF556 +#define reg_fpcc_cpmask_en_pos 0 +#define reg_fpcc_cpmask_en_len 1 +#define reg_fpcc_cpmask_en_lsb 0 +#define p_reg_fpcc_cp_grpidx 0xF557 +#define reg_fpcc_cp_grpidx_pos 0 +#define reg_fpcc_cp_grpidx_len 5 +#define reg_fpcc_cp_grpidx_lsb 0 +#define r_reg_fpcc_cp_sts 0xF558 +#define reg_fpcc_cp_sts_pos 0 +#define reg_fpcc_cp_sts_len 1 +#define reg_fpcc_cp_sts_lsb 0 +#define p_reg_sfoe_ns_7_0 0xF559 +#define reg_sfoe_ns_7_0_pos 0 +#define reg_sfoe_ns_7_0_len 8 +#define reg_sfoe_ns_7_0_lsb 0 +#define p_reg_sfoe_ns_14_8 0xF55A +#define reg_sfoe_ns_14_8_pos 0 +#define reg_sfoe_ns_14_8_len 7 +#define reg_sfoe_ns_14_8_lsb 8 +#define p_reg_sfoe_c1_7_0 0xF55B +#define reg_sfoe_c1_7_0_pos 0 +#define reg_sfoe_c1_7_0_len 8 +#define reg_sfoe_c1_7_0_lsb 0 +#define p_reg_sfoe_c1_9_8 0xF55C +#define reg_sfoe_c1_9_8_pos 0 +#define reg_sfoe_c1_9_8_len 2 +#define reg_sfoe_c1_9_8_lsb 8 +#define p_reg_sfoe_c2_7_0 0xF55D +#define reg_sfoe_c2_7_0_pos 0 +#define reg_sfoe_c2_7_0_len 8 +#define reg_sfoe_c2_7_0_lsb 0 +#define p_reg_sfoe_c2_9_8 0xF55E +#define reg_sfoe_c2_9_8_pos 0 +#define reg_sfoe_c2_9_8_len 2 +#define reg_sfoe_c2_9_8_lsb 8 +#define p_reg_sfoe_lm_counter_th 0xF55F +#define reg_sfoe_lm_counter_th_pos 0 +#define reg_sfoe_lm_counter_th_len 4 +#define reg_sfoe_lm_counter_th_lsb 0 +#define p_reg_sfoe_spec_inv 0xF560 +#define reg_sfoe_spec_inv_pos 0 +#define reg_sfoe_spec_inv_len 1 +#define reg_sfoe_spec_inv_lsb 0 +#define p_reg_sfoe_convg_th 0xF561 +#define reg_sfoe_convg_th_pos 0 +#define reg_sfoe_convg_th_len 8 +#define reg_sfoe_convg_th_lsb 0 +#define p_reg_sfoe_divg_th 0xF562 +#define reg_sfoe_divg_th_pos 0 +#define reg_sfoe_divg_th_len 8 +#define reg_sfoe_divg_th_lsb 0 +#define p_reg_sfoe_pullin_ctr_th 0xF563 +#define reg_sfoe_pullin_ctr_th_pos 0 +#define reg_sfoe_pullin_ctr_th_len 4 +#define reg_sfoe_pullin_ctr_th_lsb 0 +#define p_reg_sfoe_sf_ctr_th 0xF564 +#define reg_sfoe_sf_ctr_th_pos 0 +#define reg_sfoe_sf_ctr_th_len 4 +#define reg_sfoe_sf_ctr_th_lsb 0 +#define p_reg_sfoe_pullin_th 0xF565 +#define reg_sfoe_pullin_th_pos 0 +#define reg_sfoe_pullin_th_len 8 +#define reg_sfoe_pullin_th_lsb 0 +#define p_reg_sfoe_kalman_cnt 0xF566 +#define reg_sfoe_kalman_cnt_pos 0 +#define reg_sfoe_kalman_cnt_len 4 +#define reg_sfoe_kalman_cnt_lsb 0 +#define p_reg_sfoe_fsm_info 0xF567 +#define reg_sfoe_fsm_info_pos 0 +#define reg_sfoe_fsm_info_len 4 +#define reg_sfoe_fsm_info_lsb 0 +#define r_reg_sfoe_pullin_cnt 0xF568 +#define reg_sfoe_pullin_cnt_pos 0 +#define reg_sfoe_pullin_cnt_len 4 +#define reg_sfoe_pullin_cnt_lsb 0 +#define r_reg_sfoe_sf_cnt 0xF569 +#define reg_sfoe_sf_cnt_pos 0 +#define reg_sfoe_sf_cnt_len 4 +#define reg_sfoe_sf_cnt_lsb 0 +#define p_reg_fste_phase_ini_7_0 0xF56A +#define reg_fste_phase_ini_7_0_pos 0 +#define reg_fste_phase_ini_7_0_len 8 +#define reg_fste_phase_ini_7_0_lsb 0 +#define p_reg_fste_phase_ini_11_8 0xF56B +#define reg_fste_phase_ini_11_8_pos 0 +#define reg_fste_phase_ini_11_8_len 4 +#define reg_fste_phase_ini_11_8_lsb 8 +#define p_reg_fste_phase_inc_7_0 0xF56C +#define reg_fste_phase_inc_7_0_pos 0 +#define reg_fste_phase_inc_7_0_len 8 +#define reg_fste_phase_inc_7_0_lsb 0 +#define p_reg_fste_phase_inc_11_8 0xF56D +#define reg_fste_phase_inc_11_8_pos 0 +#define reg_fste_phase_inc_11_8_len 4 +#define reg_fste_phase_inc_11_8_lsb 8 +#define p_reg_fste_acum_cost_cnt_max 0xF56E +#define reg_fste_acum_cost_cnt_max_pos 0 +#define reg_fste_acum_cost_cnt_max_len 4 +#define reg_fste_acum_cost_cnt_max_lsb 0 +#define p_reg_fste_step_size_std 0xF56F +#define reg_fste_step_size_std_pos 0 +#define reg_fste_step_size_std_len 4 +#define reg_fste_step_size_std_lsb 0 +#define p_reg_fste_step_size_max 0xF570 +#define reg_fste_step_size_max_pos 0 +#define reg_fste_step_size_max_len 4 +#define reg_fste_step_size_max_lsb 0 +#define p_reg_fste_rpd_dir_cnt_max 0xF571 +#define reg_fste_rpd_dir_cnt_max_pos 0 +#define reg_fste_rpd_dir_cnt_max_len 4 +#define reg_fste_rpd_dir_cnt_max_lsb 0 +#define p_reg_fste_frac_cost_cnt_max_7_0 0xF572 +#define reg_fste_frac_cost_cnt_max_7_0_pos 0 +#define reg_fste_frac_cost_cnt_max_7_0_len 8 +#define reg_fste_frac_cost_cnt_max_7_0_lsb 0 +#define p_reg_fste_frac_cost_cnt_max_9_8 0xF573 +#define reg_fste_frac_cost_cnt_max_9_8_pos 0 +#define reg_fste_frac_cost_cnt_max_9_8_len 2 +#define reg_fste_frac_cost_cnt_max_9_8_lsb 8 +#define p_reg_fste_isLongWeakTail 0xF574 +#define reg_fste_isLongWeakTail_pos 0 +#define reg_fste_isLongWeakTail_len 1 +#define reg_fste_isLongWeakTail_lsb 0 +#define p_reg_fste_isLongWeakHead 0xF575 +#define reg_fste_isLongWeakHead_pos 0 +#define reg_fste_isLongWeakHead_len 1 +#define reg_fste_isLongWeakHead_lsb 0 +#define p_reg_fste_w0_7_0 0xF576 +#define reg_fste_w0_7_0_pos 0 +#define reg_fste_w0_7_0_len 8 +#define reg_fste_w0_7_0_lsb 0 +#define p_reg_fste_w0_9_8 0xF577 +#define reg_fste_w0_9_8_pos 0 +#define reg_fste_w0_9_8_len 2 +#define reg_fste_w0_9_8_lsb 8 +#define p_reg_fste_w1_7_0 0xF578 +#define reg_fste_w1_7_0_pos 0 +#define reg_fste_w1_7_0_len 8 +#define reg_fste_w1_7_0_lsb 0 +#define p_reg_fste_w1_9_8 0xF579 +#define reg_fste_w1_9_8_pos 0 +#define reg_fste_w1_9_8_len 2 +#define reg_fste_w1_9_8_lsb 8 +#define p_reg_fste_w2_7_0 0xF57A +#define reg_fste_w2_7_0_pos 0 +#define reg_fste_w2_7_0_len 8 +#define reg_fste_w2_7_0_lsb 0 +#define p_reg_fste_w2_9_8 0xF57B +#define reg_fste_w2_9_8_pos 0 +#define reg_fste_w2_9_8_len 2 +#define reg_fste_w2_9_8_lsb 8 +#define p_reg_fste_w3_7_0 0xF57C +#define reg_fste_w3_7_0_pos 0 +#define reg_fste_w3_7_0_len 8 +#define reg_fste_w3_7_0_lsb 0 +#define p_reg_fste_w3_9_8 0xF57D +#define reg_fste_w3_9_8_pos 0 +#define reg_fste_w3_9_8_len 2 +#define reg_fste_w3_9_8_lsb 8 +#define p_reg_fste_w4_7_0 0xF57E +#define reg_fste_w4_7_0_pos 0 +#define reg_fste_w4_7_0_len 8 +#define reg_fste_w4_7_0_lsb 0 +#define p_reg_fste_w4_9_8 0xF57F +#define reg_fste_w4_9_8_pos 0 +#define reg_fste_w4_9_8_len 2 +#define reg_fste_w4_9_8_lsb 8 +#define p_reg_fste_w5_7_0 0xF580 +#define reg_fste_w5_7_0_pos 0 +#define reg_fste_w5_7_0_len 8 +#define reg_fste_w5_7_0_lsb 0 +#define p_reg_fste_w5_9_8 0xF581 +#define reg_fste_w5_9_8_pos 0 +#define reg_fste_w5_9_8_len 2 +#define reg_fste_w5_9_8_lsb 8 +#define p_reg_fste_w6_7_0 0xF582 +#define reg_fste_w6_7_0_pos 0 +#define reg_fste_w6_7_0_len 8 +#define reg_fste_w6_7_0_lsb 0 +#define p_reg_fste_w6_9_8 0xF583 +#define reg_fste_w6_9_8_pos 0 +#define reg_fste_w6_9_8_len 2 +#define reg_fste_w6_9_8_lsb 8 +#define p_reg_fste_w7_7_0 0xF584 +#define reg_fste_w7_7_0_pos 0 +#define reg_fste_w7_7_0_len 8 +#define reg_fste_w7_7_0_lsb 0 +#define p_reg_fste_w7_9_8 0xF585 +#define reg_fste_w7_9_8_pos 0 +#define reg_fste_w7_9_8_len 2 +#define reg_fste_w7_9_8_lsb 8 +#define p_reg_fste_w8_7_0 0xF586 +#define reg_fste_w8_7_0_pos 0 +#define reg_fste_w8_7_0_len 8 +#define reg_fste_w8_7_0_lsb 0 +#define p_reg_fste_w8_9_8 0xF587 +#define reg_fste_w8_9_8_pos 0 +#define reg_fste_w8_9_8_len 2 +#define reg_fste_w8_9_8_lsb 8 +#define p_reg_fste_w9_7_0 0xF588 +#define reg_fste_w9_7_0_pos 0 +#define reg_fste_w9_7_0_len 8 +#define reg_fste_w9_7_0_lsb 0 +#define p_reg_fste_w9_9_8 0xF589 +#define reg_fste_w9_9_8_pos 0 +#define reg_fste_w9_9_8_len 2 +#define reg_fste_w9_9_8_lsb 8 +#define p_reg_fste_wa_7_0 0xF58A +#define reg_fste_wa_7_0_pos 0 +#define reg_fste_wa_7_0_len 8 +#define reg_fste_wa_7_0_lsb 0 +#define p_reg_fste_wa_9_8 0xF58B +#define reg_fste_wa_9_8_pos 0 +#define reg_fste_wa_9_8_len 2 +#define reg_fste_wa_9_8_lsb 8 +#define p_reg_fste_wb_7_0 0xF58C +#define reg_fste_wb_7_0_pos 0 +#define reg_fste_wb_7_0_len 8 +#define reg_fste_wb_7_0_lsb 0 +#define p_reg_fste_wb_9_8 0xF58D +#define reg_fste_wb_9_8_pos 0 +#define reg_fste_wb_9_8_len 2 +#define reg_fste_wb_9_8_lsb 8 +#define p_reg_fste_wc_7_0 0xF58E +#define reg_fste_wc_7_0_pos 0 +#define reg_fste_wc_7_0_len 8 +#define reg_fste_wc_7_0_lsb 0 +#define p_reg_fste_wc_9_8 0xF58F +#define reg_fste_wc_9_8_pos 0 +#define reg_fste_wc_9_8_len 2 +#define reg_fste_wc_9_8_lsb 8 +#define p_reg_fste_wd_7_0 0xF590 +#define reg_fste_wd_7_0_pos 0 +#define reg_fste_wd_7_0_len 8 +#define reg_fste_wd_7_0_lsb 0 +#define p_reg_fste_wd_9_8 0xF591 +#define reg_fste_wd_9_8_pos 0 +#define reg_fste_wd_9_8_len 2 +#define reg_fste_wd_9_8_lsb 8 +#define p_reg_fste_we_7_0 0xF592 +#define reg_fste_we_7_0_pos 0 +#define reg_fste_we_7_0_len 8 +#define reg_fste_we_7_0_lsb 0 +#define p_reg_fste_we_9_8 0xF593 +#define reg_fste_we_9_8_pos 0 +#define reg_fste_we_9_8_len 2 +#define reg_fste_we_9_8_lsb 8 +#define p_reg_fste_wf_7_0 0xF594 +#define reg_fste_wf_7_0_pos 0 +#define reg_fste_wf_7_0_len 8 +#define reg_fste_wf_7_0_lsb 0 +#define p_reg_fste_wf_9_8 0xF595 +#define reg_fste_wf_9_8_pos 0 +#define reg_fste_wf_9_8_len 2 +#define reg_fste_wf_9_8_lsb 8 +#define p_reg_fste_wg_7_0 0xF596 +#define reg_fste_wg_7_0_pos 0 +#define reg_fste_wg_7_0_len 8 +#define reg_fste_wg_7_0_lsb 0 +#define p_reg_fste_wg_9_8 0xF597 +#define reg_fste_wg_9_8_pos 0 +#define reg_fste_wg_9_8_len 2 +#define reg_fste_wg_9_8_lsb 8 +#define p_reg_fste_wh_7_0 0xF598 +#define reg_fste_wh_7_0_pos 0 +#define reg_fste_wh_7_0_len 8 +#define reg_fste_wh_7_0_lsb 0 +#define p_reg_fste_wh_9_8 0xF599 +#define reg_fste_wh_9_8_pos 0 +#define reg_fste_wh_9_8_len 2 +#define reg_fste_wh_9_8_lsb 8 +#define r_fd_fste_i_adj_org 0xF59A +#define fd_fste_i_adj_org_pos 0 +#define fd_fste_i_adj_org_len 5 +#define fd_fste_i_adj_org_lsb 0 +#define r_fd_fste_f_adj_7_0 0xF59B +#define fd_fste_f_adj_7_0_pos 0 +#define fd_fste_f_adj_7_0_len 8 +#define fd_fste_f_adj_7_0_lsb 0 +#define r_fd_fste_f_adj_15_8 0xF59C +#define fd_fste_f_adj_15_8_pos 0 +#define fd_fste_f_adj_15_8_len 8 +#define fd_fste_f_adj_15_8_lsb 8 +#define r_fd_fste_f_adj_19_16 0xF59D +#define fd_fste_f_adj_19_16_pos 0 +#define fd_fste_f_adj_19_16_len 4 +#define fd_fste_f_adj_19_16_lsb 16 +#define p_reg_fste_ehw_7_0 0xF59E +#define reg_fste_ehw_7_0_pos 0 +#define reg_fste_ehw_7_0_len 8 +#define reg_fste_ehw_7_0_lsb 0 +#define p_reg_fste_ehw_12_8 0xF59F +#define reg_fste_ehw_12_8_pos 0 +#define reg_fste_ehw_12_8_len 5 +#define reg_fste_ehw_12_8_lsb 8 +#define p_reg_fste_i_adj_vld 0xF5A0 +#define reg_fste_i_adj_vld_pos 0 +#define reg_fste_i_adj_vld_len 1 +#define reg_fste_i_adj_vld_lsb 0 +#define p_reg_fste_ceTimesPhasor_real 0xF5A1 +#define reg_fste_ceTimesPhasor_real_pos 0 +#define reg_fste_ceTimesPhasor_real_len 1 +#define reg_fste_ceTimesPhasor_real_lsb 0 +#define p_reg_fste_ceTimesPhasor_imag 0xF5A2 +#define reg_fste_ceTimesPhasor_imag_pos 0 +#define reg_fste_ceTimesPhasor_imag_len 1 +#define reg_fste_ceTimesPhasor_imag_lsb 0 +#define p_reg_fste_cerTimesW_real 0xF5A3 +#define reg_fste_cerTimesW_real_pos 0 +#define reg_fste_cerTimesW_real_len 1 +#define reg_fste_cerTimesW_real_lsb 0 +#define p_reg_fste_cerTimesW_imag 0xF5A4 +#define reg_fste_cerTimesW_imag_pos 0 +#define reg_fste_cerTimesW_imag_len 1 +#define reg_fste_cerTimesW_imag_lsb 0 +#define p_reg_fste_cerTimesWAccum_real 0xF5A5 +#define reg_fste_cerTimesWAccum_real_pos 0 +#define reg_fste_cerTimesWAccum_real_len 1 +#define reg_fste_cerTimesWAccum_real_lsb 0 +#define p_reg_fste_cerTimesWAccum_imag 0xF5A6 +#define reg_fste_cerTimesWAccum_imag_pos 0 +#define reg_fste_cerTimesWAccum_imag_len 1 +#define reg_fste_cerTimesWAccum_imag_lsb 0 +#define p_reg_fste_cost 0xF5A7 +#define reg_fste_cost_pos 0 +#define reg_fste_cost_len 1 +#define reg_fste_cost_lsb 0 +#define p_fd_tpsd_en 0xF5A8 +#define fd_tpsd_en_pos 0 +#define fd_tpsd_en_len 1 +#define fd_tpsd_en_lsb 0 +#define p_fd_tpsd_lock 0xF5A9 +#define fd_tpsd_lock_pos 0 +#define fd_tpsd_lock_len 1 +#define fd_tpsd_lock_lsb 0 +#define r_fd_tpsd_s19 0xF5AA +#define fd_tpsd_s19_pos 0 +#define fd_tpsd_s19_len 1 +#define fd_tpsd_s19_lsb 0 +#define r_fd_tpsd_s17 0xF5AB +#define fd_tpsd_s17_pos 0 +#define fd_tpsd_s17_len 1 +#define fd_tpsd_s17_lsb 0 +#define p_fd_sfr_ste_en 0xF5AC +#define fd_sfr_ste_en_pos 0 +#define fd_sfr_ste_en_len 1 +#define fd_sfr_ste_en_lsb 0 +#define p_fd_sfr_ste_mode 0xF5AD +#define fd_sfr_ste_mode_pos 0 +#define fd_sfr_ste_mode_len 2 +#define fd_sfr_ste_mode_lsb 0 +#define p_fd_sfr_ste_done 0xF5AE +#define fd_sfr_ste_done_pos 0 +#define fd_sfr_ste_done_len 1 +#define fd_sfr_ste_done_lsb 0 +#define p_reg_cfoe_ffoe_en 0xF5AF +#define reg_cfoe_ffoe_en_pos 0 +#define reg_cfoe_ffoe_en_len 1 +#define reg_cfoe_ffoe_en_lsb 0 +#define p_reg_cfoe_ifoe_en 0xF5B0 +#define reg_cfoe_ifoe_en_pos 0 +#define reg_cfoe_ifoe_en_len 1 +#define reg_cfoe_ifoe_en_lsb 0 +#define p_reg_cfoe_fot_en 0xF5B1 +#define reg_cfoe_fot_en_pos 0 +#define reg_cfoe_fot_en_len 1 +#define reg_cfoe_fot_en_lsb 0 +#define p_reg_cfoe_fot_lm_en 0xF5B2 +#define reg_cfoe_fot_lm_en_pos 0 +#define reg_cfoe_fot_lm_en_len 1 +#define reg_cfoe_fot_lm_en_lsb 0 +#define p_reg_cfoe_fot_rst 0xF5B3 +#define reg_cfoe_fot_rst_pos 0 +#define reg_cfoe_fot_rst_len 1 +#define reg_cfoe_fot_rst_lsb 0 +#define r_fd_cfoe_ffoe_done 0xF5B4 +#define fd_cfoe_ffoe_done_pos 0 +#define fd_cfoe_ffoe_done_len 1 +#define fd_cfoe_ffoe_done_lsb 0 +#define p_fd_cfoe_metric_vld 0xF5B5 +#define fd_cfoe_metric_vld_pos 0 +#define fd_cfoe_metric_vld_len 1 +#define fd_cfoe_metric_vld_lsb 0 +#define p_reg_cfoe_ifod_vld 0xF5B6 +#define reg_cfoe_ifod_vld_pos 0 +#define reg_cfoe_ifod_vld_len 1 +#define reg_cfoe_ifod_vld_lsb 0 +#define r_fd_cfoe_ifoe_done 0xF5B7 +#define fd_cfoe_ifoe_done_pos 0 +#define fd_cfoe_ifoe_done_len 1 +#define fd_cfoe_ifoe_done_lsb 0 +#define p_reg_cfoe_ifoe_spec_inv 0xF5B8 +#define reg_cfoe_ifoe_spec_inv_pos 0 +#define reg_cfoe_ifoe_spec_inv_len 1 +#define reg_cfoe_ifoe_spec_inv_lsb 0 +#define p_reg_cfoe_divg_int 0xF5B9 +#define reg_cfoe_divg_int_pos 0 +#define reg_cfoe_divg_int_len 1 +#define reg_cfoe_divg_int_lsb 0 +#define r_reg_cfoe_divg_flag 0xF5BA +#define reg_cfoe_divg_flag_pos 0 +#define reg_cfoe_divg_flag_len 1 +#define reg_cfoe_divg_flag_lsb 0 +#define p_reg_sfoe_en 0xF5BB +#define reg_sfoe_en_pos 0 +#define reg_sfoe_en_len 1 +#define reg_sfoe_en_lsb 0 +#define p_reg_sfoe_dis 0xF5BC +#define reg_sfoe_dis_pos 0 +#define reg_sfoe_dis_len 1 +#define reg_sfoe_dis_lsb 0 +#define p_reg_sfoe_rst 0xF5BD +#define reg_sfoe_rst_pos 0 +#define reg_sfoe_rst_len 1 +#define reg_sfoe_rst_lsb 0 +#define p_reg_sfoe_vld_int 0xF5BE +#define reg_sfoe_vld_int_pos 0 +#define reg_sfoe_vld_int_len 1 +#define reg_sfoe_vld_int_lsb 0 +#define p_reg_sfoe_lm_en 0xF5BF +#define reg_sfoe_lm_en_pos 0 +#define reg_sfoe_lm_en_len 1 +#define reg_sfoe_lm_en_lsb 0 +#define p_reg_sfoe_divg_int 0xF5C0 +#define reg_sfoe_divg_int_pos 0 +#define reg_sfoe_divg_int_len 1 +#define reg_sfoe_divg_int_lsb 0 +#define r_reg_sfoe_divg_flag 0xF5C1 +#define reg_sfoe_divg_flag_pos 0 +#define reg_sfoe_divg_flag_len 1 +#define reg_sfoe_divg_flag_lsb 0 +#define p_reg_fft_rst 0xF5C2 +#define reg_fft_rst_pos 0 +#define reg_fft_rst_len 1 +#define reg_fft_rst_lsb 0 +#define p_reg_fft_mask2_en 0xF5C3 +#define reg_fft_mask2_en_pos 0 +#define reg_fft_mask2_en_len 1 +#define reg_fft_mask2_en_lsb 0 +#define p_reg_fft_mask3_en 0xF5C4 +#define reg_fft_mask3_en_pos 0 +#define reg_fft_mask3_en_len 1 +#define reg_fft_mask3_en_lsb 0 +#define p_reg_fft_crc_en 0xF5C5 +#define reg_fft_crc_en_pos 0 +#define reg_fft_crc_en_len 1 +#define reg_fft_crc_en_lsb 0 +#define p_reg_fft_mask0_en 0xF5C6 +#define reg_fft_mask0_en_pos 0 +#define reg_fft_mask0_en_len 1 +#define reg_fft_mask0_en_lsb 0 +#define p_reg_fft_mask1_en 0xF5C7 +#define reg_fft_mask1_en_pos 0 +#define reg_fft_mask1_en_len 1 +#define reg_fft_mask1_en_lsb 0 +#define p_fd_fste_en 0xF5C8 +#define fd_fste_en_pos 0 +#define fd_fste_en_len 1 +#define fd_fste_en_lsb 0 +#define p_reg_feq_eh2_comp_en 0xF5C9 +#define reg_feq_eh2_comp_en_pos 0 +#define reg_feq_eh2_comp_en_len 1 +#define reg_feq_eh2_comp_en_lsb 0 +#define p_reg_feq_read_update 0xF5CA +#define reg_feq_read_update_pos 0 +#define reg_feq_read_update_len 1 +#define reg_feq_read_update_lsb 0 +#define p_reg_feq_data_vld 0xF5CB +#define reg_feq_data_vld_pos 0 +#define reg_feq_data_vld_len 1 +#define reg_feq_data_vld_lsb 0 +#define p_reg_feq_tone_idx_7_0 0xF5CC +#define reg_feq_tone_idx_7_0_pos 0 +#define reg_feq_tone_idx_7_0_len 8 +#define reg_feq_tone_idx_7_0_lsb 0 +#define p_reg_feq_tone_idx_12_8 0xF5CD +#define reg_feq_tone_idx_12_8_pos 0 +#define reg_feq_tone_idx_12_8_len 5 +#define reg_feq_tone_idx_12_8_lsb 8 +#define r_reg_feq_data_re_7_0 0xF5CE +#define reg_feq_data_re_7_0_pos 0 +#define reg_feq_data_re_7_0_len 8 +#define reg_feq_data_re_7_0_lsb 0 +#define r_reg_feq_data_re_15_8 0xF5CF +#define reg_feq_data_re_15_8_pos 0 +#define reg_feq_data_re_15_8_len 8 +#define reg_feq_data_re_15_8_lsb 8 +#define r_reg_feq_data_re_21_16 0xF5D0 +#define reg_feq_data_re_21_16_pos 0 +#define reg_feq_data_re_21_16_len 6 +#define reg_feq_data_re_21_16_lsb 16 +#define r_reg_feq_data_im_7_0 0xF5D1 +#define reg_feq_data_im_7_0_pos 0 +#define reg_feq_data_im_7_0_len 8 +#define reg_feq_data_im_7_0_lsb 0 +#define r_reg_feq_data_im_15_8 0xF5D2 +#define reg_feq_data_im_15_8_pos 0 +#define reg_feq_data_im_15_8_len 8 +#define reg_feq_data_im_15_8_lsb 8 +#define r_reg_feq_data_im_21_16 0xF5D3 +#define reg_feq_data_im_21_16_pos 0 +#define reg_feq_data_im_21_16_len 6 +#define reg_feq_data_im_21_16_lsb 16 +#define r_reg_feq_data_h2_7_0 0xF5D4 +#define reg_feq_data_h2_7_0_pos 0 +#define reg_feq_data_h2_7_0_len 8 +#define reg_feq_data_h2_7_0_lsb 0 +#define r_reg_feq_data_h2_15_8 0xF5D5 +#define reg_feq_data_h2_15_8_pos 0 +#define reg_feq_data_h2_15_8_len 8 +#define reg_feq_data_h2_15_8_lsb 8 +#define r_reg_feq_data_h2_18_16 0xF5D6 +#define reg_feq_data_h2_18_16_pos 0 +#define reg_feq_data_h2_18_16_len 3 +#define reg_feq_data_h2_18_16_lsb 16 +#define p_reg_fs_en 0xF5D7 +#define reg_fs_en_pos 0 +#define reg_fs_en_len 1 +#define reg_fs_en_lsb 0 +#define p_reg_fs_offset 0xF5D8 +#define reg_fs_offset_pos 0 +#define reg_fs_offset_len 3 +#define reg_fs_offset_lsb 0 +#define p_reg_fs_debug 0xF5D9 +#define reg_fs_debug_pos 0 +#define reg_fs_debug_len 1 +#define reg_fs_debug_lsb 0 +#define p_reg_fs_half_inv 0xF5DA +#define reg_fs_half_inv_pos 0 +#define reg_fs_half_inv_len 1 +#define reg_fs_half_inv_lsb 0 +#define p_reg_cdpf_currentfftposition_7_0 0xF5DB +#define reg_cdpf_currentfftposition_7_0_pos 0 +#define reg_cdpf_currentfftposition_7_0_len 8 +#define reg_cdpf_currentfftposition_7_0_lsb 0 +#define p_reg_cdpf_currentfftposition_14_8 0xF5DC +#define reg_cdpf_currentfftposition_14_8_pos 0 +#define reg_cdpf_currentfftposition_14_8_len 7 +#define reg_cdpf_currentfftposition_14_8_lsb 8 +#define r_reg_cdpf_fftshift_7_0 0xF5DD +#define reg_cdpf_fftshift_7_0_pos 0 +#define reg_cdpf_fftshift_7_0_len 8 +#define reg_cdpf_fftshift_7_0_lsb 0 +#define r_reg_cdpf_fftshift_13_8 0xF5DE +#define reg_cdpf_fftshift_13_8_pos 0 +#define reg_cdpf_fftshift_13_8_len 6 +#define reg_cdpf_fftshift_13_8_lsb 8 +#define p_reg_cdpf_channelpowerdown_7_0 0xF5DF +#define reg_cdpf_channelpowerdown_7_0_pos 0 +#define reg_cdpf_channelpowerdown_7_0_len 8 +#define reg_cdpf_channelpowerdown_7_0_lsb 0 +#define p_reg_cdpf_channelpowerdown_10_8 0xF5E0 +#define reg_cdpf_channelpowerdown_10_8_pos 0 +#define reg_cdpf_channelpowerdown_10_8_len 3 +#define reg_cdpf_channelpowerdown_10_8_lsb 8 +#define p_reg_cdpf_state 0xF5E1 +#define reg_cdpf_state_pos 0 +#define reg_cdpf_state_len 4 +#define reg_cdpf_state_lsb 0 +#define p_reg_cdpf_echotestsearchingrange 0xF5E2 +#define reg_cdpf_echotestsearchingrange_pos 0 +#define reg_cdpf_echotestsearchingrange_len 8 +#define reg_cdpf_echotestsearchingrange_lsb 0 +#define p_reg_cdpf_rxsymboldelay 0xF5E3 +#define reg_cdpf_rxsymboldelay_pos 0 +#define reg_cdpf_rxsymboldelay_len 4 +#define reg_cdpf_rxsymboldelay_lsb 0 +#define p_reg_cdpf_ceavesymbolno 0xF5E4 +#define reg_cdpf_ceavesymbolno_pos 0 +#define reg_cdpf_ceavesymbolno_len 4 +#define reg_cdpf_ceavesymbolno_lsb 0 +#define p_reg_cdpf_ceshift 0xF5E5 +#define reg_cdpf_ceshift_pos 0 +#define reg_cdpf_ceshift_len 3 +#define reg_cdpf_ceshift_lsb 0 +#define p_reg_cdpf_postpreechotry 0xF5E6 +#define reg_cdpf_postpreechotry_pos 0 +#define reg_cdpf_postpreechotry_len 2 +#define reg_cdpf_postpreechotry_lsb 0 +#define p_reg_cdpf_en 0xF5E7 +#define reg_cdpf_en_pos 0 +#define reg_cdpf_en_len 1 +#define reg_cdpf_en_lsb 0 +#define p_reg_cdpf_stateready 0xF5E8 +#define reg_cdpf_stateready_pos 0 +#define reg_cdpf_stateready_len 1 +#define reg_cdpf_stateready_lsb 0 +#define r_reg_cdpf_prepostpowercompare 0xF5E9 +#define reg_cdpf_prepostpowercompare_pos 0 +#define reg_cdpf_prepostpowercompare_len 1 +#define reg_cdpf_prepostpowercompare_lsb 0 +#define r_reg_cdpf_candidateno 0xF5EA +#define reg_cdpf_candidateno_pos 0 +#define reg_cdpf_candidateno_len 6 +#define reg_cdpf_candidateno_lsb 0 +#define p_reg_cdpf_preechopower_7_0 0xF5EB +#define reg_cdpf_preechopower_7_0_pos 0 +#define reg_cdpf_preechopower_7_0_len 8 +#define reg_cdpf_preechopower_7_0_lsb 0 +#define p_reg_cdpf_preechopower_15_8 0xF5EC +#define reg_cdpf_preechopower_15_8_pos 0 +#define reg_cdpf_preechopower_15_8_len 8 +#define reg_cdpf_preechopower_15_8_lsb 8 +#define p_reg_cdpf_postechopower_7_0 0xF5ED +#define reg_cdpf_postechopower_7_0_pos 0 +#define reg_cdpf_postechopower_7_0_len 8 +#define reg_cdpf_postechopower_7_0_lsb 0 +#define p_reg_cdpf_postechopower_15_8 0xF5EE +#define reg_cdpf_postechopower_15_8_pos 0 +#define reg_cdpf_postechopower_15_8_len 8 +#define reg_cdpf_postechopower_15_8_lsb 8 +#define p_reg_cdpf_searchingend 0xF5EF +#define reg_cdpf_searchingend_pos 0 +#define reg_cdpf_searchingend_len 8 +#define reg_cdpf_searchingend_lsb 0 +#define r_reg_cdpf_candidate_7_0 0xF5F0 +#define reg_cdpf_candidate_7_0_pos 0 +#define reg_cdpf_candidate_7_0_len 8 +#define reg_cdpf_candidate_7_0_lsb 0 +#define r_reg_cdpf_candidate_15_8 0xF5F1 +#define reg_cdpf_candidate_15_8_pos 0 +#define reg_cdpf_candidate_15_8_len 8 +#define reg_cdpf_candidate_15_8_lsb 8 +#define p_reg_cdpf_candidate_rptr 0xF5F2 +#define reg_cdpf_candidate_rptr_pos 0 +#define reg_cdpf_candidate_rptr_len 7 +#define reg_cdpf_candidate_rptr_lsb 0 +#define p_reg_cdpf_candidate_rptr_force 0xF5F3 +#define reg_cdpf_candidate_rptr_force_pos 0 +#define reg_cdpf_candidate_rptr_force_len 1 +#define reg_cdpf_candidate_rptr_force_lsb 0 +#define p_reg_cdpf_trialshiftoffset_7_0 0xF5F4 +#define reg_cdpf_trialshiftoffset_7_0_pos 0 +#define reg_cdpf_trialshiftoffset_7_0_len 8 +#define reg_cdpf_trialshiftoffset_7_0_lsb 0 +#define p_reg_cdpf_trialshiftoffset_13_8 0xF5F5 +#define reg_cdpf_trialshiftoffset_13_8_pos 0 +#define reg_cdpf_trialshiftoffset_13_8_len 6 +#define reg_cdpf_trialshiftoffset_13_8_lsb 8 +#define p_reg_cdpf_channellength_7_0 0xF5F6 +#define reg_cdpf_channellength_7_0_pos 0 +#define reg_cdpf_channellength_7_0_len 8 +#define reg_cdpf_channellength_7_0_lsb 0 +#define p_reg_cdpf_channellength_12_8 0xF5F7 +#define reg_cdpf_channellength_12_8_pos 0 +#define reg_cdpf_channellength_12_8_len 5 +#define reg_cdpf_channellength_12_8_lsb 8 +#define p_reg_cdpf_hardwaresort 0xF5F8 +#define reg_cdpf_hardwaresort_pos 0 +#define reg_cdpf_hardwaresort_len 1 +#define reg_cdpf_hardwaresort_lsb 0 +#define p_reg_cdpf_maxcandidateno 0xF5F9 +#define reg_cdpf_maxcandidateno_pos 0 +#define reg_cdpf_maxcandidateno_len 3 +#define reg_cdpf_maxcandidateno_lsb 0 +#define p_reg_cdpf_channelleftindex 0xF5FA +#define reg_cdpf_channelleftindex_pos 0 +#define reg_cdpf_channelleftindex_len 4 +#define reg_cdpf_channelleftindex_lsb 0 +#define r_reg_cdpf_fdishift_7_0 0xF5FB +#define reg_cdpf_fdishift_7_0_pos 0 +#define reg_cdpf_fdishift_7_0_len 8 +#define reg_cdpf_fdishift_7_0_lsb 0 +#define r_reg_cdpf_fdishift_15_8 0xF5FC +#define reg_cdpf_fdishift_15_8_pos 0 +#define reg_cdpf_fdishift_15_8_len 8 +#define reg_cdpf_fdishift_15_8_lsb 8 +#define p_reg_cdpf_guardband 0xF5FD +#define reg_cdpf_guardband_pos 0 +#define reg_cdpf_guardband_len 5 +#define reg_cdpf_guardband_lsb 0 +#define p_reg_cdpf_maxtonemaxindex_7_0 0xF5FE +#define reg_cdpf_maxtonemaxindex_7_0_pos 0 +#define reg_cdpf_maxtonemaxindex_7_0_len 8 +#define reg_cdpf_maxtonemaxindex_7_0_lsb 0 +#define p_reg_cdpf_maxtonemaxindex_12_8 0xF5FF +#define reg_cdpf_maxtonemaxindex_12_8_pos 0 +#define reg_cdpf_maxtonemaxindex_12_8_len 5 +#define reg_cdpf_maxtonemaxindex_12_8_lsb 8 +#define p_reg_cdpf_fdiw0 0xF600 +#define reg_cdpf_fdiw0_pos 0 +#define reg_cdpf_fdiw0_len 7 +#define reg_cdpf_fdiw0_lsb 0 +#define p_reg_cdpf_fdiw1 0xF601 +#define reg_cdpf_fdiw1_pos 0 +#define reg_cdpf_fdiw1_len 7 +#define reg_cdpf_fdiw1_lsb 0 +#define p_reg_cdpf_fdiw2 0xF602 +#define reg_cdpf_fdiw2_pos 0 +#define reg_cdpf_fdiw2_len 7 +#define reg_cdpf_fdiw2_lsb 0 +#define p_reg_cdpf_fdiw3 0xF603 +#define reg_cdpf_fdiw3_pos 0 +#define reg_cdpf_fdiw3_len 7 +#define reg_cdpf_fdiw3_lsb 0 +#define p_reg_cdpf_fdiw4 0xF604 +#define reg_cdpf_fdiw4_pos 0 +#define reg_cdpf_fdiw4_len 7 +#define reg_cdpf_fdiw4_lsb 0 +#define p_reg_cdpf_fdiw5 0xF605 +#define reg_cdpf_fdiw5_pos 0 +#define reg_cdpf_fdiw5_len 7 +#define reg_cdpf_fdiw5_lsb 0 +#define p_reg_cdpf_fdiw6 0xF606 +#define reg_cdpf_fdiw6_pos 0 +#define reg_cdpf_fdiw6_len 7 +#define reg_cdpf_fdiw6_lsb 0 +#define p_reg_cdpf_fdiw7 0xF607 +#define reg_cdpf_fdiw7_pos 0 +#define reg_cdpf_fdiw7_len 7 +#define reg_cdpf_fdiw7_lsb 0 +#define r_reg_cdpf_fdiwindowsize 0xF608 +#define reg_cdpf_fdiwindowsize_pos 0 +#define reg_cdpf_fdiwindowsize_len 4 +#define reg_cdpf_fdiwindowsize_lsb 0 +#define p_reg_stes_mode 0xF609 +#define reg_stes_mode_pos 0 +#define reg_stes_mode_len 1 +#define reg_stes_mode_lsb 0 +#define p_reg_stes_done_st 0xF60A +#define reg_stes_done_st_pos 0 +#define reg_stes_done_st_len 2 +#define reg_stes_done_st_lsb 0 +#define p_reg_stes_done 0xF60B +#define reg_stes_done_pos 0 +#define reg_stes_done_len 1 +#define reg_stes_done_lsb 0 +#define p_reg_stes_timing_7_0 0xF60C +#define reg_stes_timing_7_0_pos 0 +#define reg_stes_timing_7_0_len 8 +#define reg_stes_timing_7_0_lsb 0 +#define p_reg_stes_timing_15_8 0xF60D +#define reg_stes_timing_15_8_pos 0 +#define reg_stes_timing_15_8_len 8 +#define reg_stes_timing_15_8_lsb 8 +#define p_reg_stes_sym_tot_adj_thre_7_0 0xF60E +#define reg_stes_sym_tot_adj_thre_7_0_pos 0 +#define reg_stes_sym_tot_adj_thre_7_0_len 8 +#define reg_stes_sym_tot_adj_thre_7_0_lsb 0 +#define p_reg_stes_sym_tot_adj_thre_15_8 0xF60F +#define reg_stes_sym_tot_adj_thre_15_8_pos 0 +#define reg_stes_sym_tot_adj_thre_15_8_len 8 +#define reg_stes_sym_tot_adj_thre_15_8_lsb 8 +#define p_reg_stes_sym_thre_9_2 0xF610 +#define reg_stes_sym_thre_9_2_pos 0 +#define reg_stes_sym_thre_9_2_len 8 +#define reg_stes_sym_thre_9_2_lsb 0 +#define p_reg_stes_sym_wo_adj_thre_9_2 0xF611 +#define reg_stes_sym_wo_adj_thre_9_2_pos 0 +#define reg_stes_sym_wo_adj_thre_9_2_len 8 +#define reg_stes_sym_wo_adj_thre_9_2_lsb 0 +#define p_reg_fste_i_adj_7_0 0xF612 +#define reg_fste_i_adj_7_0_pos 0 +#define reg_fste_i_adj_7_0_len 8 +#define reg_fste_i_adj_7_0_lsb 0 +#define p_reg_fste_i_adj_15_8 0xF613 +#define reg_fste_i_adj_15_8_pos 0 +#define reg_fste_i_adj_15_8_len 8 +#define reg_fste_i_adj_15_8_lsb 8 +#define r_fd_stes_iadj_val_7_0 0xF614 +#define fd_stes_iadj_val_7_0_pos 0 +#define fd_stes_iadj_val_7_0_len 8 +#define fd_stes_iadj_val_7_0_lsb 0 +#define r_fd_stes_iadj_val_15_8 0xF615 +#define fd_stes_iadj_val_15_8_pos 0 +#define fd_stes_iadj_val_15_8_len 8 +#define fd_stes_iadj_val_15_8_lsb 8 +#define r_fd_stes_symb_cnt_9_2 0xF616 +#define fd_stes_symb_cnt_9_2_pos 0 +#define fd_stes_symb_cnt_9_2_len 8 +#define fd_stes_symb_cnt_9_2_lsb 0 +#define r_fd_stes_snoi_cnt_9_2 0xF617 +#define fd_stes_snoi_cnt_9_2_pos 0 +#define fd_stes_snoi_cnt_9_2_len 8 +#define fd_stes_snoi_cnt_9_2_lsb 0 +#define r_fd_last_iadj_val_7_0 0xF618 +#define fd_last_iadj_val_7_0_pos 0 +#define fd_last_iadj_val_7_0_len 8 +#define fd_last_iadj_val_7_0_lsb 0 +#define r_fd_last_iadj_val_15_8 0xF619 +#define fd_last_iadj_val_15_8_pos 0 +#define fd_last_iadj_val_15_8_len 8 +#define fd_last_iadj_val_15_8_lsb 8 +#define p_reg_stes_bypass 0xF61A +#define reg_stes_bypass_pos 0 +#define reg_stes_bypass_len 1 +#define reg_stes_bypass_lsb 0 +#define p_reg_stes_best_timing_idx 0xF61B +#define reg_stes_best_timing_idx_pos 0 +#define reg_stes_best_timing_idx_len 4 +#define reg_stes_best_timing_idx_lsb 0 +#define p_reg_stes_iadj_val_7_0 0xF61C +#define reg_stes_iadj_val_7_0_pos 0 +#define reg_stes_iadj_val_7_0_len 8 +#define reg_stes_iadj_val_7_0_lsb 0 +#define p_reg_stes_iadj_val_15_8 0xF61D +#define reg_stes_iadj_val_15_8_pos 0 +#define reg_stes_iadj_val_15_8_len 8 +#define reg_stes_iadj_val_15_8_lsb 8 +#define p_reg_p_ste_start_guard_7_0 0xF620 +#define reg_p_ste_start_guard_7_0_pos 0 +#define reg_p_ste_start_guard_7_0_len 8 +#define reg_p_ste_start_guard_7_0_lsb 0 +#define p_reg_p_ste_start_guard_9_8 0xF621 +#define reg_p_ste_start_guard_9_8_pos 0 +#define reg_p_ste_start_guard_9_8_len 2 +#define reg_p_ste_start_guard_9_8_lsb 8 +#define p_reg_p_ste_end_guard_7_0 0xF622 +#define reg_p_ste_end_guard_7_0_pos 0 +#define reg_p_ste_end_guard_7_0_len 8 +#define reg_p_ste_end_guard_7_0_lsb 0 +#define p_reg_p_ste_end_guard_9_8 0xF623 +#define reg_p_ste_end_guard_9_8_pos 0 +#define reg_p_ste_end_guard_9_8_len 2 +#define reg_p_ste_end_guard_9_8_lsb 8 +#define r_reg_r_ste_wrong_beacon_count 0xF624 +#define reg_r_ste_wrong_beacon_count_pos 0 +#define reg_r_ste_wrong_beacon_count_len 7 +#define reg_r_ste_wrong_beacon_count_lsb 0 +#define p_reg_p_fccid_en 0xF625 +#define reg_p_fccid_en_pos 0 +#define reg_p_fccid_en_len 1 +#define reg_p_fccid_en_lsb 0 +#define p_reg_p_fccid_fft_ave_symbol_num 0xF626 +#define reg_p_fccid_fft_ave_symbol_num_pos 0 +#define reg_p_fccid_fft_ave_symbol_num_len 6 +#define reg_p_fccid_fft_ave_symbol_num_lsb 0 +#define p_reg_p_fccid_fft_work_start_tone_7_0 0xF627 +#define reg_p_fccid_fft_work_start_tone_7_0_pos 0 +#define reg_p_fccid_fft_work_start_tone_7_0_len 8 +#define reg_p_fccid_fft_work_start_tone_7_0_lsb 0 +#define p_reg_p_fccid_fft_work_start_tone_12_8 0xF628 +#define reg_p_fccid_fft_work_start_tone_12_8_pos 0 +#define reg_p_fccid_fft_work_start_tone_12_8_len 5 +#define reg_p_fccid_fft_work_start_tone_12_8_lsb 8 +#define p_reg_p_fccid_fft_work_end_tone_7_0 0xF629 +#define reg_p_fccid_fft_work_end_tone_7_0_pos 0 +#define reg_p_fccid_fft_work_end_tone_7_0_len 8 +#define reg_p_fccid_fft_work_end_tone_7_0_lsb 0 +#define p_reg_p_fccid_fft_work_end_tone_12_8 0xF62A +#define reg_p_fccid_fft_work_end_tone_12_8_pos 0 +#define reg_p_fccid_fft_work_end_tone_12_8_len 5 +#define reg_p_fccid_fft_work_end_tone_12_8_lsb 8 +#define p_reg_p_fccid_peak_to_th_divider 0xF62B +#define reg_p_fccid_peak_to_th_divider_pos 0 +#define reg_p_fccid_peak_to_th_divider_len 4 +#define reg_p_fccid_peak_to_th_divider_lsb 0 +#define p_reg_p_fccid_peak_to_th_mode 0xF62C +#define reg_p_fccid_peak_to_th_mode_pos 0 +#define reg_p_fccid_peak_to_th_mode_len 2 +#define reg_p_fccid_peak_to_th_mode_lsb 0 +#define p_reg_p_fccid_search_mode 0xF62D +#define reg_p_fccid_search_mode_pos 0 +#define reg_p_fccid_search_mode_len 1 +#define reg_p_fccid_search_mode_lsb 0 +#define p_reg_p_fccid_group_th 0xF62E +#define reg_p_fccid_group_th_pos 0 +#define reg_p_fccid_group_th_len 7 +#define reg_p_fccid_group_th_lsb 0 +#define p_reg_p_fccid_search_rdy 0xF62F +#define reg_p_fccid_search_rdy_pos 0 +#define reg_p_fccid_search_rdy_len 1 +#define reg_p_fccid_search_rdy_lsb 0 +#define r_reg_r_fccid_fft_ave_read_out_7_0 0xF630 +#define reg_r_fccid_fft_ave_read_out_7_0_pos 0 +#define reg_r_fccid_fft_ave_read_out_7_0_len 8 +#define reg_r_fccid_fft_ave_read_out_7_0_lsb 0 +#define r_reg_r_fccid_fft_ave_read_out_15_8 0xF631 +#define reg_r_fccid_fft_ave_read_out_15_8_pos 0 +#define reg_r_fccid_fft_ave_read_out_15_8_len 8 +#define reg_r_fccid_fft_ave_read_out_15_8_lsb 8 +#define r_reg_r_fccid_large_tone_num_7_0 0xF632 +#define reg_r_fccid_large_tone_num_7_0_pos 0 +#define reg_r_fccid_large_tone_num_7_0_len 8 +#define reg_r_fccid_large_tone_num_7_0_lsb 0 +#define r_reg_r_fccid_large_tone_num_12_8 0xF633 +#define reg_r_fccid_large_tone_num_12_8_pos 0 +#define reg_r_fccid_large_tone_num_12_8_len 5 +#define reg_r_fccid_large_tone_num_12_8_lsb 8 +#define r_reg_r_fccid_cci1_start_tone_7_0 0xF634 +#define reg_r_fccid_cci1_start_tone_7_0_pos 0 +#define reg_r_fccid_cci1_start_tone_7_0_len 8 +#define reg_r_fccid_cci1_start_tone_7_0_lsb 0 +#define r_reg_r_fccid_cci1_start_tone_12_8 0xF635 +#define reg_r_fccid_cci1_start_tone_12_8_pos 0 +#define reg_r_fccid_cci1_start_tone_12_8_len 5 +#define reg_r_fccid_cci1_start_tone_12_8_lsb 8 +#define r_reg_r_fccid_cci1_end_tone_7_0 0xF636 +#define reg_r_fccid_cci1_end_tone_7_0_pos 0 +#define reg_r_fccid_cci1_end_tone_7_0_len 8 +#define reg_r_fccid_cci1_end_tone_7_0_lsb 0 +#define r_reg_r_fccid_cci1_end_tone_12_8 0xF637 +#define reg_r_fccid_cci1_end_tone_12_8_pos 0 +#define reg_r_fccid_cci1_end_tone_12_8_len 5 +#define reg_r_fccid_cci1_end_tone_12_8_lsb 8 +#define r_reg_r_fccid_cci1_peak_7_0 0xF638 +#define reg_r_fccid_cci1_peak_7_0_pos 0 +#define reg_r_fccid_cci1_peak_7_0_len 8 +#define reg_r_fccid_cci1_peak_7_0_lsb 0 +#define r_reg_r_fccid_cci1_peak_15_8 0xF639 +#define reg_r_fccid_cci1_peak_15_8_pos 0 +#define reg_r_fccid_cci1_peak_15_8_len 8 +#define reg_r_fccid_cci1_peak_15_8_lsb 8 +#define r_reg_r_fccid_cci2_start_tone_7_0 0xF63A +#define reg_r_fccid_cci2_start_tone_7_0_pos 0 +#define reg_r_fccid_cci2_start_tone_7_0_len 8 +#define reg_r_fccid_cci2_start_tone_7_0_lsb 0 +#define r_reg_r_fccid_cci2_start_tone_12_8 0xF63B +#define reg_r_fccid_cci2_start_tone_12_8_pos 0 +#define reg_r_fccid_cci2_start_tone_12_8_len 5 +#define reg_r_fccid_cci2_start_tone_12_8_lsb 8 +#define r_reg_r_fccid_cci2_end_tone_7_0 0xF63C +#define reg_r_fccid_cci2_end_tone_7_0_pos 0 +#define reg_r_fccid_cci2_end_tone_7_0_len 8 +#define reg_r_fccid_cci2_end_tone_7_0_lsb 0 +#define r_reg_r_fccid_cci2_end_tone_12_8 0xF63D +#define reg_r_fccid_cci2_end_tone_12_8_pos 0 +#define reg_r_fccid_cci2_end_tone_12_8_len 5 +#define reg_r_fccid_cci2_end_tone_12_8_lsb 8 +#define r_reg_r_fccid_cci2_peak_7_0 0xF63E +#define reg_r_fccid_cci2_peak_7_0_pos 0 +#define reg_r_fccid_cci2_peak_7_0_len 8 +#define reg_r_fccid_cci2_peak_7_0_lsb 0 +#define r_reg_r_fccid_cci2_peak_15_8 0xF63F +#define reg_r_fccid_cci2_peak_15_8_pos 0 +#define reg_r_fccid_cci2_peak_15_8_len 8 +#define reg_r_fccid_cci2_peak_15_8_lsb 8 +#define r_reg_r_fccid_cci3_start_tone_7_0 0xF640 +#define reg_r_fccid_cci3_start_tone_7_0_pos 0 +#define reg_r_fccid_cci3_start_tone_7_0_len 8 +#define reg_r_fccid_cci3_start_tone_7_0_lsb 0 +#define r_reg_r_fccid_cci3_start_tone_12_8 0xF641 +#define reg_r_fccid_cci3_start_tone_12_8_pos 0 +#define reg_r_fccid_cci3_start_tone_12_8_len 5 +#define reg_r_fccid_cci3_start_tone_12_8_lsb 8 +#define r_reg_r_fccid_cci3_end_tone_7_0 0xF642 +#define reg_r_fccid_cci3_end_tone_7_0_pos 0 +#define reg_r_fccid_cci3_end_tone_7_0_len 8 +#define reg_r_fccid_cci3_end_tone_7_0_lsb 0 +#define r_reg_r_fccid_cci3_end_tone_12_8 0xF643 +#define reg_r_fccid_cci3_end_tone_12_8_pos 0 +#define reg_r_fccid_cci3_end_tone_12_8_len 5 +#define reg_r_fccid_cci3_end_tone_12_8_lsb 8 +#define r_reg_r_fccid_cci3_peak_7_0 0xF644 +#define reg_r_fccid_cci3_peak_7_0_pos 0 +#define reg_r_fccid_cci3_peak_7_0_len 8 +#define reg_r_fccid_cci3_peak_7_0_lsb 0 +#define r_reg_r_fccid_cci3_peak_15_8 0xF645 +#define reg_r_fccid_cci3_peak_15_8_pos 0 +#define reg_r_fccid_cci3_peak_15_8_len 8 +#define reg_r_fccid_cci3_peak_15_8_lsb 8 +#define r_reg_r_fccid_cci4_start_tone_7_0 0xF646 +#define reg_r_fccid_cci4_start_tone_7_0_pos 0 +#define reg_r_fccid_cci4_start_tone_7_0_len 8 +#define reg_r_fccid_cci4_start_tone_7_0_lsb 0 +#define r_reg_r_fccid_cci4_start_tone_12_8 0xF647 +#define reg_r_fccid_cci4_start_tone_12_8_pos 0 +#define reg_r_fccid_cci4_start_tone_12_8_len 5 +#define reg_r_fccid_cci4_start_tone_12_8_lsb 8 +#define r_reg_r_fccid_cci4_end_tone_7_0 0xF648 +#define reg_r_fccid_cci4_end_tone_7_0_pos 0 +#define reg_r_fccid_cci4_end_tone_7_0_len 8 +#define reg_r_fccid_cci4_end_tone_7_0_lsb 0 +#define r_reg_r_fccid_cci4_end_tone_12_8 0xF649 +#define reg_r_fccid_cci4_end_tone_12_8_pos 0 +#define reg_r_fccid_cci4_end_tone_12_8_len 5 +#define reg_r_fccid_cci4_end_tone_12_8_lsb 8 +#define r_reg_r_fccid_cci4_peak_7_0 0xF64A +#define reg_r_fccid_cci4_peak_7_0_pos 0 +#define reg_r_fccid_cci4_peak_7_0_len 8 +#define reg_r_fccid_cci4_peak_7_0_lsb 0 +#define r_reg_r_fccid_cci4_peak_15_8 0xF64B +#define reg_r_fccid_cci4_peak_15_8_pos 0 +#define reg_r_fccid_cci4_peak_15_8_len 8 +#define reg_r_fccid_cci4_peak_15_8_lsb 8 +#define r_reg_r_fccid_cci1_rank 0xF64C +#define reg_r_fccid_cci1_rank_pos 0 +#define reg_r_fccid_cci1_rank_len 3 +#define reg_r_fccid_cci1_rank_lsb 0 +#define r_reg_r_fccid_cci2_rank 0xF64D +#define reg_r_fccid_cci2_rank_pos 0 +#define reg_r_fccid_cci2_rank_len 3 +#define reg_r_fccid_cci2_rank_lsb 0 +#define r_reg_r_fccid_cci3_rank 0xF64E +#define reg_r_fccid_cci3_rank_pos 0 +#define reg_r_fccid_cci3_rank_len 3 +#define reg_r_fccid_cci3_rank_lsb 0 +#define r_reg_r_fccid_cci4_rank 0xF64F +#define reg_r_fccid_cci4_rank_pos 0 +#define reg_r_fccid_cci4_rank_len 3 +#define reg_r_fccid_cci4_rank_lsb 0 +#define p_reg_p_csi_shift3 0xF650 +#define reg_p_csi_shift3_pos 0 +#define reg_p_csi_shift3_len 4 +#define reg_p_csi_shift3_lsb 0 +#define p_reg_p_csi_mul3 0xF651 +#define reg_p_csi_mul3_pos 0 +#define reg_p_csi_mul3_len 8 +#define reg_p_csi_mul3_lsb 0 +#define p_reg_p_csi_level3_7_0 0xF652 +#define reg_p_csi_level3_7_0_pos 0 +#define reg_p_csi_level3_7_0_len 8 +#define reg_p_csi_level3_7_0_lsb 0 +#define p_reg_p_csi_level3_8 0xF653 +#define reg_p_csi_level3_8_pos 0 +#define reg_p_csi_level3_8_len 1 +#define reg_p_csi_level3_8_lsb 8 +#define p_reg_p_csi_fftout_shift_fix_value 0xF654 +#define reg_p_csi_fftout_shift_fix_value_pos 0 +#define reg_p_csi_fftout_shift_fix_value_len 4 +#define reg_p_csi_fftout_shift_fix_value_lsb 0 +#define p_reg_p_feq_scale_pow 0xF655 +#define reg_p_feq_scale_pow_pos 0 +#define reg_p_feq_scale_pow_len 6 +#define reg_p_feq_scale_pow_lsb 0 +#define p_reg_p_csi_cp_idx 0xF656 +#define reg_p_csi_cp_idx_pos 0 +#define reg_p_csi_cp_idx_len 8 +#define reg_p_csi_cp_idx_lsb 0 +#define p_reg_p_csi_outsh_zero_th_7_0 0xF657 +#define reg_p_csi_outsh_zero_th_7_0_pos 0 +#define reg_p_csi_outsh_zero_th_7_0_len 8 +#define reg_p_csi_outsh_zero_th_7_0_lsb 0 +#define p_reg_p_csi_outsh_zero_th_10_8 0xF658 +#define reg_p_csi_outsh_zero_th_10_8_pos 0 +#define reg_p_csi_outsh_zero_th_10_8_len 3 +#define reg_p_csi_outsh_zero_th_10_8_lsb 8 +#define p_reg_p_csi_ar_ratio 0xF659 +#define reg_p_csi_ar_ratio_pos 0 +#define reg_p_csi_ar_ratio_len 8 +#define reg_p_csi_ar_ratio_lsb 0 +#define p_reg_r_csi_cp_vld 0xF65A +#define reg_r_csi_cp_vld_pos 0 +#define reg_r_csi_cp_vld_len 1 +#define reg_r_csi_cp_vld_lsb 0 +#define p_reg_r_csi_sp_vld 0xF65B +#define reg_r_csi_sp_vld_pos 0 +#define reg_r_csi_sp_vld_len 1 +#define reg_r_csi_sp_vld_lsb 0 +#define p_reg_p_csi_fft_out_shift_en 0xF65C +#define reg_p_csi_fft_out_shift_en_pos 0 +#define reg_p_csi_fft_out_shift_en_len 1 +#define reg_p_csi_fft_out_shift_en_lsb 0 +#define p_reg_p_csi_feq_out_shift_en 0xF65D +#define reg_p_csi_feq_out_shift_en_pos 0 +#define reg_p_csi_feq_out_shift_en_len 1 +#define reg_p_csi_feq_out_shift_en_lsb 0 +#define p_reg_r_csi_cp_fft_out 0xF65E +#define reg_r_csi_cp_fft_out_pos 0 +#define reg_r_csi_cp_fft_out_len 1 +#define reg_r_csi_cp_fft_out_lsb 0 +#define p_reg_r_csi_sp_feq_log2_out 0xF65F +#define reg_r_csi_sp_feq_log2_out_pos 0 +#define reg_r_csi_sp_feq_log2_out_len 8 +#define reg_r_csi_sp_feq_log2_out_lsb 0 +#define p_reg_r_csi_sp_fft_out 0xF660 +#define reg_r_csi_sp_fft_out_pos 0 +#define reg_r_csi_sp_fft_out_len 1 +#define reg_r_csi_sp_fft_out_lsb 0 +#define p_reg_p_feq_eh2_from_fpcc_en 0xF661 +#define reg_p_feq_eh2_from_fpcc_en_pos 0 +#define reg_p_feq_eh2_from_fpcc_en_len 1 +#define reg_p_feq_eh2_from_fpcc_en_lsb 0 +#define r_reg_r_fccid_fft_ave_peak_7_0 0xF662 +#define reg_r_fccid_fft_ave_peak_7_0_pos 0 +#define reg_r_fccid_fft_ave_peak_7_0_len 8 +#define reg_r_fccid_fft_ave_peak_7_0_lsb 0 +#define r_reg_r_fccid_fft_ave_peak_15_8 0xF663 +#define reg_r_fccid_fft_ave_peak_15_8_pos 0 +#define reg_r_fccid_fft_ave_peak_15_8_len 8 +#define reg_r_fccid_fft_ave_peak_15_8_lsb 8 +#define r_reg_r_fccid_fft_ave_peak_23_16 0xF664 +#define reg_r_fccid_fft_ave_peak_23_16_pos 0 +#define reg_r_fccid_fft_ave_peak_23_16_len 8 +#define reg_r_fccid_fft_ave_peak_23_16_lsb 16 +#define r_reg_r_fccid_fft_ave_peak_26_24 0xF665 +#define reg_r_fccid_fft_ave_peak_26_24_pos 0 +#define reg_r_fccid_fft_ave_peak_26_24_len 3 +#define reg_r_fccid_fft_ave_peak_26_24_lsb 24 +#define p_reg_p_fccid_fft_ave_read_rdy 0xF666 +#define reg_p_fccid_fft_ave_read_rdy_pos 0 +#define reg_p_fccid_fft_ave_read_rdy_len 1 +#define reg_p_fccid_fft_ave_read_rdy_lsb 0 +#define p_reg_p_fccid_fft_ave_read_index_7_0 0xF667 +#define reg_p_fccid_fft_ave_read_index_7_0_pos 0 +#define reg_p_fccid_fft_ave_read_index_7_0_len 8 +#define reg_p_fccid_fft_ave_read_index_7_0_lsb 0 +#define p_reg_p_fccid_fft_ave_read_index_12_8 0xF668 +#define reg_p_fccid_fft_ave_read_index_12_8_pos 0 +#define reg_p_fccid_fft_ave_read_index_12_8_len 5 +#define reg_p_fccid_fft_ave_read_index_12_8_lsb 8 +#define p_reg_cdpf_candidate_rw 0xF669 +#define reg_cdpf_candidate_rw_pos 0 +#define reg_cdpf_candidate_rw_len 1 +#define reg_cdpf_candidate_rw_lsb 0 +#define p_reg_cdpf_candidate_prog_7_0 0xF66A +#define reg_cdpf_candidate_prog_7_0_pos 0 +#define reg_cdpf_candidate_prog_7_0_len 8 +#define reg_cdpf_candidate_prog_7_0_lsb 0 +#define p_reg_cdpf_candidate_prog_15_8 0xF66B +#define reg_cdpf_candidate_prog_15_8_pos 0 +#define reg_cdpf_candidate_prog_15_8_len 8 +#define reg_cdpf_candidate_prog_15_8_lsb 8 +#define p_reg_cdpf_candidateno_prog 0xF66C +#define reg_cdpf_candidateno_prog_pos 0 +#define reg_cdpf_candidateno_prog_len 6 +#define reg_cdpf_candidateno_prog_lsb 0 +#define p_reg_cdpf_candidateno_switch 0xF66D +#define reg_cdpf_candidateno_switch_pos 0 +#define reg_cdpf_candidateno_switch_len 1 +#define reg_cdpf_candidateno_switch_lsb 0 +#define g_reg_tpsd_txmod 0xF900 +#define reg_tpsd_txmod_pos 0 +#define reg_tpsd_txmod_len 2 +#define reg_tpsd_txmod_lsb 0 +#define g_reg_tpsd_gi 0xF901 +#define reg_tpsd_gi_pos 0 +#define reg_tpsd_gi_len 2 +#define reg_tpsd_gi_lsb 0 +#define g_reg_tpsd_hier 0xF902 +#define reg_tpsd_hier_pos 0 +#define reg_tpsd_hier_len 3 +#define reg_tpsd_hier_lsb 0 +#define g_reg_tpsd_const 0xF903 +#define reg_tpsd_const_pos 0 +#define reg_tpsd_const_len 2 +#define reg_tpsd_const_lsb 0 +#define g_reg_bw 0xF904 +#define reg_bw_pos 0 +#define reg_bw_len 2 +#define reg_bw_lsb 0 +#define g_reg_dec_pri 0xF905 +#define reg_dec_pri_pos 0 +#define reg_dec_pri_len 1 +#define reg_dec_pri_lsb 0 +#define g_reg_tpsd_hpcr 0xF906 +#define reg_tpsd_hpcr_pos 0 +#define reg_tpsd_hpcr_len 3 +#define reg_tpsd_hpcr_lsb 0 +#define g_reg_tpsd_lpcr 0xF907 +#define reg_tpsd_lpcr_pos 0 +#define reg_tpsd_lpcr_len 3 +#define reg_tpsd_lpcr_lsb 0 +#define g_reg_tpsd_indep 0xF908 +#define reg_tpsd_indep_pos 0 +#define reg_tpsd_indep_len 1 +#define reg_tpsd_indep_lsb 0 +#define g_reg_tpsd_tslice 0xF909 +#define reg_tpsd_tslice_pos 0 +#define reg_tpsd_tslice_len 1 +#define reg_tpsd_tslice_lsb 0 +#define g_reg_tpsd_mpefec 0xF90A +#define reg_tpsd_mpefec_pos 0 +#define reg_tpsd_mpefec_len 1 +#define reg_tpsd_mpefec_lsb 0 +#define g_reg_sntc_en 0xF90B +#define reg_sntc_en_pos 0 +#define reg_sntc_en_len 1 +#define reg_sntc_en_lsb 0 +#define g_reg_intp_sys_div 0xF90C +#define reg_intp_sys_div_pos 0 +#define reg_intp_sys_div_len 1 +#define reg_intp_sys_div_lsb 0 +#define g_reg_clk_sntc_sel 0xF90D +#define reg_clk_sntc_sel_pos 0 +#define reg_clk_sntc_sel_len 3 +#define reg_clk_sntc_sel_lsb 0 +#define p_reg_ce_gs_force 0xFD00 +#define reg_ce_gs_force_pos 0 +#define reg_ce_gs_force_len 1 +#define reg_ce_gs_force_lsb 0 +#define p_reg_ce_dagcgain_delay 0xFD01 +#define reg_ce_dagcgain_delay_pos 0 +#define reg_ce_dagcgain_delay_len 2 +#define reg_ce_dagcgain_delay_lsb 0 +#define p_reg_ce_derot_en 0xFD02 +#define reg_ce_derot_en_pos 0 +#define reg_ce_derot_en_len 1 +#define reg_ce_derot_en_lsb 0 +#define p_reg_ce_fctrl_en 0xFD05 +#define reg_ce_fctrl_en_pos 0 +#define reg_ce_fctrl_en_len 1 +#define reg_ce_fctrl_en_lsb 0 +#define p_reg_ce_en 0xFD06 +#define reg_ce_en_pos 0 +#define reg_ce_en_len 1 +#define reg_ce_en_lsb 0 +#define p_reg_ce_sat_wes 0xFD07 +#define reg_ce_sat_wes_pos 0 +#define reg_ce_sat_wes_len 1 +#define reg_ce_sat_wes_lsb 0 +#define p_reg_ce_sat_sigma2 0xFD08 +#define reg_ce_sat_sigma2_pos 0 +#define reg_ce_sat_sigma2_len 1 +#define reg_ce_sat_sigma2_lsb 0 +#define p_reg_ce_sat_tdi_br_re 0xFD09 +#define reg_ce_sat_tdi_br_re_pos 0 +#define reg_ce_sat_tdi_br_re_len 1 +#define reg_ce_sat_tdi_br_re_lsb 0 +#define p_reg_ce_sat_tdi_br_im 0xFD0A +#define reg_ce_sat_tdi_br_im_pos 0 +#define reg_ce_sat_tdi_br_im_len 1 +#define reg_ce_sat_tdi_br_im_lsb 0 +#define p_reg_ce_sat_tdi_ar_re 0xFD0B +#define reg_ce_sat_tdi_ar_re_pos 0 +#define reg_ce_sat_tdi_ar_re_len 1 +#define reg_ce_sat_tdi_ar_re_lsb 0 +#define p_reg_ce_sat_tdi_ar_im 0xFD0C +#define reg_ce_sat_tdi_ar_im_pos 0 +#define reg_ce_sat_tdi_ar_im_len 1 +#define reg_ce_sat_tdi_ar_im_lsb 0 +#define p_reg_ce_sat_fdi_br_re 0xFD0D +#define reg_ce_sat_fdi_br_re_pos 0 +#define reg_ce_sat_fdi_br_re_len 1 +#define reg_ce_sat_fdi_br_re_lsb 0 +#define p_reg_ce_sat_fdi_br_im 0xFD0E +#define reg_ce_sat_fdi_br_im_pos 0 +#define reg_ce_sat_fdi_br_im_len 1 +#define reg_ce_sat_fdi_br_im_lsb 0 +#define p_reg_ce_var_forced_value 0xFD0F +#define reg_ce_var_forced_value_pos 0 +#define reg_ce_var_forced_value_len 3 +#define reg_ce_var_forced_value_lsb 0 +#define p_reg_ce_s1 0xFD10 +#define reg_ce_s1_pos 0 +#define reg_ce_s1_len 5 +#define reg_ce_s1_lsb 0 +#define r_reg_ce_tdi_flatness_7_0 0xFD11 +#define reg_ce_tdi_flatness_7_0_pos 0 +#define reg_ce_tdi_flatness_7_0_len 8 +#define reg_ce_tdi_flatness_7_0_lsb 0 +#define r_reg_ce_tdi_flatness_8 0xFD12 +#define reg_ce_tdi_flatness_8_pos 0 +#define reg_ce_tdi_flatness_8_len 1 +#define reg_ce_tdi_flatness_8_lsb 8 +#define r_reg_ce_tone_7_0 0xFD13 +#define reg_ce_tone_7_0_pos 0 +#define reg_ce_tone_7_0_len 8 +#define reg_ce_tone_7_0_lsb 0 +#define r_reg_ce_tone_12_8 0xFD14 +#define reg_ce_tone_12_8_pos 0 +#define reg_ce_tone_12_8_len 5 +#define reg_ce_tone_12_8_lsb 8 +#define p_reg_ce_centroid_drift_th 0xFD15 +#define reg_ce_centroid_drift_th_pos 0 +#define reg_ce_centroid_drift_th_len 8 +#define reg_ce_centroid_drift_th_lsb 0 +#define p_reg_ce_centroid_bias_inc_7_0 0xFD16 +#define reg_ce_centroid_bias_inc_7_0_pos 0 +#define reg_ce_centroid_bias_inc_7_0_len 8 +#define reg_ce_centroid_bias_inc_7_0_lsb 0 +#define p_reg_ce_centroid_bias_inc_8 0xFD17 +#define reg_ce_centroid_bias_inc_8_pos 0 +#define reg_ce_centroid_bias_inc_8_len 1 +#define reg_ce_centroid_bias_inc_8_lsb 8 +#define p_reg_ce_centroid_count_max 0xFD18 +#define reg_ce_centroid_count_max_pos 0 +#define reg_ce_centroid_count_max_len 4 +#define reg_ce_centroid_count_max_lsb 0 +#define p_reg_ce_var_th0_7_0 0xFD19 +#define reg_ce_var_th0_7_0_pos 0 +#define reg_ce_var_th0_7_0_len 8 +#define reg_ce_var_th0_7_0_lsb 0 +#define p_reg_ce_var_th0_15_8 0xFD1A +#define reg_ce_var_th0_15_8_pos 0 +#define reg_ce_var_th0_15_8_len 8 +#define reg_ce_var_th0_15_8_lsb 8 +#define p_reg_ce_var_th1_7_0 0xFD1B +#define reg_ce_var_th1_7_0_pos 0 +#define reg_ce_var_th1_7_0_len 8 +#define reg_ce_var_th1_7_0_lsb 0 +#define p_reg_ce_var_th1_15_8 0xFD1C +#define reg_ce_var_th1_15_8_pos 0 +#define reg_ce_var_th1_15_8_len 8 +#define reg_ce_var_th1_15_8_lsb 8 +#define p_reg_ce_var_th2_7_0 0xFD1D +#define reg_ce_var_th2_7_0_pos 0 +#define reg_ce_var_th2_7_0_len 8 +#define reg_ce_var_th2_7_0_lsb 0 +#define p_reg_ce_var_th2_15_8 0xFD1E +#define reg_ce_var_th2_15_8_pos 0 +#define reg_ce_var_th2_15_8_len 8 +#define reg_ce_var_th2_15_8_lsb 8 +#define p_reg_ce_var_th3_7_0 0xFD1F +#define reg_ce_var_th3_7_0_pos 0 +#define reg_ce_var_th3_7_0_len 8 +#define reg_ce_var_th3_7_0_lsb 0 +#define p_reg_ce_var_th3_15_8 0xFD20 +#define reg_ce_var_th3_15_8_pos 0 +#define reg_ce_var_th3_15_8_len 8 +#define reg_ce_var_th3_15_8_lsb 8 +#define p_reg_ce_var_th4_7_0 0xFD21 +#define reg_ce_var_th4_7_0_pos 0 +#define reg_ce_var_th4_7_0_len 8 +#define reg_ce_var_th4_7_0_lsb 0 +#define p_reg_ce_var_th4_15_8 0xFD22 +#define reg_ce_var_th4_15_8_pos 0 +#define reg_ce_var_th4_15_8_len 8 +#define reg_ce_var_th4_15_8_lsb 8 +#define p_reg_ce_var_th5_7_0 0xFD23 +#define reg_ce_var_th5_7_0_pos 0 +#define reg_ce_var_th5_7_0_len 8 +#define reg_ce_var_th5_7_0_lsb 0 +#define p_reg_ce_var_th5_15_8 0xFD24 +#define reg_ce_var_th5_15_8_pos 0 +#define reg_ce_var_th5_15_8_len 8 +#define reg_ce_var_th5_15_8_lsb 8 +#define p_reg_ce_var_th6_7_0 0xFD25 +#define reg_ce_var_th6_7_0_pos 0 +#define reg_ce_var_th6_7_0_len 8 +#define reg_ce_var_th6_7_0_lsb 0 +#define p_reg_ce_var_th6_15_8 0xFD26 +#define reg_ce_var_th6_15_8_pos 0 +#define reg_ce_var_th6_15_8_len 8 +#define reg_ce_var_th6_15_8_lsb 8 +#define p_reg_ce_var_max 0xFD27 +#define reg_ce_var_max_pos 0 +#define reg_ce_var_max_len 3 +#define reg_ce_var_max_lsb 0 +#define p_reg_ce_cent_forced_en 0xFD28 +#define reg_ce_cent_forced_en_pos 0 +#define reg_ce_cent_forced_en_len 1 +#define reg_ce_cent_forced_en_lsb 0 +#define p_reg_ce_var_forced_en 0xFD29 +#define reg_ce_var_forced_en_pos 0 +#define reg_ce_var_forced_en_len 1 +#define reg_ce_var_forced_en_lsb 0 +#define p_reg_ce_fctrl_auto_reset_en 0xFD2A +#define reg_ce_fctrl_auto_reset_en_pos 0 +#define reg_ce_fctrl_auto_reset_en_len 1 +#define reg_ce_fctrl_auto_reset_en_lsb 0 +#define p_reg_ce_cent_auto_clr_en 0xFD2B +#define reg_ce_cent_auto_clr_en_pos 0 +#define reg_ce_cent_auto_clr_en_len 1 +#define reg_ce_cent_auto_clr_en_lsb 0 +#define p_reg_ce_fctrl_reset 0xFD2C +#define reg_ce_fctrl_reset_pos 0 +#define reg_ce_fctrl_reset_len 1 +#define reg_ce_fctrl_reset_lsb 0 +#define p_reg_ce_cent_forced_value_7_0 0xFD2D +#define reg_ce_cent_forced_value_7_0_pos 0 +#define reg_ce_cent_forced_value_7_0_len 8 +#define reg_ce_cent_forced_value_7_0_lsb 0 +#define p_reg_ce_cent_forced_value_11_8 0xFD2E +#define reg_ce_cent_forced_value_11_8_pos 0 +#define reg_ce_cent_forced_value_11_8_len 4 +#define reg_ce_cent_forced_value_11_8_lsb 8 +#define p_reg_ce_cent_auto_clr_value_7_0 0xFD2F +#define reg_ce_cent_auto_clr_value_7_0_pos 0 +#define reg_ce_cent_auto_clr_value_7_0_len 8 +#define reg_ce_cent_auto_clr_value_7_0_lsb 0 +#define p_reg_ce_cent_auto_clr_value_11_8 0xFD30 +#define reg_ce_cent_auto_clr_value_11_8_pos 0 +#define reg_ce_cent_auto_clr_value_11_8_len 4 +#define reg_ce_cent_auto_clr_value_11_8_lsb 8 +#define p_reg_ce_centroid_max_7_0 0xFD31 +#define reg_ce_centroid_max_7_0_pos 0 +#define reg_ce_centroid_max_7_0_len 8 +#define reg_ce_centroid_max_7_0_lsb 0 +#define p_reg_ce_centroid_max_11_8 0xFD32 +#define reg_ce_centroid_max_11_8_pos 0 +#define reg_ce_centroid_max_11_8_len 4 +#define reg_ce_centroid_max_11_8_lsb 8 +#define p_reg_ce_fctrl_rd 0xFD33 +#define reg_ce_fctrl_rd_pos 0 +#define reg_ce_fctrl_rd_len 1 +#define reg_ce_fctrl_rd_lsb 0 +#define r_reg_ce_centroid_out_7_0 0xFD34 +#define reg_ce_centroid_out_7_0_pos 0 +#define reg_ce_centroid_out_7_0_len 8 +#define reg_ce_centroid_out_7_0_lsb 0 +#define r_reg_ce_centroid_out_11_8 0xFD35 +#define reg_ce_centroid_out_11_8_pos 0 +#define reg_ce_centroid_out_11_8_len 4 +#define reg_ce_centroid_out_11_8_lsb 8 +#define r_reg_ce_fctrl_rdy 0xFD36 +#define reg_ce_fctrl_rdy_pos 0 +#define reg_ce_fctrl_rdy_len 1 +#define reg_ce_fctrl_rdy_lsb 0 +#define r_reg_ce_var 0xFD37 +#define reg_ce_var_pos 0 +#define reg_ce_var_len 3 +#define reg_ce_var_lsb 0 +#define r_reg_ce_bias_7_0 0xFD38 +#define reg_ce_bias_7_0_pos 0 +#define reg_ce_bias_7_0_len 8 +#define reg_ce_bias_7_0_lsb 0 +#define r_reg_ce_bias_11_8 0xFD39 +#define reg_ce_bias_11_8_pos 0 +#define reg_ce_bias_11_8_len 4 +#define reg_ce_bias_11_8_lsb 8 +#define r_reg_ce_m1_7_0 0xFD3A +#define reg_ce_m1_7_0_pos 0 +#define reg_ce_m1_7_0_len 8 +#define reg_ce_m1_7_0_lsb 0 +#define r_reg_ce_m1_11_8 0xFD3B +#define reg_ce_m1_11_8_pos 0 +#define reg_ce_m1_11_8_len 4 +#define reg_ce_m1_11_8_lsb 8 +#define r_reg_ce_rh0_7_0 0xFD3C +#define reg_ce_rh0_7_0_pos 0 +#define reg_ce_rh0_7_0_len 8 +#define reg_ce_rh0_7_0_lsb 0 +#define r_reg_ce_rh0_15_8 0xFD3D +#define reg_ce_rh0_15_8_pos 0 +#define reg_ce_rh0_15_8_len 8 +#define reg_ce_rh0_15_8_lsb 8 +#define r_reg_ce_rh0_23_16 0xFD3E +#define reg_ce_rh0_23_16_pos 0 +#define reg_ce_rh0_23_16_len 8 +#define reg_ce_rh0_23_16_lsb 16 +#define r_reg_ce_rh0_31_24 0xFD3F +#define reg_ce_rh0_31_24_pos 0 +#define reg_ce_rh0_31_24_len 8 +#define reg_ce_rh0_31_24_lsb 24 +#define p_reg_ce_tdi_delta 0xFD40 +#define reg_ce_tdi_delta_pos 0 +#define reg_ce_tdi_delta_len 3 +#define reg_ce_tdi_delta_lsb 0 +#define p_reg_ce_fdi_delta 0xFD41 +#define reg_ce_fdi_delta_pos 0 +#define reg_ce_fdi_delta_len 3 +#define reg_ce_fdi_delta_lsb 0 +#define p_reg_ce_fste_delta 0xFD42 +#define reg_ce_fste_delta_pos 0 +#define reg_ce_fste_delta_len 3 +#define reg_ce_fste_delta_lsb 0 +#define r_reg_ce_fft_s1 0xFD43 +#define reg_ce_fft_s1_pos 0 +#define reg_ce_fft_s1_len 4 +#define reg_ce_fft_s1_lsb 0 +#define r_reg_feq_fix_eh2_7_0 0xFD44 +#define reg_feq_fix_eh2_7_0_pos 0 +#define reg_feq_fix_eh2_7_0_len 8 +#define reg_feq_fix_eh2_7_0_lsb 0 +#define r_reg_feq_fix_eh2_15_8 0xFD45 +#define reg_feq_fix_eh2_15_8_pos 0 +#define reg_feq_fix_eh2_15_8_len 8 +#define reg_feq_fix_eh2_15_8_lsb 8 +#define r_reg_feq_fix_eh2_23_16 0xFD46 +#define reg_feq_fix_eh2_23_16_pos 0 +#define reg_feq_fix_eh2_23_16_len 8 +#define reg_feq_fix_eh2_23_16_lsb 16 +#define r_reg_feq_fix_eh2_31_24 0xFD47 +#define reg_feq_fix_eh2_31_24_pos 0 +#define reg_feq_fix_eh2_31_24_len 8 +#define reg_feq_fix_eh2_31_24_lsb 24 +#define r_reg_ce_m2_central_7_0 0xFD48 +#define reg_ce_m2_central_7_0_pos 0 +#define reg_ce_m2_central_7_0_len 8 +#define reg_ce_m2_central_7_0_lsb 0 +#define r_reg_ce_m2_central_15_8 0xFD49 +#define reg_ce_m2_central_15_8_pos 0 +#define reg_ce_m2_central_15_8_len 8 +#define reg_ce_m2_central_15_8_lsb 8 +#define r_reg_ce_sigma2_7_0 0xFD4A +#define reg_ce_sigma2_7_0_pos 0 +#define reg_ce_sigma2_7_0_len 8 +#define reg_ce_sigma2_7_0_lsb 0 +#define r_reg_ce_sigma2_15_8 0xFD4B +#define reg_ce_sigma2_15_8_pos 0 +#define reg_ce_sigma2_15_8_len 8 +#define reg_ce_sigma2_15_8_lsb 8 +#define r_reg_ce_sigma2_19_16 0xFD4C +#define reg_ce_sigma2_19_16_pos 0 +#define reg_ce_sigma2_19_16_len 4 +#define reg_ce_sigma2_19_16_lsb 16 +#define r_reg_ce_data_im_7_0 0xFD4D +#define reg_ce_data_im_7_0_pos 0 +#define reg_ce_data_im_7_0_len 8 +#define reg_ce_data_im_7_0_lsb 0 +#define r_reg_ce_data_im_14_8 0xFD4E +#define reg_ce_data_im_14_8_pos 0 +#define reg_ce_data_im_14_8_len 7 +#define reg_ce_data_im_14_8_lsb 8 +#define r_reg_ce_data_re_7_0 0xFD4F +#define reg_ce_data_re_7_0_pos 0 +#define reg_ce_data_re_7_0_len 8 +#define reg_ce_data_re_7_0_lsb 0 +#define r_reg_ce_data_re_14_8 0xFD50 +#define reg_ce_data_re_14_8_pos 0 +#define reg_ce_data_re_14_8_len 7 +#define reg_ce_data_re_14_8_lsb 8 +#define p_reg_ce_var_default_value 0xFD51 +#define reg_ce_var_default_value_pos 0 +#define reg_ce_var_default_value_len 3 +#define reg_ce_var_default_value_lsb 0 +#define p_reg_ce_cent_default_value_7_0 0xFD52 +#define reg_ce_cent_default_value_7_0_pos 0 +#define reg_ce_cent_default_value_7_0_len 8 +#define reg_ce_cent_default_value_7_0_lsb 0 +#define p_reg_ce_cent_default_value_11_8 0xFD53 +#define reg_ce_cent_default_value_11_8_pos 0 +#define reg_ce_cent_default_value_11_8_len 4 +#define reg_ce_cent_default_value_11_8_lsb 8 +#define r_reg_ce_var_hw 0xFD54 +#define reg_ce_var_hw_pos 0 +#define reg_ce_var_hw_len 3 +#define reg_ce_var_hw_lsb 0 +#define r_reg_ce_cent_hw_7_0 0xFD55 +#define reg_ce_cent_hw_7_0_pos 0 +#define reg_ce_cent_hw_7_0_len 8 +#define reg_ce_cent_hw_7_0_lsb 0 +#define r_reg_ce_cent_hw_11_8 0xFD56 +#define reg_ce_cent_hw_11_8_pos 0 +#define reg_ce_cent_hw_11_8_len 4 +#define reg_ce_cent_hw_11_8_lsb 8 +#define p_reg_ce_fdi_cp_test_en 0xFD57 +#define reg_ce_fdi_cp_test_en_pos 0 +#define reg_ce_fdi_cp_test_en_len 1 +#define reg_ce_fdi_cp_test_en_lsb 0 +#define p_reg_ce_cptestindex0_7_0 0xFD58 +#define reg_ce_cptestindex0_7_0_pos 0 +#define reg_ce_cptestindex0_7_0_len 8 +#define reg_ce_cptestindex0_7_0_lsb 0 +#define p_reg_ce_cptestindex0_12_8 0xFD59 +#define reg_ce_cptestindex0_12_8_pos 0 +#define reg_ce_cptestindex0_12_8_len 5 +#define reg_ce_cptestindex0_12_8_lsb 8 +#define p_reg_ce_cptestfdi0 0xFD5A +#define reg_ce_cptestfdi0_pos 0 +#define reg_ce_cptestfdi0_len 3 +#define reg_ce_cptestfdi0_lsb 0 +#define p_reg_ce_cptestindex1_7_0 0xFD5B +#define reg_ce_cptestindex1_7_0_pos 0 +#define reg_ce_cptestindex1_7_0_len 8 +#define reg_ce_cptestindex1_7_0_lsb 0 +#define p_reg_ce_cptestindex1_12_8 0xFD5C +#define reg_ce_cptestindex1_12_8_pos 0 +#define reg_ce_cptestindex1_12_8_len 5 +#define reg_ce_cptestindex1_12_8_lsb 8 +#define p_reg_ce_cptestfdi1 0xFD5D +#define reg_ce_cptestfdi1_pos 0 +#define reg_ce_cptestfdi1_len 3 +#define reg_ce_cptestfdi1_lsb 0 +#define p_reg_ce_cptestindex2_7_0 0xFD5E +#define reg_ce_cptestindex2_7_0_pos 0 +#define reg_ce_cptestindex2_7_0_len 8 +#define reg_ce_cptestindex2_7_0_lsb 0 +#define p_reg_ce_cptestindex2_12_8 0xFD5F +#define reg_ce_cptestindex2_12_8_pos 0 +#define reg_ce_cptestindex2_12_8_len 5 +#define reg_ce_cptestindex2_12_8_lsb 8 +#define p_reg_ce_cptestfdi2 0xFD60 +#define reg_ce_cptestfdi2_pos 0 +#define reg_ce_cptestfdi2_len 3 +#define reg_ce_cptestfdi2_lsb 0 +#define p_reg_ce_cptestindex3_7_0 0xFD61 +#define reg_ce_cptestindex3_7_0_pos 0 +#define reg_ce_cptestindex3_7_0_len 8 +#define reg_ce_cptestindex3_7_0_lsb 0 +#define p_reg_ce_cptestindex3_12_8 0xFD62 +#define reg_ce_cptestindex3_12_8_pos 0 +#define reg_ce_cptestindex3_12_8_len 5 +#define reg_ce_cptestindex3_12_8_lsb 8 +#define p_reg_ce_cptestfdi3 0xFD63 +#define reg_ce_cptestfdi3_pos 0 +#define reg_ce_cptestfdi3_len 3 +#define reg_ce_cptestfdi3_lsb 0 +#define p_reg_ce_cptestindex4_7_0 0xFD64 +#define reg_ce_cptestindex4_7_0_pos 0 +#define reg_ce_cptestindex4_7_0_len 8 +#define reg_ce_cptestindex4_7_0_lsb 0 +#define p_reg_ce_cptestindex4_12_8 0xFD65 +#define reg_ce_cptestindex4_12_8_pos 0 +#define reg_ce_cptestindex4_12_8_len 5 +#define reg_ce_cptestindex4_12_8_lsb 8 +#define p_reg_ce_cptestfdi4 0xFD66 +#define reg_ce_cptestfdi4_pos 0 +#define reg_ce_cptestfdi4_len 3 +#define reg_ce_cptestfdi4_lsb 0 +#define p_reg_ce_cptestindex5_7_0 0xFD67 +#define reg_ce_cptestindex5_7_0_pos 0 +#define reg_ce_cptestindex5_7_0_len 8 +#define reg_ce_cptestindex5_7_0_lsb 0 +#define p_reg_ce_cptestindex5_12_8 0xFD68 +#define reg_ce_cptestindex5_12_8_pos 0 +#define reg_ce_cptestindex5_12_8_len 5 +#define reg_ce_cptestindex5_12_8_lsb 8 +#define p_reg_ce_cptestfdi5 0xFD69 +#define reg_ce_cptestfdi5_pos 0 +#define reg_ce_cptestfdi5_len 3 +#define reg_ce_cptestfdi5_lsb 0 +#define p_reg_ce_cptestindex6_7_0 0xFD6A +#define reg_ce_cptestindex6_7_0_pos 0 +#define reg_ce_cptestindex6_7_0_len 8 +#define reg_ce_cptestindex6_7_0_lsb 0 +#define p_reg_ce_cptestindex6_12_8 0xFD6B +#define reg_ce_cptestindex6_12_8_pos 0 +#define reg_ce_cptestindex6_12_8_len 5 +#define reg_ce_cptestindex6_12_8_lsb 8 +#define p_reg_ce_cptestfdi6 0xFD6C +#define reg_ce_cptestfdi6_pos 0 +#define reg_ce_cptestfdi6_len 3 +#define reg_ce_cptestfdi6_lsb 0 +#define p_reg_ce_cptestindex7_7_0 0xFD6D +#define reg_ce_cptestindex7_7_0_pos 0 +#define reg_ce_cptestindex7_7_0_len 8 +#define reg_ce_cptestindex7_7_0_lsb 0 +#define p_reg_ce_cptestindex7_12_8 0xFD6E +#define reg_ce_cptestindex7_12_8_pos 0 +#define reg_ce_cptestindex7_12_8_len 5 +#define reg_ce_cptestindex7_12_8_lsb 8 +#define p_reg_ce_cptestfdi7 0xFD6F +#define reg_ce_cptestfdi7_pos 0 +#define reg_ce_cptestfdi7_len 3 +#define reg_ce_cptestfdi7_lsb 0 +#define p_reg_ce_cp_replace_tdiout_en 0xFD74 +#define reg_ce_cp_replace_tdiout_en_pos 0 +#define reg_ce_cp_replace_tdiout_en_len 1 +#define reg_ce_cp_replace_tdiout_en_lsb 0 +#define p_reg_ce_tdi_mask0_en 0xFD7D +#define reg_ce_tdi_mask0_en_pos 0 +#define reg_ce_tdi_mask0_en_len 1 +#define reg_ce_tdi_mask0_en_lsb 0 +#define p_reg_ce_tdi_mask_from0_7_0 0xFD7E +#define reg_ce_tdi_mask_from0_7_0_pos 0 +#define reg_ce_tdi_mask_from0_7_0_len 8 +#define reg_ce_tdi_mask_from0_7_0_lsb 0 +#define p_reg_ce_tdi_mask_from0_12_8 0xFD7F +#define reg_ce_tdi_mask_from0_12_8_pos 0 +#define reg_ce_tdi_mask_from0_12_8_len 5 +#define reg_ce_tdi_mask_from0_12_8_lsb 8 +#define p_reg_ce_tdi_mask_to0_7_0 0xFD80 +#define reg_ce_tdi_mask_to0_7_0_pos 0 +#define reg_ce_tdi_mask_to0_7_0_len 8 +#define reg_ce_tdi_mask_to0_7_0_lsb 0 +#define p_reg_ce_tdi_mask_to0_12_8 0xFD81 +#define reg_ce_tdi_mask_to0_12_8_pos 0 +#define reg_ce_tdi_mask_to0_12_8_len 5 +#define reg_ce_tdi_mask_to0_12_8_lsb 8 +#define p_reg_ce_tdi_mask1_en 0xFD82 +#define reg_ce_tdi_mask1_en_pos 0 +#define reg_ce_tdi_mask1_en_len 1 +#define reg_ce_tdi_mask1_en_lsb 0 +#define p_reg_ce_tdi_mask_from1_7_0 0xFD83 +#define reg_ce_tdi_mask_from1_7_0_pos 0 +#define reg_ce_tdi_mask_from1_7_0_len 8 +#define reg_ce_tdi_mask_from1_7_0_lsb 0 +#define p_reg_ce_tdi_mask_from1_12_8 0xFD84 +#define reg_ce_tdi_mask_from1_12_8_pos 0 +#define reg_ce_tdi_mask_from1_12_8_len 5 +#define reg_ce_tdi_mask_from1_12_8_lsb 8 +#define p_reg_ce_tdi_mask_to1_7_0 0xFD85 +#define reg_ce_tdi_mask_to1_7_0_pos 0 +#define reg_ce_tdi_mask_to1_7_0_len 8 +#define reg_ce_tdi_mask_to1_7_0_lsb 0 +#define p_reg_ce_tdi_mask_to1_12_8 0xFD86 +#define reg_ce_tdi_mask_to1_12_8_pos 0 +#define reg_ce_tdi_mask_to1_12_8_len 5 +#define reg_ce_tdi_mask_to1_12_8_lsb 8 +#define p_reg_ce_2nd_var_max 0xFD87 +#define reg_ce_2nd_var_max_pos 0 +#define reg_ce_2nd_var_max_len 3 +#define reg_ce_2nd_var_max_lsb 0 +#define p_reg_ce_2nd_cent_forced_en 0xFD88 +#define reg_ce_2nd_cent_forced_en_pos 0 +#define reg_ce_2nd_cent_forced_en_len 1 +#define reg_ce_2nd_cent_forced_en_lsb 0 +#define p_reg_ce_2nd_var_forced_en 0xFD89 +#define reg_ce_2nd_var_forced_en_pos 0 +#define reg_ce_2nd_var_forced_en_len 1 +#define reg_ce_2nd_var_forced_en_lsb 0 +#define p_reg_ce_2nd_fctrl_auto_reset_en 0xFD8A +#define reg_ce_2nd_fctrl_auto_reset_en_pos 0 +#define reg_ce_2nd_fctrl_auto_reset_en_len 1 +#define reg_ce_2nd_fctrl_auto_reset_en_lsb 0 +#define p_reg_ce_2nd_cent_auto_clr_en 0xFD8B +#define reg_ce_2nd_cent_auto_clr_en_pos 0 +#define reg_ce_2nd_cent_auto_clr_en_len 1 +#define reg_ce_2nd_cent_auto_clr_en_lsb 0 +#define p_reg_ce_2nd_cent_forced_value_7_0 0xFD8C +#define reg_ce_2nd_cent_forced_value_7_0_pos 0 +#define reg_ce_2nd_cent_forced_value_7_0_len 8 +#define reg_ce_2nd_cent_forced_value_7_0_lsb 0 +#define p_reg_ce_2nd_cent_forced_value_11_8 0xFD8D +#define reg_ce_2nd_cent_forced_value_11_8_pos 0 +#define reg_ce_2nd_cent_forced_value_11_8_len 4 +#define reg_ce_2nd_cent_forced_value_11_8_lsb 8 +#define p_reg_ce_2nd_cent_auto_clr_value_7_0 0xFD8E +#define reg_ce_2nd_cent_auto_clr_value_7_0_pos 0 +#define reg_ce_2nd_cent_auto_clr_value_7_0_len 8 +#define reg_ce_2nd_cent_auto_clr_value_7_0_lsb 0 +#define p_reg_ce_2nd_cent_auto_clr_value_11_8 0xFD8F +#define reg_ce_2nd_cent_auto_clr_value_11_8_pos 0 +#define reg_ce_2nd_cent_auto_clr_value_11_8_len 4 +#define reg_ce_2nd_cent_auto_clr_value_11_8_lsb 8 +#define p_reg_ce_gs_s1_var 0xFD90 +#define reg_ce_gs_s1_var_pos 0 +#define reg_ce_gs_s1_var_len 4 +#define reg_ce_gs_s1_var_lsb 0 +#define p_reg_ce_2nd_centroid_max_7_0 0xFD91 +#define reg_ce_2nd_centroid_max_7_0_pos 0 +#define reg_ce_2nd_centroid_max_7_0_len 8 +#define reg_ce_2nd_centroid_max_7_0_lsb 0 +#define p_reg_ce_2nd_centroid_max_11_8 0xFD92 +#define reg_ce_2nd_centroid_max_11_8_pos 0 +#define reg_ce_2nd_centroid_max_11_8_len 4 +#define reg_ce_2nd_centroid_max_11_8_lsb 8 +#define r_reg_ce_2nd_centroid_out_7_0 0xFD93 +#define reg_ce_2nd_centroid_out_7_0_pos 0 +#define reg_ce_2nd_centroid_out_7_0_len 8 +#define reg_ce_2nd_centroid_out_7_0_lsb 0 +#define r_reg_ce_2nd_centroid_out_11_8 0xFD94 +#define reg_ce_2nd_centroid_out_11_8_pos 0 +#define reg_ce_2nd_centroid_out_11_8_len 4 +#define reg_ce_2nd_centroid_out_11_8_lsb 8 +#define r_reg_ce_2nd_fctrl_rdy 0xFD95 +#define reg_ce_2nd_fctrl_rdy_pos 0 +#define reg_ce_2nd_fctrl_rdy_len 1 +#define reg_ce_2nd_fctrl_rdy_lsb 0 +#define r_reg_ce_2nd_var 0xFD96 +#define reg_ce_2nd_var_pos 0 +#define reg_ce_2nd_var_len 3 +#define reg_ce_2nd_var_lsb 0 +#define r_reg_ce_2nd_bias_7_0 0xFD97 +#define reg_ce_2nd_bias_7_0_pos 0 +#define reg_ce_2nd_bias_7_0_len 8 +#define reg_ce_2nd_bias_7_0_lsb 0 +#define r_reg_ce_2nd_bias_11_8 0xFD98 +#define reg_ce_2nd_bias_11_8_pos 0 +#define reg_ce_2nd_bias_11_8_len 4 +#define reg_ce_2nd_bias_11_8_lsb 8 +#define r_reg_ce_2nd_m1_7_0 0xFD99 +#define reg_ce_2nd_m1_7_0_pos 0 +#define reg_ce_2nd_m1_7_0_len 8 +#define reg_ce_2nd_m1_7_0_lsb 0 +#define r_reg_ce_2nd_m1_11_8 0xFD9A +#define reg_ce_2nd_m1_11_8_pos 0 +#define reg_ce_2nd_m1_11_8_len 4 +#define reg_ce_2nd_m1_11_8_lsb 8 +#define p_reg_ce_2nd_var_forced_value 0xFD9B +#define reg_ce_2nd_var_forced_value_pos 0 +#define reg_ce_2nd_var_forced_value_len 3 +#define reg_ce_2nd_var_forced_value_lsb 0 +#define r_reg_ce_2nd_m2_central_7_0 0xFD9C +#define reg_ce_2nd_m2_central_7_0_pos 0 +#define reg_ce_2nd_m2_central_7_0_len 8 +#define reg_ce_2nd_m2_central_7_0_lsb 0 +#define r_reg_ce_2nd_m2_central_15_8 0xFD9D +#define reg_ce_2nd_m2_central_15_8_pos 0 +#define reg_ce_2nd_m2_central_15_8_len 8 +#define reg_ce_2nd_m2_central_15_8_lsb 8 +#define p_reg_ce_2nd_var_default_value 0xFD9E +#define reg_ce_2nd_var_default_value_pos 0 +#define reg_ce_2nd_var_default_value_len 3 +#define reg_ce_2nd_var_default_value_lsb 0 +#define p_reg_ce_2nd_cent_default_value_7_0 0xFD9F +#define reg_ce_2nd_cent_default_value_7_0_pos 0 +#define reg_ce_2nd_cent_default_value_7_0_len 8 +#define reg_ce_2nd_cent_default_value_7_0_lsb 0 +#define p_reg_ce_2nd_cent_default_value_11_8 0xFDA0 +#define reg_ce_2nd_cent_default_value_11_8_pos 0 +#define reg_ce_2nd_cent_default_value_11_8_len 4 +#define reg_ce_2nd_cent_default_value_11_8_lsb 8 +#define p_reg_ce_use_fdi_long 0xFDA1 +#define reg_ce_use_fdi_long_pos 0 +#define reg_ce_use_fdi_long_len 1 +#define reg_ce_use_fdi_long_lsb 0 +#define p_reg_p_ce_tdi_lms_en 0xFDA2 +#define reg_p_ce_tdi_lms_en_pos 0 +#define reg_p_ce_tdi_lms_en_len 1 +#define reg_p_ce_tdi_lms_en_lsb 0 +#define p_reg_p_ce_tdi_lms_bufshift 0xFDA3 +#define reg_p_ce_tdi_lms_bufshift_pos 0 +#define reg_p_ce_tdi_lms_bufshift_len 2 +#define reg_p_ce_tdi_lms_bufshift_lsb 0 +#define p_reg_p_ce_tdi_lms_ave_ratio 0xFDA4 +#define reg_p_ce_tdi_lms_ave_ratio_pos 0 +#define reg_p_ce_tdi_lms_ave_ratio_len 5 +#define reg_p_ce_tdi_lms_ave_ratio_lsb 0 +#define p_reg_p_ce_conf2_in_con0_en 0xFDA5 +#define reg_p_ce_conf2_in_con0_en_pos 0 +#define reg_p_ce_conf2_in_con0_en_len 1 +#define reg_p_ce_conf2_in_con0_en_lsb 0 +#define p_fec_rsd_packet_unit_7_0 0xF700 +#define fec_rsd_packet_unit_7_0_pos 0 +#define fec_rsd_packet_unit_7_0_len 8 +#define fec_rsd_packet_unit_7_0_lsb 0 +#define p_fec_rsd_packet_unit_15_8 0xF701 +#define fec_rsd_packet_unit_15_8_pos 0 +#define fec_rsd_packet_unit_15_8_len 8 +#define fec_rsd_packet_unit_15_8_lsb 8 +#define r_reg_rsd_bit_err_cnt_7_0 0xF702 +#define reg_rsd_bit_err_cnt_7_0_pos 0 +#define reg_rsd_bit_err_cnt_7_0_len 8 +#define reg_rsd_bit_err_cnt_7_0_lsb 0 +#define r_reg_rsd_bit_err_cnt_15_8 0xF703 +#define reg_rsd_bit_err_cnt_15_8_pos 0 +#define reg_rsd_bit_err_cnt_15_8_len 8 +#define reg_rsd_bit_err_cnt_15_8_lsb 8 +#define r_reg_rsd_bit_err_cnt_23_16 0xF704 +#define reg_rsd_bit_err_cnt_23_16_pos 0 +#define reg_rsd_bit_err_cnt_23_16_len 8 +#define reg_rsd_bit_err_cnt_23_16_lsb 16 +#define r_reg_rsd_abort_packet_cnt_7_0 0xF705 +#define reg_rsd_abort_packet_cnt_7_0_pos 0 +#define reg_rsd_abort_packet_cnt_7_0_len 8 +#define reg_rsd_abort_packet_cnt_7_0_lsb 0 +#define r_reg_rsd_abort_packet_cnt_15_8 0xF706 +#define reg_rsd_abort_packet_cnt_15_8_pos 0 +#define reg_rsd_abort_packet_cnt_15_8_len 8 +#define reg_rsd_abort_packet_cnt_15_8_lsb 8 +#define p_fec_RSD_PKT_NUM_PER_UNIT_7_0 0xF707 +#define fec_RSD_PKT_NUM_PER_UNIT_7_0_pos 0 +#define fec_RSD_PKT_NUM_PER_UNIT_7_0_len 8 +#define fec_RSD_PKT_NUM_PER_UNIT_7_0_lsb 0 +#define p_fec_RSD_PKT_NUM_PER_UNIT_15_8 0xF708 +#define fec_RSD_PKT_NUM_PER_UNIT_15_8_pos 0 +#define fec_RSD_PKT_NUM_PER_UNIT_15_8_len 8 +#define fec_RSD_PKT_NUM_PER_UNIT_15_8_lsb 8 +#define p_fec_RS_TH_1_7_0 0xF709 +#define fec_RS_TH_1_7_0_pos 0 +#define fec_RS_TH_1_7_0_len 8 +#define fec_RS_TH_1_7_0_lsb 0 +#define p_fec_RS_TH_1_15_8 0xF70A +#define fec_RS_TH_1_15_8_pos 0 +#define fec_RS_TH_1_15_8_len 8 +#define fec_RS_TH_1_15_8_lsb 8 +#define p_fec_RS_TH_2 0xF70B +#define fec_RS_TH_2_pos 0 +#define fec_RS_TH_2_len 8 +#define fec_RS_TH_2_lsb 0 +#define p_fec_rsd_ber_rst 0xF70C +#define fec_rsd_ber_rst_pos 0 +#define fec_rsd_ber_rst_len 1 +#define fec_rsd_ber_rst_lsb 0 +#define p_reg_rsd_ber_rdy 0xF70D +#define reg_rsd_ber_rdy_pos 0 +#define reg_rsd_ber_rdy_len 1 +#define reg_rsd_ber_rdy_lsb 0 +#define p_reg_rsd_trigger_retrain 0xF70E +#define reg_rsd_trigger_retrain_pos 0 +#define reg_rsd_trigger_retrain_len 1 +#define reg_rsd_trigger_retrain_lsb 0 +#define p_reg_sync_recover 0xF70F +#define reg_sync_recover_pos 0 +#define reg_sync_recover_len 1 +#define reg_sync_recover_lsb 0 +#define p_fec_crc_en 0xF710 +#define fec_crc_en_pos 0 +#define fec_crc_en_len 1 +#define fec_crc_en_lsb 0 +#define p_fec_mon_en 0xF711 +#define fec_mon_en_pos 0 +#define fec_mon_en_len 1 +#define fec_mon_en_lsb 0 +#define p_reg_sync_chk 0xF712 +#define reg_sync_chk_pos 0 +#define reg_sync_chk_len 1 +#define reg_sync_chk_lsb 0 +#define p_fec_dummy_reg_2 0xF713 +#define fec_dummy_reg_2_pos 0 +#define fec_dummy_reg_2_len 3 +#define fec_dummy_reg_2_lsb 0 +#define p_reg_fec_data_en 0xF714 +#define reg_fec_data_en_pos 0 +#define reg_fec_data_en_len 1 +#define reg_fec_data_en_lsb 0 +#define p_fec_vtb_rsd_mon_en 0xF715 +#define fec_vtb_rsd_mon_en_pos 0 +#define fec_vtb_rsd_mon_en_len 1 +#define fec_vtb_rsd_mon_en_lsb 0 +#define p_reg_fec_sw_rst 0xF716 +#define reg_fec_sw_rst_pos 0 +#define reg_fec_sw_rst_len 1 +#define reg_fec_sw_rst_lsb 0 +#define r_fec_vtb_pm_crc 0xF717 +#define fec_vtb_pm_crc_pos 0 +#define fec_vtb_pm_crc_len 8 +#define fec_vtb_pm_crc_lsb 0 +#define r_fec_vtb_tb_7_crc 0xF718 +#define fec_vtb_tb_7_crc_pos 0 +#define fec_vtb_tb_7_crc_len 8 +#define fec_vtb_tb_7_crc_lsb 0 +#define r_fec_vtb_tb_6_crc 0xF719 +#define fec_vtb_tb_6_crc_pos 0 +#define fec_vtb_tb_6_crc_len 8 +#define fec_vtb_tb_6_crc_lsb 0 +#define r_fec_vtb_tb_5_crc 0xF71A +#define fec_vtb_tb_5_crc_pos 0 +#define fec_vtb_tb_5_crc_len 8 +#define fec_vtb_tb_5_crc_lsb 0 +#define r_fec_vtb_tb_4_crc 0xF71B +#define fec_vtb_tb_4_crc_pos 0 +#define fec_vtb_tb_4_crc_len 8 +#define fec_vtb_tb_4_crc_lsb 0 +#define r_fec_vtb_tb_3_crc 0xF71C +#define fec_vtb_tb_3_crc_pos 0 +#define fec_vtb_tb_3_crc_len 8 +#define fec_vtb_tb_3_crc_lsb 0 +#define r_fec_vtb_tb_2_crc 0xF71D +#define fec_vtb_tb_2_crc_pos 0 +#define fec_vtb_tb_2_crc_len 8 +#define fec_vtb_tb_2_crc_lsb 0 +#define r_fec_vtb_tb_1_crc 0xF71E +#define fec_vtb_tb_1_crc_pos 0 +#define fec_vtb_tb_1_crc_len 8 +#define fec_vtb_tb_1_crc_lsb 0 +#define r_fec_vtb_tb_0_crc 0xF71F +#define fec_vtb_tb_0_crc_pos 0 +#define fec_vtb_tb_0_crc_len 8 +#define fec_vtb_tb_0_crc_lsb 0 +#define r_fec_rsd_bank0_crc 0xF720 +#define fec_rsd_bank0_crc_pos 0 +#define fec_rsd_bank0_crc_len 8 +#define fec_rsd_bank0_crc_lsb 0 +#define r_fec_rsd_bank1_crc 0xF721 +#define fec_rsd_bank1_crc_pos 0 +#define fec_rsd_bank1_crc_len 8 +#define fec_rsd_bank1_crc_lsb 0 +#define r_fec_idi_vtb_crc 0xF722 +#define fec_idi_vtb_crc_pos 0 +#define fec_idi_vtb_crc_len 8 +#define fec_idi_vtb_crc_lsb 0 +#define p_reg_fec_rsd_packet_unit_exp 0xF723 +#define reg_fec_rsd_packet_unit_exp_pos 0 +#define reg_fec_rsd_packet_unit_exp_len 4 +#define reg_fec_rsd_packet_unit_exp_lsb 0 +#define p_reg_rsd_bit_err_exp_rdy 0xF724 +#define reg_rsd_bit_err_exp_rdy_pos 0 +#define reg_rsd_bit_err_exp_rdy_len 1 +#define reg_rsd_bit_err_exp_rdy_lsb 0 +#define r_reg_rsd_bit_err_exp 0xF725 +#define reg_rsd_bit_err_exp_pos 0 +#define reg_rsd_bit_err_exp_len 5 +#define reg_rsd_bit_err_exp_lsb 0 +#define p_fec_rsd_packet_unit1_7_0 0xF726 +#define fec_rsd_packet_unit1_7_0_pos 0 +#define fec_rsd_packet_unit1_7_0_len 8 +#define fec_rsd_packet_unit1_7_0_lsb 0 +#define p_fec_rsd_packet_unit1_15_8 0xF727 +#define fec_rsd_packet_unit1_15_8_pos 0 +#define fec_rsd_packet_unit1_15_8_len 8 +#define fec_rsd_packet_unit1_15_8_lsb 8 +#define r_reg_rsd_bit_err_cnt1_7_0 0xF728 +#define reg_rsd_bit_err_cnt1_7_0_pos 0 +#define reg_rsd_bit_err_cnt1_7_0_len 8 +#define reg_rsd_bit_err_cnt1_7_0_lsb 0 +#define r_reg_rsd_bit_err_cnt1_15_8 0xF729 +#define reg_rsd_bit_err_cnt1_15_8_pos 0 +#define reg_rsd_bit_err_cnt1_15_8_len 8 +#define reg_rsd_bit_err_cnt1_15_8_lsb 8 +#define r_reg_rsd_bit_err_cnt1_23_16 0xF72A +#define reg_rsd_bit_err_cnt1_23_16_pos 0 +#define reg_rsd_bit_err_cnt1_23_16_len 8 +#define reg_rsd_bit_err_cnt1_23_16_lsb 16 +#define r_reg_rsd_abort_packet_cnt1_7_0 0xF72B +#define reg_rsd_abort_packet_cnt1_7_0_pos 0 +#define reg_rsd_abort_packet_cnt1_7_0_len 8 +#define reg_rsd_abort_packet_cnt1_7_0_lsb 0 +#define r_reg_rsd_abort_packet_cnt1_15_8 0xF72C +#define reg_rsd_abort_packet_cnt1_15_8_pos 0 +#define reg_rsd_abort_packet_cnt1_15_8_len 8 +#define reg_rsd_abort_packet_cnt1_15_8_lsb 8 +#define p_fec_rsd_ber_rst1 0xF72D +#define fec_rsd_ber_rst1_pos 0 +#define fec_rsd_ber_rst1_len 1 +#define fec_rsd_ber_rst1_lsb 0 +#define p_reg_rsd_ber_rdy1 0xF72E +#define reg_rsd_ber_rdy1_pos 0 +#define reg_rsd_ber_rdy1_len 1 +#define reg_rsd_ber_rdy1_lsb 0 +#define p_reg_dca_txmod_sel 0xF72F +#define reg_dca_txmod_sel_pos 0 +#define reg_dca_txmod_sel_len 1 +#define reg_dca_txmod_sel_lsb 0 +#define p_reg_dca_platch 0xF730 +#define reg_dca_platch_pos 0 +#define reg_dca_platch_len 1 +#define reg_dca_platch_lsb 0 +#define p_reg_dca_upper_chip 0xF731 +#define reg_dca_upper_chip_pos 0 +#define reg_dca_upper_chip_len 1 +#define reg_dca_upper_chip_lsb 0 +#define p_reg_dca_lower_chip 0xF732 +#define reg_dca_lower_chip_pos 0 +#define reg_dca_lower_chip_len 1 +#define reg_dca_lower_chip_lsb 0 +#define p_reg_dca_enl 0xF733 +#define reg_dca_enl_pos 0 +#define reg_dca_enl_len 1 +#define reg_dca_enl_lsb 0 +#define p_reg_dca_enu 0xF734 +#define reg_dca_enu_pos 0 +#define reg_dca_enu_len 1 +#define reg_dca_enu_lsb 0 +#define p_reg_dca_th 0xF735 +#define reg_dca_th_pos 0 +#define reg_dca_th_len 5 +#define reg_dca_th_lsb 0 +#define p_reg_dca_scale 0xF736 +#define reg_dca_scale_pos 0 +#define reg_dca_scale_len 4 +#define reg_dca_scale_lsb 0 +#define p_reg_dca_tone_7_0 0xF737 +#define reg_dca_tone_7_0_pos 0 +#define reg_dca_tone_7_0_len 8 +#define reg_dca_tone_7_0_lsb 0 +#define p_reg_dca_tone_12_8 0xF738 +#define reg_dca_tone_12_8_pos 0 +#define reg_dca_tone_12_8_len 5 +#define reg_dca_tone_12_8_lsb 8 +#define p_reg_dca_time_7_0 0xF739 +#define reg_dca_time_7_0_pos 0 +#define reg_dca_time_7_0_len 8 +#define reg_dca_time_7_0_lsb 0 +#define p_reg_dca_time_15_8 0xF73A +#define reg_dca_time_15_8_pos 0 +#define reg_dca_time_15_8_len 8 +#define reg_dca_time_15_8_lsb 8 +#define r_fec_dcasm 0xF73B +#define fec_dcasm_pos 0 +#define fec_dcasm_len 3 +#define fec_dcasm_lsb 0 +#define p_reg_dca_stand_alone 0xF73C +#define reg_dca_stand_alone_pos 0 +#define reg_dca_stand_alone_len 1 +#define reg_dca_stand_alone_lsb 0 +#define p_reg_dca_upper_out_en 0xF73D +#define reg_dca_upper_out_en_pos 0 +#define reg_dca_upper_out_en_len 1 +#define reg_dca_upper_out_en_lsb 0 +#define p_reg_dca_rc_en 0xF73E +#define reg_dca_rc_en_pos 0 +#define reg_dca_rc_en_len 1 +#define reg_dca_rc_en_lsb 0 +#define p_reg_dca_retrain_send 0xF73F +#define reg_dca_retrain_send_pos 0 +#define reg_dca_retrain_send_len 1 +#define reg_dca_retrain_send_lsb 0 +#define p_reg_dca_retrain_rec 0xF740 +#define reg_dca_retrain_rec_pos 0 +#define reg_dca_retrain_rec_len 1 +#define reg_dca_retrain_rec_lsb 0 +#define p_reg_dca_gi_gap 0xF741 +#define reg_dca_gi_gap_pos 0 +#define reg_dca_gi_gap_len 8 +#define reg_dca_gi_gap_lsb 0 +#define r_reg_dca_rec_up_tpsd_txmod 0xF742 +#define reg_dca_rec_up_tpsd_txmod_pos 0 +#define reg_dca_rec_up_tpsd_txmod_len 2 +#define reg_dca_rec_up_tpsd_txmod_lsb 0 +#define r_reg_dca_rec_up_tpsd_const 0xF743 +#define reg_dca_rec_up_tpsd_const_pos 0 +#define reg_dca_rec_up_tpsd_const_len 2 +#define reg_dca_rec_up_tpsd_const_lsb 0 +#define r_reg_dca_rec_up_tpsd_indep 0xF744 +#define reg_dca_rec_up_tpsd_indep_pos 0 +#define reg_dca_rec_up_tpsd_indep_len 1 +#define reg_dca_rec_up_tpsd_indep_lsb 0 +#define r_reg_dca_rec_up_tpsd_hier 0xF745 +#define reg_dca_rec_up_tpsd_hier_pos 0 +#define reg_dca_rec_up_tpsd_hier_len 2 +#define reg_dca_rec_up_tpsd_hier_lsb 0 +#define r_reg_dca_rec_up_tpsd_hpcr 0xF746 +#define reg_dca_rec_up_tpsd_hpcr_pos 0 +#define reg_dca_rec_up_tpsd_hpcr_len 3 +#define reg_dca_rec_up_tpsd_hpcr_lsb 0 +#define r_reg_dca_rec_up_tpsd_lpcr 0xF747 +#define reg_dca_rec_up_tpsd_lpcr_pos 0 +#define reg_dca_rec_up_tpsd_lpcr_len 3 +#define reg_dca_rec_up_tpsd_lpcr_lsb 0 +#define r_reg_dca_rec_up_tpsd_lock 0xF748 +#define reg_dca_rec_up_tpsd_lock_pos 0 +#define reg_dca_rec_up_tpsd_lock_len 1 +#define reg_dca_rec_up_tpsd_lock_lsb 0 +#define r_reg_dca_rec_lo_tpsd_txmod 0xF749 +#define reg_dca_rec_lo_tpsd_txmod_pos 0 +#define reg_dca_rec_lo_tpsd_txmod_len 2 +#define reg_dca_rec_lo_tpsd_txmod_lsb 0 +#define r_reg_dca_rec_lo_tpsd_const 0xF74A +#define reg_dca_rec_lo_tpsd_const_pos 0 +#define reg_dca_rec_lo_tpsd_const_len 2 +#define reg_dca_rec_lo_tpsd_const_lsb 0 +#define r_reg_dca_rec_lo_tpsd_indep 0xF74B +#define reg_dca_rec_lo_tpsd_indep_pos 0 +#define reg_dca_rec_lo_tpsd_indep_len 1 +#define reg_dca_rec_lo_tpsd_indep_lsb 0 +#define r_reg_dca_rec_lo_tpsd_hier 0xF74C +#define reg_dca_rec_lo_tpsd_hier_pos 0 +#define reg_dca_rec_lo_tpsd_hier_len 2 +#define reg_dca_rec_lo_tpsd_hier_lsb 0 +#define r_reg_dca_rec_lo_tpsd_hpcr 0xF74D +#define reg_dca_rec_lo_tpsd_hpcr_pos 0 +#define reg_dca_rec_lo_tpsd_hpcr_len 3 +#define reg_dca_rec_lo_tpsd_hpcr_lsb 0 +#define r_reg_dca_rec_lo_tpsd_lpcr 0xF74E +#define reg_dca_rec_lo_tpsd_lpcr_pos 0 +#define reg_dca_rec_lo_tpsd_lpcr_len 3 +#define reg_dca_rec_lo_tpsd_lpcr_lsb 0 +#define r_reg_dca_rec_lo_tpsd_lock 0xF74F +#define reg_dca_rec_lo_tpsd_lock_pos 0 +#define reg_dca_rec_lo_tpsd_lock_len 1 +#define reg_dca_rec_lo_tpsd_lock_lsb 0 +#define p_reg_dca_gpr_ctr_up_send 0xF750 +#define reg_dca_gpr_ctr_up_send_pos 0 +#define reg_dca_gpr_ctr_up_send_len 8 +#define reg_dca_gpr_ctr_up_send_lsb 0 +#define p_reg_dca_gpr_dat_up_send_0 0xF751 +#define reg_dca_gpr_dat_up_send_0_pos 0 +#define reg_dca_gpr_dat_up_send_0_len 8 +#define reg_dca_gpr_dat_up_send_0_lsb 0 +#define p_reg_dca_gpr_dat_up_send_1 0xF752 +#define reg_dca_gpr_dat_up_send_1_pos 0 +#define reg_dca_gpr_dat_up_send_1_len 8 +#define reg_dca_gpr_dat_up_send_1_lsb 0 +#define p_reg_dca_gpr_dat_up_send_2 0xF753 +#define reg_dca_gpr_dat_up_send_2_pos 0 +#define reg_dca_gpr_dat_up_send_2_len 8 +#define reg_dca_gpr_dat_up_send_2_lsb 0 +#define p_reg_dca_gpr_dat_up_send_3 0xF754 +#define reg_dca_gpr_dat_up_send_3_pos 0 +#define reg_dca_gpr_dat_up_send_3_len 8 +#define reg_dca_gpr_dat_up_send_3_lsb 0 +#define p_reg_dca_gpr_dat_up_send_4 0xF755 +#define reg_dca_gpr_dat_up_send_4_pos 0 +#define reg_dca_gpr_dat_up_send_4_len 8 +#define reg_dca_gpr_dat_up_send_4_lsb 0 +#define p_reg_dca_gpr_dat_up_send_5 0xF756 +#define reg_dca_gpr_dat_up_send_5_pos 0 +#define reg_dca_gpr_dat_up_send_5_len 8 +#define reg_dca_gpr_dat_up_send_5_lsb 0 +#define p_reg_dca_over_wr_up_send 0xF757 +#define reg_dca_over_wr_up_send_pos 0 +#define reg_dca_over_wr_up_send_len 1 +#define reg_dca_over_wr_up_send_lsb 0 +#define p_reg_dca_int_up_send 0xF758 +#define reg_dca_int_up_send_pos 0 +#define reg_dca_int_up_send_len 1 +#define reg_dca_int_up_send_lsb 0 +#define p_reg_dca_gpr_ctr_lo_send 0xF759 +#define reg_dca_gpr_ctr_lo_send_pos 0 +#define reg_dca_gpr_ctr_lo_send_len 8 +#define reg_dca_gpr_ctr_lo_send_lsb 0 +#define p_reg_dca_gpr_dat_lo_send_0 0xF75A +#define reg_dca_gpr_dat_lo_send_0_pos 0 +#define reg_dca_gpr_dat_lo_send_0_len 8 +#define reg_dca_gpr_dat_lo_send_0_lsb 0 +#define p_reg_dca_gpr_dat_lo_send_1 0xF75B +#define reg_dca_gpr_dat_lo_send_1_pos 0 +#define reg_dca_gpr_dat_lo_send_1_len 8 +#define reg_dca_gpr_dat_lo_send_1_lsb 0 +#define p_reg_dca_gpr_dat_lo_send_2 0xF75C +#define reg_dca_gpr_dat_lo_send_2_pos 0 +#define reg_dca_gpr_dat_lo_send_2_len 8 +#define reg_dca_gpr_dat_lo_send_2_lsb 0 +#define p_reg_dca_gpr_dat_lo_send_3 0xF75D +#define reg_dca_gpr_dat_lo_send_3_pos 0 +#define reg_dca_gpr_dat_lo_send_3_len 8 +#define reg_dca_gpr_dat_lo_send_3_lsb 0 +#define p_reg_dca_gpr_dat_lo_send_4 0xF75E +#define reg_dca_gpr_dat_lo_send_4_pos 0 +#define reg_dca_gpr_dat_lo_send_4_len 8 +#define reg_dca_gpr_dat_lo_send_4_lsb 0 +#define p_reg_dca_gpr_dat_lo_send_5 0xF75F +#define reg_dca_gpr_dat_lo_send_5_pos 0 +#define reg_dca_gpr_dat_lo_send_5_len 8 +#define reg_dca_gpr_dat_lo_send_5_lsb 0 +#define p_reg_dca_over_wr_lo_send 0xF760 +#define reg_dca_over_wr_lo_send_pos 0 +#define reg_dca_over_wr_lo_send_len 1 +#define reg_dca_over_wr_lo_send_lsb 0 +#define p_reg_dca_int_lo_send 0xF761 +#define reg_dca_int_lo_send_pos 0 +#define reg_dca_int_lo_send_len 1 +#define reg_dca_int_lo_send_lsb 0 +#define r_reg_dca_gpr_ctr_up_rec 0xF762 +#define reg_dca_gpr_ctr_up_rec_pos 0 +#define reg_dca_gpr_ctr_up_rec_len 8 +#define reg_dca_gpr_ctr_up_rec_lsb 0 +#define r_reg_dca_gpr_dat_up_rec_0 0xF763 +#define reg_dca_gpr_dat_up_rec_0_pos 0 +#define reg_dca_gpr_dat_up_rec_0_len 8 +#define reg_dca_gpr_dat_up_rec_0_lsb 0 +#define r_reg_dca_gpr_dat_up_rec_1 0xF764 +#define reg_dca_gpr_dat_up_rec_1_pos 0 +#define reg_dca_gpr_dat_up_rec_1_len 8 +#define reg_dca_gpr_dat_up_rec_1_lsb 0 +#define r_reg_dca_gpr_dat_up_rec_2 0xF765 +#define reg_dca_gpr_dat_up_rec_2_pos 0 +#define reg_dca_gpr_dat_up_rec_2_len 8 +#define reg_dca_gpr_dat_up_rec_2_lsb 0 +#define r_reg_dca_gpr_dat_up_rec_3 0xF766 +#define reg_dca_gpr_dat_up_rec_3_pos 0 +#define reg_dca_gpr_dat_up_rec_3_len 8 +#define reg_dca_gpr_dat_up_rec_3_lsb 0 +#define r_reg_dca_gpr_dat_up_rec_4 0xF767 +#define reg_dca_gpr_dat_up_rec_4_pos 0 +#define reg_dca_gpr_dat_up_rec_4_len 8 +#define reg_dca_gpr_dat_up_rec_4_lsb 0 +#define r_reg_dca_gpr_dat_up_rec_5 0xF768 +#define reg_dca_gpr_dat_up_rec_5_pos 0 +#define reg_dca_gpr_dat_up_rec_5_len 8 +#define reg_dca_gpr_dat_up_rec_5_lsb 0 +#define r_reg_dca_over_wr_up_rec 0xF769 +#define reg_dca_over_wr_up_rec_pos 0 +#define reg_dca_over_wr_up_rec_len 1 +#define reg_dca_over_wr_up_rec_lsb 0 +#define p_reg_dca_int_up_rec 0xF76A +#define reg_dca_int_up_rec_pos 0 +#define reg_dca_int_up_rec_len 1 +#define reg_dca_int_up_rec_lsb 0 +#define p_reg_dca_fw_read_yet_up 0xF76B +#define reg_dca_fw_read_yet_up_pos 0 +#define reg_dca_fw_read_yet_up_len 1 +#define reg_dca_fw_read_yet_up_lsb 0 +#define r_reg_dca_gpr_ctr_lo_rec 0xF76C +#define reg_dca_gpr_ctr_lo_rec_pos 0 +#define reg_dca_gpr_ctr_lo_rec_len 8 +#define reg_dca_gpr_ctr_lo_rec_lsb 0 +#define r_reg_dca_gpr_dat_lo_rec_0 0xF76D +#define reg_dca_gpr_dat_lo_rec_0_pos 0 +#define reg_dca_gpr_dat_lo_rec_0_len 8 +#define reg_dca_gpr_dat_lo_rec_0_lsb 0 +#define r_reg_dca_gpr_dat_lo_rec_1 0xF76E +#define reg_dca_gpr_dat_lo_rec_1_pos 0 +#define reg_dca_gpr_dat_lo_rec_1_len 8 +#define reg_dca_gpr_dat_lo_rec_1_lsb 0 +#define r_reg_dca_gpr_dat_lo_rec_2 0xF76F +#define reg_dca_gpr_dat_lo_rec_2_pos 0 +#define reg_dca_gpr_dat_lo_rec_2_len 8 +#define reg_dca_gpr_dat_lo_rec_2_lsb 0 +#define r_reg_dca_gpr_dat_lo_rec_3 0xF770 +#define reg_dca_gpr_dat_lo_rec_3_pos 0 +#define reg_dca_gpr_dat_lo_rec_3_len 8 +#define reg_dca_gpr_dat_lo_rec_3_lsb 0 +#define r_reg_dca_gpr_dat_lo_rec_4 0xF771 +#define reg_dca_gpr_dat_lo_rec_4_pos 0 +#define reg_dca_gpr_dat_lo_rec_4_len 8 +#define reg_dca_gpr_dat_lo_rec_4_lsb 0 +#define r_reg_dca_gpr_dat_lo_rec_5 0xF772 +#define reg_dca_gpr_dat_lo_rec_5_pos 0 +#define reg_dca_gpr_dat_lo_rec_5_len 8 +#define reg_dca_gpr_dat_lo_rec_5_lsb 0 +#define r_reg_dca_over_wr_lo_rec 0xF773 +#define reg_dca_over_wr_lo_rec_pos 0 +#define reg_dca_over_wr_lo_rec_len 1 +#define reg_dca_over_wr_lo_rec_lsb 0 +#define p_reg_dca_int_lo_rec 0xF774 +#define reg_dca_int_lo_rec_pos 0 +#define reg_dca_int_lo_rec_len 1 +#define reg_dca_int_lo_rec_lsb 0 +#define p_reg_dca_fw_read_yet_lo 0xF775 +#define reg_dca_fw_read_yet_lo_pos 0 +#define reg_dca_fw_read_yet_lo_len 1 +#define reg_dca_fw_read_yet_lo_lsb 0 +#define p_reg_dca_en 0xF776 +#define reg_dca_en_pos 0 +#define reg_dca_en_len 1 +#define reg_dca_en_lsb 0 +#define p_reg_dca_ulrdy_delay 0xF777 +#define reg_dca_ulrdy_delay_pos 0 +#define reg_dca_ulrdy_delay_len 8 +#define reg_dca_ulrdy_delay_lsb 0 +#define p_reg_dca_fpga_latch 0xF778 +#define reg_dca_fpga_latch_pos 0 +#define reg_dca_fpga_latch_len 8 +#define reg_dca_fpga_latch_lsb 0 +#define p_reg_dca_vldld_err 0xF779 +#define reg_dca_vldld_err_pos 0 +#define reg_dca_vldld_err_len 1 +#define reg_dca_vldld_err_lsb 0 +#define p_reg_dca_vldud_err 0xF77A +#define reg_dca_vldud_err_pos 0 +#define reg_dca_vldud_err_len 1 +#define reg_dca_vldud_err_lsb 0 +#define p_reg_dca_modeu_err 0xF77B +#define reg_dca_modeu_err_pos 0 +#define reg_dca_modeu_err_len 1 +#define reg_dca_modeu_err_lsb 0 +#define p_reg_dca_model_err 0xF77C +#define reg_dca_model_err_pos 0 +#define reg_dca_model_err_len 1 +#define reg_dca_model_err_lsb 0 +#define p_reg_dca_interrupt 0xF77D +#define reg_dca_interrupt_pos 0 +#define reg_dca_interrupt_len 1 +#define reg_dca_interrupt_lsb 0 +#define p_reg_dca_auto_reset_en 0xF77E +#define reg_dca_auto_reset_en_pos 0 +#define reg_dca_auto_reset_en_len 1 +#define reg_dca_auto_reset_en_lsb 0 +#define p_reg_qnt_valuew_7_0 0xF77F +#define reg_qnt_valuew_7_0_pos 0 +#define reg_qnt_valuew_7_0_len 8 +#define reg_qnt_valuew_7_0_lsb 0 +#define p_reg_qnt_valuew_10_8 0xF780 +#define reg_qnt_valuew_10_8_pos 0 +#define reg_qnt_valuew_10_8_len 3 +#define reg_qnt_valuew_10_8_lsb 8 +#define p_reg_qnt_nfvaluew_7_0 0xF781 +#define reg_qnt_nfvaluew_7_0_pos 0 +#define reg_qnt_nfvaluew_7_0_len 8 +#define reg_qnt_nfvaluew_7_0_lsb 0 +#define p_reg_qnt_nfvaluew_10_8 0xF782 +#define reg_qnt_nfvaluew_10_8_pos 0 +#define reg_qnt_nfvaluew_10_8_len 3 +#define reg_qnt_nfvaluew_10_8_lsb 8 +#define p_reg_qnt_flatness_thr_7_0 0xF783 +#define reg_qnt_flatness_thr_7_0_pos 0 +#define reg_qnt_flatness_thr_7_0_len 8 +#define reg_qnt_flatness_thr_7_0_lsb 0 +#define p_reg_qnt_flatness_thr_8 0xF784 +#define reg_qnt_flatness_thr_8_pos 0 +#define reg_qnt_flatness_thr_8_len 1 +#define reg_qnt_flatness_thr_8_lsb 8 +#define p_reg_llr_to_be_monitor 0xF785 +#define reg_llr_to_be_monitor_pos 0 +#define reg_llr_to_be_monitor_len 1 +#define reg_llr_to_be_monitor_lsb 0 +#define p_reg_qnt_vbc_rdy 0xF786 +#define reg_qnt_vbc_rdy_pos 0 +#define reg_qnt_vbc_rdy_len 1 +#define reg_qnt_vbc_rdy_lsb 0 +#define p_reg_qnt_noncmb_vbc_rdy 0xF787 +#define reg_qnt_noncmb_vbc_rdy_pos 0 +#define reg_qnt_noncmb_vbc_rdy_len 1 +#define reg_qnt_noncmb_vbc_rdy_lsb 0 +#define p_reg_use_eh2_mean 0xF788 +#define reg_use_eh2_mean_pos 0 +#define reg_use_eh2_mean_len 1 +#define reg_use_eh2_mean_lsb 0 +#define p_reg_qnt_vbc_ccid_mode 0xF789 +#define reg_qnt_vbc_ccid_mode_pos 0 +#define reg_qnt_vbc_ccid_mode_len 1 +#define reg_qnt_vbc_ccid_mode_lsb 0 +#define p_reg_qnt_cci_bandsize 0xF78A +#define reg_qnt_cci_bandsize_pos 0 +#define reg_qnt_cci_bandsize_len 4 +#define reg_qnt_cci_bandsize_lsb 0 +#define p_reg_qnt_vbc_sframe_num 0xF78B +#define reg_qnt_vbc_sframe_num_pos 0 +#define reg_qnt_vbc_sframe_num_len 8 +#define reg_qnt_vbc_sframe_num_lsb 0 +#define p_reg_sbx_gain_diff_7_0 0xF78C +#define reg_sbx_gain_diff_7_0_pos 0 +#define reg_sbx_gain_diff_7_0_len 8 +#define reg_sbx_gain_diff_7_0_lsb 0 +#define p_reg_sbx_gain_diff_8 0xF78D +#define reg_sbx_gain_diff_8_pos 0 +#define reg_sbx_gain_diff_8_len 1 +#define reg_sbx_gain_diff_8_lsb 8 +#define p_reg_sbx_gain_diff_rdy 0xF78E +#define reg_sbx_gain_diff_rdy_pos 0 +#define reg_sbx_gain_diff_rdy_len 1 +#define reg_sbx_gain_diff_rdy_lsb 0 +#define p_reg_sbx_noncmb_gain_diff_7_0 0xF78F +#define reg_sbx_noncmb_gain_diff_7_0_pos 0 +#define reg_sbx_noncmb_gain_diff_7_0_len 8 +#define reg_sbx_noncmb_gain_diff_7_0_lsb 0 +#define p_reg_sbx_noncmb_gain_diff_8 0xF790 +#define reg_sbx_noncmb_gain_diff_8_pos 0 +#define reg_sbx_noncmb_gain_diff_8_len 1 +#define reg_sbx_noncmb_gain_diff_8_lsb 8 +#define p_reg_sbx_noncmb_gain_diff_rdy 0xF791 +#define reg_sbx_noncmb_gain_diff_rdy_pos 0 +#define reg_sbx_noncmb_gain_diff_rdy_len 1 +#define reg_sbx_noncmb_gain_diff_rdy_lsb 0 +#define r_reg_qnt_vbc_err_7_0 0xF792 +#define reg_qnt_vbc_err_7_0_pos 0 +#define reg_qnt_vbc_err_7_0_len 8 +#define reg_qnt_vbc_err_7_0_lsb 0 +#define r_reg_qnt_vbc_err_15_8 0xF793 +#define reg_qnt_vbc_err_15_8_pos 0 +#define reg_qnt_vbc_err_15_8_len 8 +#define reg_qnt_vbc_err_15_8_lsb 8 +#define r_reg_qnt_vbc_err_23_16 0xF794 +#define reg_qnt_vbc_err_23_16_pos 0 +#define reg_qnt_vbc_err_23_16_len 8 +#define reg_qnt_vbc_err_23_16_lsb 16 +#define r_reg_qnt_noncmb_vbc_err_7_0 0xF795 +#define reg_qnt_noncmb_vbc_err_7_0_pos 0 +#define reg_qnt_noncmb_vbc_err_7_0_len 8 +#define reg_qnt_noncmb_vbc_err_7_0_lsb 0 +#define r_reg_qnt_noncmb_vbc_err_15_8 0xF796 +#define reg_qnt_noncmb_vbc_err_15_8_pos 0 +#define reg_qnt_noncmb_vbc_err_15_8_len 8 +#define reg_qnt_noncmb_vbc_err_15_8_lsb 8 +#define r_reg_qnt_noncmb_vbc_err_23_16 0xF797 +#define reg_qnt_noncmb_vbc_err_23_16_pos 0 +#define reg_qnt_noncmb_vbc_err_23_16_len 8 +#define reg_qnt_noncmb_vbc_err_23_16_lsb 16 +#define p_reg_sbx_signalquality_threshold 0xF798 +#define reg_sbx_signalquality_threshold_pos 0 +#define reg_sbx_signalquality_threshold_len 4 +#define reg_sbx_signalquality_threshold_lsb 0 +#define r_reg_sbx_signalquality_ind 0xF799 +#define reg_sbx_signalquality_ind_pos 0 +#define reg_sbx_signalquality_ind_len 1 +#define reg_sbx_signalquality_ind_lsb 0 +#define p_reg_p_sbxqnt_th1 0xF79A +#define reg_p_sbxqnt_th1_pos 0 +#define reg_p_sbxqnt_th1_len 8 +#define reg_p_sbxqnt_th1_lsb 0 +#define p_reg_p_sbxqnt_th2 0xF79B +#define reg_p_sbxqnt_th2_pos 0 +#define reg_p_sbxqnt_th2_len 8 +#define reg_p_sbxqnt_th2_lsb 0 +#define p_reg_p_sbxqnt_th3 0xF79C +#define reg_p_sbxqnt_th3_pos 0 +#define reg_p_sbxqnt_th3_len 8 +#define reg_p_sbxqnt_th3_lsb 0 +#define p_reg_p_sbxqnt_th4 0xF79D +#define reg_p_sbxqnt_th4_pos 0 +#define reg_p_sbxqnt_th4_len 8 +#define reg_p_sbxqnt_th4_lsb 0 +#define p_reg_p_sbxqnt_th5 0xF79E +#define reg_p_sbxqnt_th5_pos 0 +#define reg_p_sbxqnt_th5_len 8 +#define reg_p_sbxqnt_th5_lsb 0 +#define p_reg_p_sbxqnt_th6 0xF79F +#define reg_p_sbxqnt_th6_pos 0 +#define reg_p_sbxqnt_th6_len 8 +#define reg_p_sbxqnt_th6_lsb 0 +#define p_reg_p_sbxqnt_th7 0xF800 +#define reg_p_sbxqnt_th7_pos 0 +#define reg_p_sbxqnt_th7_len 8 +#define reg_p_sbxqnt_th7_lsb 0 +#define p_reg_p_sbxqnt_th8 0xF801 +#define reg_p_sbxqnt_th8_pos 0 +#define reg_p_sbxqnt_th8_len 8 +#define reg_p_sbxqnt_th8_lsb 0 +#define p_reg_p_sbxqnt_th9 0xF802 +#define reg_p_sbxqnt_th9_pos 0 +#define reg_p_sbxqnt_th9_len 8 +#define reg_p_sbxqnt_th9_lsb 0 +#define p_reg_p_sbxqnt_th10 0xF803 +#define reg_p_sbxqnt_th10_pos 0 +#define reg_p_sbxqnt_th10_len 8 +#define reg_p_sbxqnt_th10_lsb 0 +#define p_reg_p_sbxqnt_th11 0xF804 +#define reg_p_sbxqnt_th11_pos 0 +#define reg_p_sbxqnt_th11_len 8 +#define reg_p_sbxqnt_th11_lsb 0 +#define p_reg_p_sbxqnt_th12 0xF805 +#define reg_p_sbxqnt_th12_pos 0 +#define reg_p_sbxqnt_th12_len 8 +#define reg_p_sbxqnt_th12_lsb 0 +#define p_reg_p_sbxqnt_th13_7_0 0xF806 +#define reg_p_sbxqnt_th13_7_0_pos 0 +#define reg_p_sbxqnt_th13_7_0_len 8 +#define reg_p_sbxqnt_th13_7_0_lsb 0 +#define p_reg_p_sbxqnt_th13_9_8 0xF807 +#define reg_p_sbxqnt_th13_9_8_pos 0 +#define reg_p_sbxqnt_th13_9_8_len 2 +#define reg_p_sbxqnt_th13_9_8_lsb 8 +#define p_reg_p_sbxqnt_th14_7_0 0xF808 +#define reg_p_sbxqnt_th14_7_0_pos 0 +#define reg_p_sbxqnt_th14_7_0_len 8 +#define reg_p_sbxqnt_th14_7_0_lsb 0 +#define p_reg_p_sbxqnt_th14_9_8 0xF809 +#define reg_p_sbxqnt_th14_9_8_pos 0 +#define reg_p_sbxqnt_th14_9_8_len 2 +#define reg_p_sbxqnt_th14_9_8_lsb 8 +#define p_reg_p_sbxqnt_th15_7_0 0xF80A +#define reg_p_sbxqnt_th15_7_0_pos 0 +#define reg_p_sbxqnt_th15_7_0_len 8 +#define reg_p_sbxqnt_th15_7_0_lsb 0 +#define p_reg_p_sbxqnt_th15_9_8 0xF80B +#define reg_p_sbxqnt_th15_9_8_pos 0 +#define reg_p_sbxqnt_th15_9_8_len 2 +#define reg_p_sbxqnt_th15_9_8_lsb 8 +#define p_reg_p_sbxqnt_vzh2_th0 0xF80C +#define reg_p_sbxqnt_vzh2_th0_pos 0 +#define reg_p_sbxqnt_vzh2_th0_len 8 +#define reg_p_sbxqnt_vzh2_th0_lsb 0 +#define p_reg_p_sbxqnt_vzh2_th1 0xF80D +#define reg_p_sbxqnt_vzh2_th1_pos 0 +#define reg_p_sbxqnt_vzh2_th1_len 8 +#define reg_p_sbxqnt_vzh2_th1_lsb 0 +#define p_reg_p_sbxqnt_vzh2_th2 0xF80E +#define reg_p_sbxqnt_vzh2_th2_pos 0 +#define reg_p_sbxqnt_vzh2_th2_len 8 +#define reg_p_sbxqnt_vzh2_th2_lsb 0 +#define p_reg_p_qnt_w_comp1 0xF80F +#define reg_p_qnt_w_comp1_pos 0 +#define reg_p_qnt_w_comp1_len 8 +#define reg_p_qnt_w_comp1_lsb 0 +#define p_reg_p_qnt_w_comp2 0xF810 +#define reg_p_qnt_w_comp2_pos 0 +#define reg_p_qnt_w_comp2_len 8 +#define reg_p_qnt_w_comp2_lsb 0 +#define p_reg_p_qnt_w_comp3 0xF811 +#define reg_p_qnt_w_comp3_pos 0 +#define reg_p_qnt_w_comp3_len 8 +#define reg_p_qnt_w_comp3_lsb 0 +#define p_reg_p_vtb_in_0 0xF821 +#define reg_p_vtb_in_0_pos 0 +#define reg_p_vtb_in_0_len 6 +#define reg_p_vtb_in_0_lsb 0 +#define p_reg_p_vtb_in_1 0xF822 +#define reg_p_vtb_in_1_pos 0 +#define reg_p_vtb_in_1_len 6 +#define reg_p_vtb_in_1_lsb 0 +#define p_reg_p_vtb_in_2 0xF823 +#define reg_p_vtb_in_2_pos 0 +#define reg_p_vtb_in_2_len 6 +#define reg_p_vtb_in_2_lsb 0 +#define p_reg_p_vtb_in_3 0xF824 +#define reg_p_vtb_in_3_pos 0 +#define reg_p_vtb_in_3_len 6 +#define reg_p_vtb_in_3_lsb 0 +#define p_reg_p_vtb_in_4 0xF825 +#define reg_p_vtb_in_4_pos 0 +#define reg_p_vtb_in_4_len 6 +#define reg_p_vtb_in_4_lsb 0 +#define p_reg_p_vtb_in_5 0xF826 +#define reg_p_vtb_in_5_pos 0 +#define reg_p_vtb_in_5_len 6 +#define reg_p_vtb_in_5_lsb 0 +#define p_reg_p_vtb_in_6 0xF827 +#define reg_p_vtb_in_6_pos 0 +#define reg_p_vtb_in_6_len 6 +#define reg_p_vtb_in_6_lsb 0 +#define p_reg_p_vtb_in_7 0xF828 +#define reg_p_vtb_in_7_pos 0 +#define reg_p_vtb_in_7_len 6 +#define reg_p_vtb_in_7_lsb 0 +#define p_reg_p_vtb_in_8 0xF829 +#define reg_p_vtb_in_8_pos 0 +#define reg_p_vtb_in_8_len 6 +#define reg_p_vtb_in_8_lsb 0 +#define p_reg_p_vtb_in_9 0xF82A +#define reg_p_vtb_in_9_pos 0 +#define reg_p_vtb_in_9_len 6 +#define reg_p_vtb_in_9_lsb 0 +#define p_reg_p_vtb_in_10 0xF82B +#define reg_p_vtb_in_10_pos 0 +#define reg_p_vtb_in_10_len 6 +#define reg_p_vtb_in_10_lsb 0 +#define p_reg_p_vtb_in_11 0xF82C +#define reg_p_vtb_in_11_pos 0 +#define reg_p_vtb_in_11_len 6 +#define reg_p_vtb_in_11_lsb 0 +#define p_reg_p_vtb_in_12 0xF82D +#define reg_p_vtb_in_12_pos 0 +#define reg_p_vtb_in_12_len 6 +#define reg_p_vtb_in_12_lsb 0 +#define p_reg_p_vtb_in_13 0xF82E +#define reg_p_vtb_in_13_pos 0 +#define reg_p_vtb_in_13_len 6 +#define reg_p_vtb_in_13_lsb 0 +#define p_reg_p_vtb_in_14 0xF82F +#define reg_p_vtb_in_14_pos 0 +#define reg_p_vtb_in_14_len 6 +#define reg_p_vtb_in_14_lsb 0 +#define p_reg_p_vtb_in_15 0xF830 +#define reg_p_vtb_in_15_pos 0 +#define reg_p_vtb_in_15_len 6 +#define reg_p_vtb_in_15_lsb 0 +#define I2C_i2c_m_slave_addr 0xF940 +#define i2c_m_slave_addr_pos 0 +#define i2c_m_slave_addr_len 8 +#define i2c_m_slave_addr_lsb 0 +#define I2C_i2c_m_data1 0xF941 +#define i2c_m_data1_pos 0 +#define i2c_m_data1_len 8 +#define i2c_m_data1_lsb 0 +#define I2C_i2c_m_data2 0xF942 +#define i2c_m_data2_pos 0 +#define i2c_m_data2_len 8 +#define i2c_m_data2_lsb 0 +#define I2C_i2c_m_data3 0xF943 +#define i2c_m_data3_pos 0 +#define i2c_m_data3_len 8 +#define i2c_m_data3_lsb 0 +#define I2C_i2c_m_data4 0xF944 +#define i2c_m_data4_pos 0 +#define i2c_m_data4_len 8 +#define i2c_m_data4_lsb 0 +#define I2C_i2c_m_data5 0xF945 +#define i2c_m_data5_pos 0 +#define i2c_m_data5_len 8 +#define i2c_m_data5_lsb 0 +#define I2C_i2c_m_data6 0xF946 +#define i2c_m_data6_pos 0 +#define i2c_m_data6_len 8 +#define i2c_m_data6_lsb 0 +#define I2C_i2c_m_data7 0xF947 +#define i2c_m_data7_pos 0 +#define i2c_m_data7_len 8 +#define i2c_m_data7_lsb 0 +#define I2C_i2c_m_data8 0xF948 +#define i2c_m_data8_pos 0 +#define i2c_m_data8_len 8 +#define i2c_m_data8_lsb 0 +#define I2C_i2c_m_data9 0xF949 +#define i2c_m_data9_pos 0 +#define i2c_m_data9_len 8 +#define i2c_m_data9_lsb 0 +#define I2C_i2c_m_data10 0xF94A +#define i2c_m_data10_pos 0 +#define i2c_m_data10_len 8 +#define i2c_m_data10_lsb 0 +#define I2C_i2c_m_data11 0xF94B +#define i2c_m_data11_pos 0 +#define i2c_m_data11_len 8 +#define i2c_m_data11_lsb 0 +#define I2C_i2c_m_data12 0xF94C +#define i2c_m_data12_pos 0 +#define i2c_m_data12_len 8 +#define i2c_m_data12_lsb 0 +#define I2C_i2c_m_data13 0xF94D +#define i2c_m_data13_pos 0 +#define i2c_m_data13_len 8 +#define i2c_m_data13_lsb 0 +#define I2C_i2c_m_data14 0xF94E +#define i2c_m_data14_pos 0 +#define i2c_m_data14_len 8 +#define i2c_m_data14_lsb 0 +#define I2C_i2c_m_data15 0xF94F +#define i2c_m_data15_pos 0 +#define i2c_m_data15_len 8 +#define i2c_m_data15_lsb 0 +#define I2C_i2c_m_data16 0xF950 +#define i2c_m_data16_pos 0 +#define i2c_m_data16_len 8 +#define i2c_m_data16_lsb 0 +#define I2C_i2c_m_data17 0xF951 +#define i2c_m_data17_pos 0 +#define i2c_m_data17_len 8 +#define i2c_m_data17_lsb 0 +#define I2C_i2c_m_data18 0xF952 +#define i2c_m_data18_pos 0 +#define i2c_m_data18_len 8 +#define i2c_m_data18_lsb 0 +#define I2C_i2c_m_data19 0xF953 +#define i2c_m_data19_pos 0 +#define i2c_m_data19_len 8 +#define i2c_m_data19_lsb 0 +#define I2C_i2c_m_cmd_rw 0xF954 +#define i2c_m_cmd_rw_pos 0 +#define i2c_m_cmd_rw_len 1 +#define i2c_m_cmd_rw_lsb 0 +#define I2C_i2c_m_cmd_rwlen 0xF954 +#define i2c_m_cmd_rwlen_pos 3 +#define i2c_m_cmd_rwlen_len 4 +#define i2c_m_cmd_rwlen_lsb 0 +#define I2C_i2c_m_status_cmd_exe 0xF955 +#define i2c_m_status_cmd_exe_pos 0 +#define i2c_m_status_cmd_exe_len 1 +#define i2c_m_status_cmd_exe_lsb 0 +#define I2C_i2c_m_status_wdat_done 0xF955 +#define i2c_m_status_wdat_done_pos 1 +#define i2c_m_status_wdat_done_len 1 +#define i2c_m_status_wdat_done_lsb 0 +#define I2C_i2c_m_status_wdat_fail 0xF955 +#define i2c_m_status_wdat_fail_pos 2 +#define i2c_m_status_wdat_fail_len 1 +#define i2c_m_status_wdat_fail_lsb 0 +#define I2C_i2c_m_status_rdat_rdy 0xF955 +#define i2c_m_status_rdat_rdy_pos 3 +#define i2c_m_status_rdat_rdy_len 1 +#define i2c_m_status_rdat_rdy_lsb 0 +#define I2C_i2c_m_period 0xF956 +#define i2c_m_period_pos 0 +#define i2c_m_period_len 8 +#define i2c_m_period_lsb 0 +#define I2C_i2c_m_reg_msb_lsb 0xF957 +#define i2c_m_reg_msb_lsb_pos 0 +#define i2c_m_reg_msb_lsb_len 1 +#define i2c_m_reg_msb_lsb_lsb 0 +#define I2C_reg_ofdm_rst 0xF957 +#define reg_ofdm_rst_pos 1 +#define reg_ofdm_rst_len 1 +#define reg_ofdm_rst_lsb 0 +#define I2C_reg_sample_period_on_tuner 0xF957 +#define reg_sample_period_on_tuner_pos 2 +#define reg_sample_period_on_tuner_len 1 +#define reg_sample_period_on_tuner_lsb 0 +#define I2C_reg_sel_tuner 0xF957 +#define reg_sel_tuner_pos 3 +#define reg_sel_tuner_len 1 +#define reg_sel_tuner_lsb 0 +#define I2C_reg_ofdm_rst_en 0xF957 +#define reg_ofdm_rst_en_pos 4 +#define reg_ofdm_rst_en_len 1 +#define reg_ofdm_rst_en_lsb 0 +#define p_mp2if_psb_overflow 0xF980 +#define mp2if_psb_overflow_pos 0 +#define mp2if_psb_overflow_len 1 +#define mp2if_psb_overflow_lsb 0 +#define p_mp2if_no_modify_tei_bit 0xF981 +#define mp2if_no_modify_tei_bit_pos 0 +#define mp2if_no_modify_tei_bit_len 1 +#define mp2if_no_modify_tei_bit_lsb 0 +#define p_mp2if_keep_sf_sync_byte 0xF982 +#define mp2if_keep_sf_sync_byte_pos 0 +#define mp2if_keep_sf_sync_byte_len 1 +#define mp2if_keep_sf_sync_byte_lsb 0 +#define p_mp2if_data_access_disable 0xF983 +#define mp2if_data_access_disable_pos 0 +#define mp2if_data_access_disable_len 1 +#define mp2if_data_access_disable_lsb 0 +#define p_mp2if_mpeg_ser_do7 0xF984 +#define mp2if_mpeg_ser_do7_pos 0 +#define mp2if_mpeg_ser_do7_len 1 +#define mp2if_mpeg_ser_do7_lsb 0 +#define p_mp2if_mpeg_ser_mode 0xF985 +#define mp2if_mpeg_ser_mode_pos 0 +#define mp2if_mpeg_ser_mode_len 1 +#define mp2if_mpeg_ser_mode_lsb 0 +#define p_mp2if_mpeg_par_mode 0xF986 +#define mp2if_mpeg_par_mode_pos 0 +#define mp2if_mpeg_par_mode_len 1 +#define mp2if_mpeg_par_mode_lsb 0 +#define r_mp2if_psb_empty 0xF987 +#define mp2if_psb_empty_pos 0 +#define mp2if_psb_empty_len 1 +#define mp2if_psb_empty_lsb 0 +#define r_mp2if_ts_not_188 0xF988 +#define mp2if_ts_not_188_pos 0 +#define mp2if_ts_not_188_len 1 +#define mp2if_ts_not_188_lsb 0 +#define p_mp2if_mssync_len 0xF989 +#define mp2if_mssync_len_pos 0 +#define mp2if_mssync_len_len 1 +#define mp2if_mssync_len_lsb 0 +#define p_mp2if_msdo_msb 0xF98A +#define mp2if_msdo_msb_pos 0 +#define mp2if_msdo_msb_len 1 +#define mp2if_msdo_msb_lsb 0 +#define p_mp2if_mpeg_clk_gated 0xF98B +#define mp2if_mpeg_clk_gated_pos 0 +#define mp2if_mpeg_clk_gated_len 1 +#define mp2if_mpeg_clk_gated_lsb 0 +#define p_mp2if_mpeg_err_pol 0xF98C +#define mp2if_mpeg_err_pol_pos 0 +#define mp2if_mpeg_err_pol_len 1 +#define mp2if_mpeg_err_pol_lsb 0 +#define p_mp2if_mpeg_sync_pol 0xF98D +#define mp2if_mpeg_sync_pol_pos 0 +#define mp2if_mpeg_sync_pol_len 1 +#define mp2if_mpeg_sync_pol_lsb 0 +#define p_mp2if_mpeg_vld_pol 0xF98E +#define mp2if_mpeg_vld_pol_pos 0 +#define mp2if_mpeg_vld_pol_len 1 +#define mp2if_mpeg_vld_pol_lsb 0 +#define p_mp2if_mpeg_clk_pol 0xF98F +#define mp2if_mpeg_clk_pol_pos 0 +#define mp2if_mpeg_clk_pol_len 1 +#define mp2if_mpeg_clk_pol_lsb 0 +#define p_reg_mpeg_full_speed 0xF990 +#define reg_mpeg_full_speed_pos 0 +#define reg_mpeg_full_speed_len 1 +#define reg_mpeg_full_speed_lsb 0 +#define p_mp2if_pid_complement 0xF991 +#define mp2if_pid_complement_pos 0 +#define mp2if_pid_complement_len 1 +#define mp2if_pid_complement_lsb 0 +#define p_mp2if_pid_rst 0xF992 +#define mp2if_pid_rst_pos 0 +#define mp2if_pid_rst_len 1 +#define mp2if_pid_rst_lsb 0 +#define p_mp2if_pid_en 0xF993 +#define mp2if_pid_en_pos 0 +#define mp2if_pid_en_len 1 +#define mp2if_pid_en_lsb 0 +#define p_mp2if_pid_index_en 0xF994 +#define mp2if_pid_index_en_pos 0 +#define mp2if_pid_index_en_len 1 +#define mp2if_pid_index_en_lsb 0 +#define p_mp2if_pid_index 0xF995 +#define mp2if_pid_index_pos 0 +#define mp2if_pid_index_len 5 +#define mp2if_pid_index_lsb 0 +#define p_mp2if_pid_dat_l 0xF996 +#define mp2if_pid_dat_l_pos 0 +#define mp2if_pid_dat_l_len 8 +#define mp2if_pid_dat_l_lsb 0 +#define p_mp2if_pid_dat_h 0xF997 +#define mp2if_pid_dat_h_pos 0 +#define mp2if_pid_dat_h_len 5 +#define mp2if_pid_dat_h_lsb 0 +#define p_reg_latch_clk 0xF998 +#define reg_latch_clk_pos 0 +#define reg_latch_clk_len 1 +#define reg_latch_clk_lsb 0 +#define r_mp2if_sync_byte_locked 0xF999 +#define mp2if_sync_byte_locked_pos 0 +#define mp2if_sync_byte_locked_len 1 +#define mp2if_sync_byte_locked_lsb 0 +#define p_mp2if_ignore_sync_byte 0xF99A +#define mp2if_ignore_sync_byte_pos 0 +#define mp2if_ignore_sync_byte_len 1 +#define mp2if_ignore_sync_byte_lsb 0 +#define p_reg_mp2if_clk_en 0xF99B +#define reg_mp2if_clk_en_pos 0 +#define reg_mp2if_clk_en_len 1 +#define reg_mp2if_clk_en_lsb 0 +#define p_reg_mpeg_vld_tgl 0xF99C +#define reg_mpeg_vld_tgl_pos 0 +#define reg_mpeg_vld_tgl_len 1 +#define reg_mpeg_vld_tgl_lsb 0 +#define p_reg_mp2_sw_rst 0xF99D +#define reg_mp2_sw_rst_pos 0 +#define reg_mp2_sw_rst_len 1 +#define reg_mp2_sw_rst_lsb 0 +#define p_mp2if_psb_en 0xF99E +#define mp2if_psb_en_pos 0 +#define mp2if_psb_en_len 1 +#define mp2if_psb_en_lsb 0 +#define r_mp2if_usb20_mode 0xF99F +#define mp2if_usb20_mode_pos 0 +#define mp2if_usb20_mode_len 1 +#define mp2if_usb20_mode_lsb 0 +#define r_mp2if_strap_usb20_mode 0xF9A0 +#define mp2if_strap_usb20_mode_pos 0 +#define mp2if_strap_usb20_mode_len 1 +#define mp2if_strap_usb20_mode_lsb 0 +#define r_mp2if_lost_pkt_cnt_l 0xF9A1 +#define mp2if_lost_pkt_cnt_l_pos 0 +#define mp2if_lost_pkt_cnt_l_len 8 +#define mp2if_lost_pkt_cnt_l_lsb 0 +#define r_mp2if_lost_pkt_cnt_h 0xF9A2 +#define mp2if_lost_pkt_cnt_h_pos 0 +#define mp2if_lost_pkt_cnt_h_len 8 +#define mp2if_lost_pkt_cnt_h_lsb 0 +#define p_reg_mp2if2_en 0xF9A3 +#define reg_mp2if2_en_pos 0 +#define reg_mp2if2_en_len 1 +#define reg_mp2if2_en_lsb 0 +#define p_reg_mp2if2_sw_rst 0xF9A4 +#define reg_mp2if2_sw_rst_pos 0 +#define reg_mp2if2_sw_rst_len 1 +#define reg_mp2if2_sw_rst_lsb 0 +#define p_reg_mp2if2_half_psb 0xF9A5 +#define reg_mp2if2_half_psb_pos 0 +#define reg_mp2if2_half_psb_len 1 +#define reg_mp2if2_half_psb_lsb 0 +#define p_reg_ts_byte_endian 0xF9A6 +#define reg_ts_byte_endian_pos 0 +#define reg_ts_byte_endian_len 1 +#define reg_ts_byte_endian_lsb 0 +#define p_reg_mp2_dioif 0xF9A7 +#define reg_mp2_dioif_pos 0 +#define reg_mp2_dioif_len 1 +#define reg_mp2_dioif_lsb 0 +#define p_reg_mp2_dioif_fast 0xF9A8 +#define reg_mp2_dioif_fast_pos 0 +#define reg_mp2_dioif_fast_len 1 +#define reg_mp2_dioif_fast_lsb 0 +#define p_reg_tpsd_bw_mp2if 0xF9A9 +#define reg_tpsd_bw_mp2if_pos 0 +#define reg_tpsd_bw_mp2if_len 2 +#define reg_tpsd_bw_mp2if_lsb 0 +#define p_reg_tpsd_gi_mp2if 0xF9AA +#define reg_tpsd_gi_mp2if_pos 0 +#define reg_tpsd_gi_mp2if_len 2 +#define reg_tpsd_gi_mp2if_lsb 0 +#define p_reg_tpsd_cr_mp2if 0xF9AB +#define reg_tpsd_cr_mp2if_pos 0 +#define reg_tpsd_cr_mp2if_len 3 +#define reg_tpsd_cr_mp2if_lsb 0 +#define p_reg_tpsd_cons_mp2if 0xF9AC +#define reg_tpsd_cons_mp2if_pos 0 +#define reg_tpsd_cons_mp2if_len 2 +#define reg_tpsd_cons_mp2if_lsb 0 +#define p_reg_fw_table_en 0xF9AD +#define reg_fw_table_en_pos 0 +#define reg_fw_table_en_len 1 +#define reg_fw_table_en_lsb 0 +#define p_reg_p_aud_pk_gen_aud_pk_size 0xF9AD +#define reg_p_aud_pk_gen_aud_pk_size_pos 1 +#define reg_p_aud_pk_gen_aud_pk_size_len 6 +#define reg_p_aud_pk_gen_aud_pk_size_lsb 0 +#define p_mp2if_psb_num_blk 0xF9AE +#define mp2if_psb_num_blk_pos 0 +#define mp2if_psb_num_blk_len 6 +#define mp2if_psb_num_blk_lsb 0 +#define p_reg_fec_fake 0xF9AF +#define reg_fec_fake_pos 0 +#define reg_fec_fake_len 1 +#define reg_fec_fake_lsb 0 +#define p_reg_p_ccir_atv_en 0xF9AF +#define reg_p_ccir_atv_en_pos 1 +#define reg_p_ccir_atv_en_len 1 +#define reg_p_ccir_atv_en_lsb 0 +#define p_reg_video_stop_n 0xF9AF +#define reg_video_stop_n_pos 2 +#define reg_video_stop_n_len 1 +#define reg_video_stop_n_lsb 0 +#define p_reg_audio_stop_n 0xF9AF +#define reg_audio_stop_n_pos 3 +#define reg_audio_stop_n_len 1 +#define reg_audio_stop_n_lsb 0 +#define p_mp2if_i2smode 0xF9AF +#define mp2if_i2smode_pos 4 +#define mp2if_i2smode_len 2 +#define mp2if_i2smode_lsb 0 +#define p_mp2if_word_size 0xF9AF +#define mp2if_word_size_pos 6 +#define mp2if_word_size_len 2 +#define mp2if_word_size_lsb 0 +#define p_reg_packet_gap 0xF9B0 +#define reg_packet_gap_pos 0 +#define reg_packet_gap_len 8 +#define reg_packet_gap_lsb 0 +#define p_reg_ts_dat_inv 0xF9B2 +#define reg_ts_dat_inv_pos 0 +#define reg_ts_dat_inv_len 1 +#define reg_ts_dat_inv_lsb 0 +#define p_reg_ts_lsb_1st 0xF9B3 +#define reg_ts_lsb_1st_pos 0 +#define reg_ts_lsb_1st_len 1 +#define reg_ts_lsb_1st_lsb 0 +#define p_reg_ts_capt_bg_sel 0xF9B4 +#define reg_ts_capt_bg_sel_pos 0 +#define reg_ts_capt_bg_sel_len 1 +#define reg_ts_capt_bg_sel_lsb 0 +#define p_reg_mp2if_stop_en 0xF9B5 +#define reg_mp2if_stop_en_pos 0 +#define reg_mp2if_stop_en_len 1 +#define reg_mp2if_stop_en_lsb 0 +#define p_reg_mp2if2_pes_base 0xF9B6 +#define reg_mp2if2_pes_base_pos 0 +#define reg_mp2if2_pes_base_len 1 +#define reg_mp2if2_pes_base_lsb 0 +#define p_reg_ts_sync_inv 0xF9B7 +#define reg_ts_sync_inv_pos 0 +#define reg_ts_sync_inv_len 1 +#define reg_ts_sync_inv_lsb 0 +#define p_reg_ts_vld_inv 0xF9B8 +#define reg_ts_vld_inv_pos 0 +#define reg_ts_vld_inv_len 1 +#define reg_ts_vld_inv_lsb 0 +#define p_reg_sys_buf_overflow 0xF9B9 +#define reg_sys_buf_overflow_pos 0 +#define reg_sys_buf_overflow_len 1 +#define reg_sys_buf_overflow_lsb 0 +#define p_reg_top_dummy0 0xF9BB +#define reg_top_dummy0_pos 0 +#define reg_top_dummy0_len 8 +#define reg_top_dummy0_lsb 0 +#define p_reg_top_dummy1 0xF9BC +#define reg_top_dummy1_pos 0 +#define reg_top_dummy1_len 8 +#define reg_top_dummy1_lsb 0 +#define p_reg_top_dummy2 0xF9BD +#define reg_top_dummy2_pos 0 +#define reg_top_dummy2_len 8 +#define reg_top_dummy2_lsb 0 +#define p_reg_top_dummy3 0xF9BE +#define reg_top_dummy3_pos 0 +#define reg_top_dummy3_len 8 +#define reg_top_dummy3_lsb 0 +#define p_reg_top_dummy4 0xF9BF +#define reg_top_dummy4_pos 0 +#define reg_top_dummy4_len 8 +#define reg_top_dummy4_lsb 0 +#define p_reg_top_dummy5 0xF9C0 +#define reg_top_dummy5_pos 0 +#define reg_top_dummy5_len 8 +#define reg_top_dummy5_lsb 0 +#define p_reg_top_dummy6 0xF9C1 +#define reg_top_dummy6_pos 0 +#define reg_top_dummy6_len 8 +#define reg_top_dummy6_lsb 0 +#define p_reg_top_dummy7 0xF9C2 +#define reg_top_dummy7_pos 0 +#define reg_top_dummy7_len 8 +#define reg_top_dummy7_lsb 0 +#define p_reg_top_dummy8 0xF9C3 +#define reg_top_dummy8_pos 0 +#define reg_top_dummy8_len 8 +#define reg_top_dummy8_lsb 0 +#define p_reg_top_dummy9 0xF9C4 +#define reg_top_dummy9_pos 0 +#define reg_top_dummy9_len 8 +#define reg_top_dummy9_lsb 0 +#define p_reg_top_dummyA 0xF9C5 +#define reg_top_dummyA_pos 0 +#define reg_top_dummyA_len 8 +#define reg_top_dummyA_lsb 0 +#define p_reg_top_dummyB 0xF9C6 +#define reg_top_dummyB_pos 0 +#define reg_top_dummyB_len 8 +#define reg_top_dummyB_lsb 0 +#define p_reg_top_dummyC 0xF9C7 +#define reg_top_dummyC_pos 0 +#define reg_top_dummyC_len 8 +#define reg_top_dummyC_lsb 0 +#define p_reg_top_dummyD 0xF9C8 +#define reg_top_dummyD_pos 0 +#define reg_top_dummyD_len 8 +#define reg_top_dummyD_lsb 0 +#define p_reg_top_dummyE 0xF9C9 +#define reg_top_dummyE_pos 0 +#define reg_top_dummyE_len 8 +#define reg_top_dummyE_lsb 0 +#define p_reg_top_dummyF 0xF9CA +#define reg_top_dummyF_pos 0 +#define reg_top_dummyF_len 8 +#define reg_top_dummyF_lsb 0 +#define p_reg_mp2if_clk_coeff 0xF9CB +#define reg_mp2if_clk_coeff_pos 0 +#define reg_mp2if_clk_coeff_len 7 +#define reg_mp2if_clk_coeff_lsb 0 +#define p_reg_tsip_en 0xF9CC +#define reg_tsip_en_pos 0 +#define reg_tsip_en_len 1 +#define reg_tsip_en_lsb 0 +#define p_reg_tsis_en 0xF9CD +#define reg_tsis_en_pos 0 +#define reg_tsis_en_len 1 +#define reg_tsis_en_lsb 0 +#define p_reg_tsip_br 0xF9CE +#define reg_tsip_br_pos 0 +#define reg_tsip_br_len 1 +#define reg_tsip_br_lsb 0 +#define p_reg_tsip_frm_inv 0xF9D0 +#define reg_tsip_frm_inv_pos 0 +#define reg_tsip_frm_inv_len 1 +#define reg_tsip_frm_inv_lsb 0 +#define p_reg_tsip_str_inv 0xF9D1 +#define reg_tsip_str_inv_pos 0 +#define reg_tsip_str_inv_len 1 +#define reg_tsip_str_inv_lsb 0 +#define p_reg_tsip_fail_inv 0xF9D2 +#define reg_tsip_fail_inv_pos 0 +#define reg_tsip_fail_inv_len 1 +#define reg_tsip_fail_inv_lsb 0 +#define p_reg_tsip_frm_ignore 0xF9D3 +#define reg_tsip_frm_ignore_pos 0 +#define reg_tsip_frm_ignore_len 1 +#define reg_tsip_frm_ignore_lsb 0 +#define p_reg_tsip_str_ignore 0xF9D4 +#define reg_tsip_str_ignore_pos 0 +#define reg_tsip_str_ignore_len 1 +#define reg_tsip_str_ignore_lsb 0 +#define p_reg_tsip_fail_ignore 0xF9D5 +#define reg_tsip_fail_ignore_pos 0 +#define reg_tsip_fail_ignore_len 1 +#define reg_tsip_fail_ignore_lsb 0 +#define p_reg_tsip_endian 0xF9D6 +#define reg_tsip_endian_pos 0 +#define reg_tsip_endian_len 1 +#define reg_tsip_endian_lsb 0 +#define p_reg_tsip_overflow 0xF9D7 +#define reg_tsip_overflow_pos 0 +#define reg_tsip_overflow_len 1 +#define reg_tsip_overflow_lsb 0 +#define p_reg_ts_in_src 0xF9D8 +#define reg_ts_in_src_pos 0 +#define reg_ts_in_src_len 1 +#define reg_ts_in_src_lsb 0 +#define r_reg_clk_sel 0xF9D9 +#define reg_clk_sel_pos 0 +#define reg_clk_sel_len 2 +#define reg_clk_sel_lsb 0 +#define r_reg_tog_sel 0xF9DA +#define reg_tog_sel_pos 0 +#define reg_tog_sel_len 2 +#define reg_tog_sel_lsb 0 +#define p_reg_ts_str_ignore 0xF9DB +#define reg_ts_str_ignore_pos 0 +#define reg_ts_str_ignore_len 1 +#define reg_ts_str_ignore_lsb 0 +#define p_reg_ts_frm_ignore 0xF9DC +#define reg_ts_frm_ignore_pos 0 +#define reg_ts_frm_ignore_len 1 +#define reg_ts_frm_ignore_lsb 0 +#define p_reg_clk_sel_fix 0xF9DD +#define reg_clk_sel_fix_pos 0 +#define reg_clk_sel_fix_len 2 +#define reg_clk_sel_fix_lsb 0 +#define p_reg_tog_sel_fix 0xF9DE +#define reg_tog_sel_fix_pos 0 +#define reg_tog_sel_fix_len 2 +#define reg_tog_sel_fix_lsb 0 +#define p_reg_en_fix 0xF9DF +#define reg_en_fix_pos 0 +#define reg_en_fix_len 1 +#define reg_en_fix_lsb 0 +#define p_reg_check_tpsd_hier 0xF9E0 +#define reg_check_tpsd_hier_pos 0 +#define reg_check_tpsd_hier_len 1 +#define reg_check_tpsd_hier_lsb 0 +#define p_reg_p_i2s_master_mode 0xF9E1 +#define reg_p_i2s_master_mode_pos 0 +#define reg_p_i2s_master_mode_len 1 +#define reg_p_i2s_master_mode_lsb 0 +#define p_reg_p_sc_lr_ratio 0xF9E2 +#define reg_p_sc_lr_ratio_pos 0 +#define reg_p_sc_lr_ratio_len 2 +#define reg_p_sc_lr_ratio_lsb 0 +#define p_reg_p_i2s_fs_type 0xF9E2 +#define reg_p_i2s_fs_type_pos 2 +#define reg_p_i2s_fs_type_len 2 +#define reg_p_i2s_fs_type_lsb 0 +#define r_reg_r_pp_fullq 0xF9E3 +#define reg_r_pp_fullq_pos 0 +#define reg_r_pp_fullq_len 1 +#define reg_r_pp_fullq_lsb 0 +#define p_reg_r_ccir_rst 0xF9E3 +#define reg_r_ccir_rst_pos 1 +#define reg_r_ccir_rst_len 1 +#define reg_r_ccir_rst_lsb 0 +#define p_reg_p_full_en 0xF9E3 +#define reg_p_full_en_pos 2 +#define reg_p_full_en_len 1 +#define reg_p_full_en_lsb 0 +#define p_reg_p_vbi_dis 0xF9E3 +#define reg_p_vbi_dis_pos 3 +#define reg_p_vbi_dis_len 1 +#define reg_p_vbi_dis_lsb 0 +#define p_reg_p_ccir_all 0xF9E3 +#define reg_p_ccir_all_pos 4 +#define reg_p_ccir_all_len 1 +#define reg_p_ccir_all_lsb 0 +#define p_reg_p_ccir_vbi_raw_en 0xF9E3 +#define reg_p_ccir_vbi_raw_en_pos 5 +#define reg_p_ccir_vbi_raw_en_len 1 +#define reg_p_ccir_vbi_raw_en_lsb 0 +#define p_reg_err_byte_en 0xF9E4 +#define reg_err_byte_en_pos 0 +#define reg_err_byte_en_len 1 +#define reg_err_byte_en_lsb 0 +#define p_reg_mp2_f_adc_7_0 0xF9E5 +#define reg_mp2_f_adc_7_0_pos 0 +#define reg_mp2_f_adc_7_0_len 8 +#define reg_mp2_f_adc_7_0_lsb 0 +#define p_reg_mp2_f_adc_15_8 0xF9E6 +#define reg_mp2_f_adc_15_8_pos 0 +#define reg_mp2_f_adc_15_8_len 8 +#define reg_mp2_f_adc_15_8_lsb 8 +#define p_reg_mp2_f_adc_23_16 0xF9E7 +#define reg_mp2_f_adc_23_16_pos 0 +#define reg_mp2_f_adc_23_16_len 8 +#define reg_mp2_f_adc_23_16_lsb 16 +#define p_reg_set_util 0xF9E8 +#define reg_set_util_pos 0 +#define reg_set_util_len 8 +#define reg_set_util_lsb 0 +#define r_reg_err_byte 0xF9E9 +#define reg_err_byte_pos 0 +#define reg_err_byte_len 8 +#define reg_err_byte_lsb 0 +#define p_reg_p_ln_num1 0xF9EA +#define reg_p_ln_num1_pos 0 +#define reg_p_ln_num1_len 5 +#define reg_p_ln_num1_lsb 0 +#define p_reg_p_ln_num2_2_0 0xF9EA +#define reg_p_ln_num2_2_0_pos 5 +#define reg_p_ln_num2_2_0_len 3 +#define reg_p_ln_num2_2_0_lsb 0 +#define p_reg_p_ln_num2_4_3 0xF9EB +#define reg_p_ln_num2_4_3_pos 0 +#define reg_p_ln_num2_4_3_len 2 +#define reg_p_ln_num2_4_3_lsb 3 +#define p_reg_p_ln_num3_5_0 0xF9EB +#define reg_p_ln_num3_5_0_pos 2 +#define reg_p_ln_num3_5_0_len 6 +#define reg_p_ln_num3_5_0_lsb 0 +#define p_reg_p_ln_num3_8_6 0xF9EC +#define reg_p_ln_num3_8_6_pos 0 +#define reg_p_ln_num3_8_6_len 3 +#define reg_p_ln_num3_8_6_lsb 6 +#define p_reg_p_ln_num4_4_0 0xF9EC +#define reg_p_ln_num4_4_0_pos 3 +#define reg_p_ln_num4_4_0_len 5 +#define reg_p_ln_num4_4_0_lsb 0 +#define p_reg_p_ln_num4_8_5 0xF9ED +#define reg_p_ln_num4_8_5_pos 0 +#define reg_p_ln_num4_8_5_len 4 +#define reg_p_ln_num4_8_5_lsb 5 +#define p_reg_p_ln_num5_3_0 0xF9ED +#define reg_p_ln_num5_3_0_pos 4 +#define reg_p_ln_num5_3_0_len 4 +#define reg_p_ln_num5_3_0_lsb 0 +#define p_reg_p_ln_num5_8_4 0xF9EE +#define reg_p_ln_num5_8_4_pos 0 +#define reg_p_ln_num5_8_4_len 5 +#define reg_p_ln_num5_8_4_lsb 4 +#define p_reg_p_ln_num6_2_0 0xF9EE +#define reg_p_ln_num6_2_0_pos 5 +#define reg_p_ln_num6_2_0_len 3 +#define reg_p_ln_num6_2_0_lsb 0 +#define p_reg_p_ln_num6_8_3 0xF9EF +#define reg_p_ln_num6_8_3_pos 0 +#define reg_p_ln_num6_8_3_len 6 +#define reg_p_ln_num6_8_3_lsb 3 +#define p_reg_p_pixel_num_7_0 0xF9F0 +#define reg_p_pixel_num_7_0_pos 0 +#define reg_p_pixel_num_7_0_len 8 +#define reg_p_pixel_num_7_0_lsb 0 +#define p_reg_p_pixel_num_10_8 0xF9F1 +#define reg_p_pixel_num_10_8_pos 0 +#define reg_p_pixel_num_10_8_len 3 +#define reg_p_pixel_num_10_8_lsb 8 +#define p_reg_p_ccir_yuv_en 0xF9F1 +#define reg_p_ccir_yuv_en_pos 3 +#define reg_p_ccir_yuv_en_len 1 +#define reg_p_ccir_yuv_en_lsb 0 +#define p_reg_p_ccir_size_sft 0xF9F1 +#define reg_p_ccir_size_sft_pos 4 +#define reg_p_ccir_size_sft_len 2 +#define reg_p_ccir_size_sft_lsb 0 +#define p_reg_p_psb_cnt_sft 0xF9F1 +#define reg_p_psb_cnt_sft_pos 6 +#define reg_p_psb_cnt_sft_len 2 +#define reg_p_psb_cnt_sft_lsb 0 +#define p_reg_p_tpsd_lock_trigger 0xF9F2 +#define reg_p_tpsd_lock_trigger_pos 0 +#define reg_p_tpsd_lock_trigger_len 1 +#define reg_p_tpsd_lock_trigger_lsb 0 +#define p_reg_p_ccir_clk_sel 0xF9F3 +#define reg_p_ccir_clk_sel_pos 0 +#define reg_p_ccir_clk_sel_len 1 +#define reg_p_ccir_clk_sel_lsb 0 +#define p_reg_i2c_16_8_data_sel 0xFB00 +#define reg_i2c_16_8_data_sel_pos 0 +#define reg_i2c_16_8_data_sel_len 1 +#define reg_i2c_16_8_data_sel_lsb 0 +#define p_reg_i2c_slave_trigger_byte 0xFB01 +#define reg_i2c_slave_trigger_byte_pos 0 +#define reg_i2c_slave_trigger_byte_len 1 +#define reg_i2c_slave_trigger_byte_lsb 0 +#define p_reg_wdti_level 0xFB05 +#define reg_wdti_level_pos 0 +#define reg_wdti_level_len 1 +#define reg_wdti_level_lsb 0 +#define p_reg_rssi_avg_sel_lat 0xFB06 +#define reg_rssi_avg_sel_lat_pos 0 +#define reg_rssi_avg_sel_lat_len 2 +#define reg_rssi_avg_sel_lat_lsb 0 +#define r_ofsm_rssi_avg_7_0 0xFB07 +#define ofsm_rssi_avg_7_0_pos 0 +#define ofsm_rssi_avg_7_0_len 8 +#define ofsm_rssi_avg_7_0_lsb 0 +#define r_ofsm_rssi_avg_9_8 0xFB08 +#define ofsm_rssi_avg_9_8_pos 0 +#define ofsm_rssi_avg_9_8_len 2 +#define ofsm_rssi_avg_9_8_lsb 8 +#define r_ofsm_mbist_fail_mon51 0xFB09 +#define ofsm_mbist_fail_mon51_pos 0 +#define ofsm_mbist_fail_mon51_len 1 +#define ofsm_mbist_fail_mon51_lsb 0 +#define r_ofsm_mbist_fail_com 0xFB0A +#define ofsm_mbist_fail_com_pos 0 +#define ofsm_mbist_fail_com_len 1 +#define ofsm_mbist_fail_com_lsb 0 +#define r_ofsm_mbist_fail_fft 0xFB0B +#define ofsm_mbist_fail_fft_pos 0 +#define ofsm_mbist_fail_fft_len 1 +#define ofsm_mbist_fail_fft_lsb 0 +#define r_ofsm_mbist_fail_fd 0xFB0C +#define ofsm_mbist_fail_fd_pos 0 +#define ofsm_mbist_fail_fd_len 1 +#define ofsm_mbist_fail_fd_lsb 0 +#define r_ofsm_mbist_fail_link 0xFB0D +#define ofsm_mbist_fail_link_pos 0 +#define ofsm_mbist_fail_link_len 1 +#define ofsm_mbist_fail_link_lsb 0 +#define r_ofsm_mbist_fail_mpe 0xFB0E +#define ofsm_mbist_fail_mpe_pos 0 +#define ofsm_mbist_fail_mpe_len 1 +#define ofsm_mbist_fail_mpe_lsb 0 +#define r_ofsm_mbist_done_mpe 0xFB0F +#define ofsm_mbist_done_mpe_pos 0 +#define ofsm_mbist_done_mpe_len 1 +#define ofsm_mbist_done_mpe_lsb 0 +#define r_ofsm_mbist_mode_mpe 0xFB10 +#define ofsm_mbist_mode_mpe_pos 0 +#define ofsm_mbist_mode_mpe_len 1 +#define ofsm_mbist_mode_mpe_lsb 0 +#define p_ofsm_cmd_reg 0xFB11 +#define ofsm_cmd_reg_pos 0 +#define ofsm_cmd_reg_len 8 +#define ofsm_cmd_reg_lsb 0 +#define p_ofsm_addr_reg_h 0xFB12 +#define ofsm_addr_reg_h_pos 0 +#define ofsm_addr_reg_h_len 8 +#define ofsm_addr_reg_h_lsb 0 +#define p_ofsm_addr_reg_l 0xFB13 +#define ofsm_addr_reg_l_pos 0 +#define ofsm_addr_reg_l_len 8 +#define ofsm_addr_reg_l_lsb 0 +#define p_ofsm_data_reg_0 0xFB14 +#define ofsm_data_reg_0_pos 0 +#define ofsm_data_reg_0_len 8 +#define ofsm_data_reg_0_lsb 0 +#define p_ofsm_data_reg_1 0xFB15 +#define ofsm_data_reg_1_pos 0 +#define ofsm_data_reg_1_len 8 +#define ofsm_data_reg_1_lsb 0 +#define p_ofsm_data_reg_2 0xFB16 +#define ofsm_data_reg_2_pos 0 +#define ofsm_data_reg_2_len 8 +#define ofsm_data_reg_2_lsb 0 +#define p_ofsm_data_reg_3 0xFB17 +#define ofsm_data_reg_3_pos 0 +#define ofsm_data_reg_3_len 8 +#define ofsm_data_reg_3_lsb 0 +#define p_ofsm_data_reg_4 0xFB18 +#define ofsm_data_reg_4_pos 0 +#define ofsm_data_reg_4_len 8 +#define ofsm_data_reg_4_lsb 0 +#define p_ofsm_data_reg_5 0xFB19 +#define ofsm_data_reg_5_pos 0 +#define ofsm_data_reg_5_len 8 +#define ofsm_data_reg_5_lsb 0 +#define p_ofsm_data_reg_6 0xFB1A +#define ofsm_data_reg_6_pos 0 +#define ofsm_data_reg_6_len 8 +#define ofsm_data_reg_6_lsb 0 +#define p_ofsm_data_reg_7 0xFB1B +#define ofsm_data_reg_7_pos 0 +#define ofsm_data_reg_7_len 8 +#define ofsm_data_reg_7_lsb 0 +#define p_ofsm_data_reg_8 0xFB1C +#define ofsm_data_reg_8_pos 0 +#define ofsm_data_reg_8_len 8 +#define ofsm_data_reg_8_lsb 0 +#define p_ofsm_data_reg_9 0xFB1D +#define ofsm_data_reg_9_pos 0 +#define ofsm_data_reg_9_len 8 +#define ofsm_data_reg_9_lsb 0 +#define p_ofsm_data_reg_10 0xFB1E +#define ofsm_data_reg_10_pos 0 +#define ofsm_data_reg_10_len 8 +#define ofsm_data_reg_10_lsb 0 +#define p_ofsm_data_reg_11 0xFB1F +#define ofsm_data_reg_11_pos 0 +#define ofsm_data_reg_11_len 8 +#define ofsm_data_reg_11_lsb 0 +#define p_ofsm_data_reg_12 0xFB20 +#define ofsm_data_reg_12_pos 0 +#define ofsm_data_reg_12_len 8 +#define ofsm_data_reg_12_lsb 0 +#define p_ofsm_data_reg_13 0xFB21 +#define ofsm_data_reg_13_pos 0 +#define ofsm_data_reg_13_len 8 +#define ofsm_data_reg_13_lsb 0 +#define p_ofsm_data_reg_14 0xFB22 +#define ofsm_data_reg_14_pos 0 +#define ofsm_data_reg_14_len 8 +#define ofsm_data_reg_14_lsb 0 +#define p_ofsm_data_reg_15 0xFB23 +#define ofsm_data_reg_15_pos 0 +#define ofsm_data_reg_15_len 8 +#define ofsm_data_reg_15_lsb 0 +#define p_reg_afe_mem0 0xFB24 +#define reg_afe_mem0_pos 0 +#define reg_afe_mem0_len 8 +#define reg_afe_mem0_lsb 0 +#define p_reg_afe_mem1 0xFB25 +#define reg_afe_mem1_pos 0 +#define reg_afe_mem1_len 8 +#define reg_afe_mem1_lsb 0 +#define p_reg_afe_mem2 0xFB26 +#define reg_afe_mem2_pos 0 +#define reg_afe_mem2_len 8 +#define reg_afe_mem2_lsb 0 +#define p_reg_afe_mem3 0xFB27 +#define reg_afe_mem3_pos 0 +#define reg_afe_mem3_len 8 +#define reg_afe_mem3_lsb 0 +#define p_reg_afe_mem4 0xFB28 +#define reg_afe_mem4_pos 0 +#define reg_afe_mem4_len 8 +#define reg_afe_mem4_lsb 0 +#define p_reg_afe_mem5 0xFB29 +#define reg_afe_mem5_pos 0 +#define reg_afe_mem5_len 8 +#define reg_afe_mem5_lsb 0 +#define p_reg_afe_mem6 0xFB2A +#define reg_afe_mem6_pos 0 +#define reg_afe_mem6_len 8 +#define reg_afe_mem6_lsb 0 +#define p_reg_afe_mem7 0xFB2B +#define reg_afe_mem7_pos 0 +#define reg_afe_mem7_len 8 +#define reg_afe_mem7_lsb 0 +#define p_reg_i2cbootreq 0xFB2C +#define reg_i2cbootreq_pos 0 +#define reg_i2cbootreq_len 1 +#define reg_i2cbootreq_lsb 0 +#define p_reg_rst_i2cm 0xFB30 +#define reg_rst_i2cm_pos 0 +#define reg_rst_i2cm_len 1 +#define reg_rst_i2cm_lsb 0 +#define p_reg_rst_i2cs 0xFB31 +#define reg_rst_i2cs_pos 0 +#define reg_rst_i2cs_len 1 +#define reg_rst_i2cs_lsb 0 +#define r_reg_top_gpioscli 0xFB32 +#define reg_top_gpioscli_pos 0 +#define reg_top_gpioscli_len 1 +#define reg_top_gpioscli_lsb 0 +#define p_reg_top_gpiosclo 0xFB33 +#define reg_top_gpiosclo_pos 0 +#define reg_top_gpiosclo_len 1 +#define reg_top_gpiosclo_lsb 0 +#define p_reg_top_gpiosclen 0xFB34 +#define reg_top_gpiosclen_pos 0 +#define reg_top_gpiosclen_len 1 +#define reg_top_gpiosclen_lsb 0 +#define p_reg_top_gpiosclon 0xFB35 +#define reg_top_gpiosclon_pos 0 +#define reg_top_gpiosclon_len 1 +#define reg_top_gpiosclon_lsb 0 +#define r_reg_top_gpiosdai 0xFB36 +#define reg_top_gpiosdai_pos 0 +#define reg_top_gpiosdai_len 1 +#define reg_top_gpiosdai_lsb 0 +#define p_reg_top_gpiosdao 0xFB37 +#define reg_top_gpiosdao_pos 0 +#define reg_top_gpiosdao_len 1 +#define reg_top_gpiosdao_lsb 0 +#define p_reg_top_gpiosdaen 0xFB38 +#define reg_top_gpiosdaen_pos 0 +#define reg_top_gpiosdaen_len 1 +#define reg_top_gpiosdaen_lsb 0 +#define p_reg_top_gpiosdaon 0xFB39 +#define reg_top_gpiosdaon_pos 0 +#define reg_top_gpiosdaon_len 1 +#define reg_top_gpiosdaon_lsb 0 +#define p_reg_fix_rom_en 0xFB3A +#define reg_fix_rom_en_pos 0 +#define reg_fix_rom_en_len 1 +#define reg_fix_rom_en_lsb 0 +#define p_reg_ofsm_bug_addh_0 0xFB3B +#define reg_ofsm_bug_addh_0_pos 0 +#define reg_ofsm_bug_addh_0_len 8 +#define reg_ofsm_bug_addh_0_lsb 0 +#define p_reg_ofsm_bug_addl_0 0xFB3C +#define reg_ofsm_bug_addl_0_pos 0 +#define reg_ofsm_bug_addl_0_len 8 +#define reg_ofsm_bug_addl_0_lsb 0 +#define p_reg_ofsm_bug_addh_1 0xFB3D +#define reg_ofsm_bug_addh_1_pos 0 +#define reg_ofsm_bug_addh_1_len 8 +#define reg_ofsm_bug_addh_1_lsb 0 +#define p_reg_ofsm_bug_addl_1 0xFB3E +#define reg_ofsm_bug_addl_1_pos 0 +#define reg_ofsm_bug_addl_1_len 8 +#define reg_ofsm_bug_addl_1_lsb 0 +#define p_reg_ofsm_bug_addh_2 0xFB3F +#define reg_ofsm_bug_addh_2_pos 0 +#define reg_ofsm_bug_addh_2_len 8 +#define reg_ofsm_bug_addh_2_lsb 0 +#define p_reg_ofsm_bug_addl_2 0xFB40 +#define reg_ofsm_bug_addl_2_pos 0 +#define reg_ofsm_bug_addl_2_len 8 +#define reg_ofsm_bug_addl_2_lsb 0 +#define p_reg_ofsm_bug_addh_3 0xFB41 +#define reg_ofsm_bug_addh_3_pos 0 +#define reg_ofsm_bug_addh_3_len 8 +#define reg_ofsm_bug_addh_3_lsb 0 +#define p_reg_ofsm_bug_addl_3 0xFB42 +#define reg_ofsm_bug_addl_3_pos 0 +#define reg_ofsm_bug_addl_3_len 8 +#define reg_ofsm_bug_addl_3_lsb 0 +#define p_reg_ofsm_bug_addh_4 0xFB43 +#define reg_ofsm_bug_addh_4_pos 0 +#define reg_ofsm_bug_addh_4_len 8 +#define reg_ofsm_bug_addh_4_lsb 0 +#define p_reg_ofsm_bug_addl_4 0xFB44 +#define reg_ofsm_bug_addl_4_pos 0 +#define reg_ofsm_bug_addl_4_len 8 +#define reg_ofsm_bug_addl_4_lsb 0 +#define p_reg_ofsm_bug_addh_5 0xFB45 +#define reg_ofsm_bug_addh_5_pos 0 +#define reg_ofsm_bug_addh_5_len 8 +#define reg_ofsm_bug_addh_5_lsb 0 +#define p_reg_ofsm_bug_addl_5 0xFB46 +#define reg_ofsm_bug_addl_5_pos 0 +#define reg_ofsm_bug_addl_5_len 8 +#define reg_ofsm_bug_addl_5_lsb 0 +#define p_reg_ofsm_bug_addh_6 0xFB47 +#define reg_ofsm_bug_addh_6_pos 0 +#define reg_ofsm_bug_addh_6_len 8 +#define reg_ofsm_bug_addh_6_lsb 0 +#define p_reg_ofsm_bug_addl_6 0xFB48 +#define reg_ofsm_bug_addl_6_pos 0 +#define reg_ofsm_bug_addl_6_len 8 +#define reg_ofsm_bug_addl_6_lsb 0 +#define p_reg_ofsm_bug_addh_7 0xFB49 +#define reg_ofsm_bug_addh_7_pos 0 +#define reg_ofsm_bug_addh_7_len 8 +#define reg_ofsm_bug_addh_7_lsb 0 +#define p_reg_ofsm_bug_addl_7 0xFB4A +#define reg_ofsm_bug_addl_7_pos 0 +#define reg_ofsm_bug_addl_7_len 8 +#define reg_ofsm_bug_addl_7_lsb 0 +#define p_reg_ofsm_bug_addh_8 0xFB4B +#define reg_ofsm_bug_addh_8_pos 0 +#define reg_ofsm_bug_addh_8_len 8 +#define reg_ofsm_bug_addh_8_lsb 0 +#define p_reg_ofsm_bug_addl_8 0xFB4C +#define reg_ofsm_bug_addl_8_pos 0 +#define reg_ofsm_bug_addl_8_len 8 +#define reg_ofsm_bug_addl_8_lsb 0 +#define p_reg_ofsm_bug_addh_9 0xFB4D +#define reg_ofsm_bug_addh_9_pos 0 +#define reg_ofsm_bug_addh_9_len 8 +#define reg_ofsm_bug_addh_9_lsb 0 +#define p_reg_ofsm_bug_addl_9 0xFB4E +#define reg_ofsm_bug_addl_9_pos 0 +#define reg_ofsm_bug_addl_9_len 8 +#define reg_ofsm_bug_addl_9_lsb 0 +#define p_reg_ofsm_bug_addh_10 0xFB4F +#define reg_ofsm_bug_addh_10_pos 0 +#define reg_ofsm_bug_addh_10_len 8 +#define reg_ofsm_bug_addh_10_lsb 0 +#define p_reg_ofsm_bug_addl_10 0xFB50 +#define reg_ofsm_bug_addl_10_pos 0 +#define reg_ofsm_bug_addl_10_len 8 +#define reg_ofsm_bug_addl_10_lsb 0 +#define p_reg_ofsm_bug_addh_11 0xFB51 +#define reg_ofsm_bug_addh_11_pos 0 +#define reg_ofsm_bug_addh_11_len 8 +#define reg_ofsm_bug_addh_11_lsb 0 +#define p_reg_ofsm_bug_addl_11 0xFB52 +#define reg_ofsm_bug_addl_11_pos 0 +#define reg_ofsm_bug_addl_11_len 8 +#define reg_ofsm_bug_addl_11_lsb 0 +#define p_reg_ofsm_bug_addh_12 0xFB53 +#define reg_ofsm_bug_addh_12_pos 0 +#define reg_ofsm_bug_addh_12_len 8 +#define reg_ofsm_bug_addh_12_lsb 0 +#define p_reg_ofsm_bug_addl_12 0xFB54 +#define reg_ofsm_bug_addl_12_pos 0 +#define reg_ofsm_bug_addl_12_len 8 +#define reg_ofsm_bug_addl_12_lsb 0 +#define p_reg_ofsm_bug_addh_13 0xFB55 +#define reg_ofsm_bug_addh_13_pos 0 +#define reg_ofsm_bug_addh_13_len 8 +#define reg_ofsm_bug_addh_13_lsb 0 +#define p_reg_ofsm_bug_addl_13 0xFB56 +#define reg_ofsm_bug_addl_13_pos 0 +#define reg_ofsm_bug_addl_13_len 8 +#define reg_ofsm_bug_addl_13_lsb 0 +#define p_reg_ofsm_bug_addh_14 0xFB57 +#define reg_ofsm_bug_addh_14_pos 0 +#define reg_ofsm_bug_addh_14_len 8 +#define reg_ofsm_bug_addh_14_lsb 0 +#define p_reg_ofsm_bug_addl_14 0xFB58 +#define reg_ofsm_bug_addl_14_pos 0 +#define reg_ofsm_bug_addl_14_len 8 +#define reg_ofsm_bug_addl_14_lsb 0 +#define p_reg_ofsm_bug_addh_15 0xFB59 +#define reg_ofsm_bug_addh_15_pos 0 +#define reg_ofsm_bug_addh_15_len 8 +#define reg_ofsm_bug_addh_15_lsb 0 +#define p_reg_ofsm_bug_addl_15 0xFB5A +#define reg_ofsm_bug_addl_15_pos 0 +#define reg_ofsm_bug_addl_15_len 8 +#define reg_ofsm_bug_addl_15_lsb 0 +#define p_reg_ofsm_jmp_addh_0 0xFB5B +#define reg_ofsm_jmp_addh_0_pos 0 +#define reg_ofsm_jmp_addh_0_len 8 +#define reg_ofsm_jmp_addh_0_lsb 0 +#define p_reg_ofsm_jmp_addl_0 0xFB5C +#define reg_ofsm_jmp_addl_0_pos 0 +#define reg_ofsm_jmp_addl_0_len 8 +#define reg_ofsm_jmp_addl_0_lsb 0 +#define p_reg_ofsm_jmp_addh_1 0xFB5D +#define reg_ofsm_jmp_addh_1_pos 0 +#define reg_ofsm_jmp_addh_1_len 8 +#define reg_ofsm_jmp_addh_1_lsb 0 +#define p_reg_ofsm_jmp_addl_1 0xFB5E +#define reg_ofsm_jmp_addl_1_pos 0 +#define reg_ofsm_jmp_addl_1_len 8 +#define reg_ofsm_jmp_addl_1_lsb 0 +#define p_reg_ofsm_jmp_addh_2 0xFB5F +#define reg_ofsm_jmp_addh_2_pos 0 +#define reg_ofsm_jmp_addh_2_len 8 +#define reg_ofsm_jmp_addh_2_lsb 0 +#define p_reg_ofsm_jmp_addl_2 0xFB60 +#define reg_ofsm_jmp_addl_2_pos 0 +#define reg_ofsm_jmp_addl_2_len 8 +#define reg_ofsm_jmp_addl_2_lsb 0 +#define p_reg_ofsm_jmp_addh_3 0xFB61 +#define reg_ofsm_jmp_addh_3_pos 0 +#define reg_ofsm_jmp_addh_3_len 8 +#define reg_ofsm_jmp_addh_3_lsb 0 +#define p_reg_ofsm_jmp_addl_3 0xFB62 +#define reg_ofsm_jmp_addl_3_pos 0 +#define reg_ofsm_jmp_addl_3_len 8 +#define reg_ofsm_jmp_addl_3_lsb 0 +#define p_reg_ofsm_jmp_addh_4 0xFB63 +#define reg_ofsm_jmp_addh_4_pos 0 +#define reg_ofsm_jmp_addh_4_len 8 +#define reg_ofsm_jmp_addh_4_lsb 0 +#define p_reg_ofsm_jmp_addl_4 0xFB64 +#define reg_ofsm_jmp_addl_4_pos 0 +#define reg_ofsm_jmp_addl_4_len 8 +#define reg_ofsm_jmp_addl_4_lsb 0 +#define p_reg_ofsm_jmp_addh_5 0xFB65 +#define reg_ofsm_jmp_addh_5_pos 0 +#define reg_ofsm_jmp_addh_5_len 8 +#define reg_ofsm_jmp_addh_5_lsb 0 +#define p_reg_ofsm_jmp_addl_5 0xFB66 +#define reg_ofsm_jmp_addl_5_pos 0 +#define reg_ofsm_jmp_addl_5_len 8 +#define reg_ofsm_jmp_addl_5_lsb 0 +#define p_reg_ofsm_jmp_addh_6 0xFB67 +#define reg_ofsm_jmp_addh_6_pos 0 +#define reg_ofsm_jmp_addh_6_len 8 +#define reg_ofsm_jmp_addh_6_lsb 0 +#define p_reg_ofsm_jmp_addl_6 0xFB68 +#define reg_ofsm_jmp_addl_6_pos 0 +#define reg_ofsm_jmp_addl_6_len 8 +#define reg_ofsm_jmp_addl_6_lsb 0 +#define p_reg_ofsm_jmp_addh_7 0xFB69 +#define reg_ofsm_jmp_addh_7_pos 0 +#define reg_ofsm_jmp_addh_7_len 8 +#define reg_ofsm_jmp_addh_7_lsb 0 +#define p_reg_ofsm_jmp_addl_7 0xFB6A +#define reg_ofsm_jmp_addl_7_pos 0 +#define reg_ofsm_jmp_addl_7_len 8 +#define reg_ofsm_jmp_addl_7_lsb 0 +#define p_reg_ofsm_jmp_addh_8 0xFB6B +#define reg_ofsm_jmp_addh_8_pos 0 +#define reg_ofsm_jmp_addh_8_len 8 +#define reg_ofsm_jmp_addh_8_lsb 0 +#define p_reg_ofsm_jmp_addl_8 0xFB6C +#define reg_ofsm_jmp_addl_8_pos 0 +#define reg_ofsm_jmp_addl_8_len 8 +#define reg_ofsm_jmp_addl_8_lsb 0 +#define p_reg_ofsm_jmp_addh_9 0xFB6D +#define reg_ofsm_jmp_addh_9_pos 0 +#define reg_ofsm_jmp_addh_9_len 8 +#define reg_ofsm_jmp_addh_9_lsb 0 +#define p_reg_ofsm_jmp_addl_9 0xFB6E +#define reg_ofsm_jmp_addl_9_pos 0 +#define reg_ofsm_jmp_addl_9_len 8 +#define reg_ofsm_jmp_addl_9_lsb 0 +#define p_reg_ofsm_jmp_addh_10 0xFB6F +#define reg_ofsm_jmp_addh_10_pos 0 +#define reg_ofsm_jmp_addh_10_len 8 +#define reg_ofsm_jmp_addh_10_lsb 0 +#define p_reg_ofsm_jmp_addl_10 0xFB70 +#define reg_ofsm_jmp_addl_10_pos 0 +#define reg_ofsm_jmp_addl_10_len 8 +#define reg_ofsm_jmp_addl_10_lsb 0 +#define p_reg_ofsm_jmp_addh_11 0xFB71 +#define reg_ofsm_jmp_addh_11_pos 0 +#define reg_ofsm_jmp_addh_11_len 8 +#define reg_ofsm_jmp_addh_11_lsb 0 +#define p_reg_ofsm_jmp_addl_11 0xFB72 +#define reg_ofsm_jmp_addl_11_pos 0 +#define reg_ofsm_jmp_addl_11_len 8 +#define reg_ofsm_jmp_addl_11_lsb 0 +#define p_reg_ofsm_jmp_addh_12 0xFB73 +#define reg_ofsm_jmp_addh_12_pos 0 +#define reg_ofsm_jmp_addh_12_len 8 +#define reg_ofsm_jmp_addh_12_lsb 0 +#define p_reg_ofsm_jmp_addl_12 0xFB74 +#define reg_ofsm_jmp_addl_12_pos 0 +#define reg_ofsm_jmp_addl_12_len 8 +#define reg_ofsm_jmp_addl_12_lsb 0 +#define p_reg_ofsm_jmp_addh_13 0xFB75 +#define reg_ofsm_jmp_addh_13_pos 0 +#define reg_ofsm_jmp_addh_13_len 8 +#define reg_ofsm_jmp_addh_13_lsb 0 +#define p_reg_ofsm_jmp_addl_13 0xFB76 +#define reg_ofsm_jmp_addl_13_pos 0 +#define reg_ofsm_jmp_addl_13_len 8 +#define reg_ofsm_jmp_addl_13_lsb 0 +#define p_reg_ofsm_jmp_addh_14 0xFB77 +#define reg_ofsm_jmp_addh_14_pos 0 +#define reg_ofsm_jmp_addh_14_len 8 +#define reg_ofsm_jmp_addh_14_lsb 0 +#define p_reg_ofsm_jmp_addl_14 0xFB78 +#define reg_ofsm_jmp_addl_14_pos 0 +#define reg_ofsm_jmp_addl_14_len 8 +#define reg_ofsm_jmp_addl_14_lsb 0 +#define p_reg_ofsm_jmp_addh_15 0xFB79 +#define reg_ofsm_jmp_addh_15_pos 0 +#define reg_ofsm_jmp_addh_15_len 8 +#define reg_ofsm_jmp_addh_15_lsb 0 +#define p_reg_ofsm_jmp_addl_15 0xFB7A +#define reg_ofsm_jmp_addl_15_pos 0 +#define reg_ofsm_jmp_addl_15_len 8 +#define reg_ofsm_jmp_addl_15_lsb 0 +#define p_reg_sw_mon51 0xFB7B +#define reg_sw_mon51_pos 0 +#define reg_sw_mon51_len 7 +#define reg_sw_mon51_lsb 0 +#define p_reg_ofdm_mon51_flag 0xFB7C +#define reg_ofdm_mon51_flag_pos 0 +#define reg_ofdm_mon51_flag_len 1 +#define reg_ofdm_mon51_flag_lsb 0 +#define p_reg_ofdm_force_mon51 0xFB7D +#define reg_ofdm_force_mon51_pos 0 +#define reg_ofdm_force_mon51_len 1 +#define reg_ofdm_force_mon51_lsb 0 +#define p_reg_ofdm_which_cpu 0xFB7E +#define reg_ofdm_which_cpu_pos 0 +#define reg_ofdm_which_cpu_len 1 +#define reg_ofdm_which_cpu_lsb 0 +#define p_reg_ofdm_code_ready 0xFB7F +#define reg_ofdm_code_ready_pos 0 +#define reg_ofdm_code_ready_len 1 +#define reg_ofdm_code_ready_lsb 0 +#define p_reg_ofdm_mailbox_wend 0xFB80 +#define reg_ofdm_mailbox_wend_pos 0 +#define reg_ofdm_mailbox_wend_len 1 +#define reg_ofdm_mailbox_wend_lsb 0 +#define r_reg_fast_slow_train 0xFB81 +#define reg_fast_slow_train_pos 0 +#define reg_fast_slow_train_len 1 +#define reg_fast_slow_train_lsb 0 +#define p_reg_ofdm_mailbox_wptr 0xFB82 +#define reg_ofdm_mailbox_wptr_pos 0 +#define reg_ofdm_mailbox_wptr_len 8 +#define reg_ofdm_mailbox_wptr_lsb 0 +#define p_reg_ofdm_mailbox_int 0xFB86 +#define reg_ofdm_mailbox_int_pos 0 +#define reg_ofdm_mailbox_int_len 1 +#define reg_ofdm_mailbox_int_lsb 0 +#define p_reg_ofdm_lnk2ofdm_int 0xFB87 +#define reg_ofdm_lnk2ofdm_int_pos 0 +#define reg_ofdm_lnk2ofdm_int_len 1 +#define reg_ofdm_lnk2ofdm_int_lsb 0 +#define p_reg_ofdm_ofdm2lnk_int 0xFB88 +#define reg_ofdm_ofdm2lnk_int_pos 0 +#define reg_ofdm_ofdm2lnk_int_len 1 +#define reg_ofdm_ofdm2lnk_int_lsb 0 +#define r_reg_load_ofdm_reg 0xFB8F +#define reg_load_ofdm_reg_pos 0 +#define reg_load_ofdm_reg_len 1 +#define reg_load_ofdm_reg_lsb 0 +#define p_reg_lnk_mbx_rd_length_7_0 0xFB90 +#define reg_lnk_mbx_rd_length_7_0_pos 0 +#define reg_lnk_mbx_rd_length_7_0_len 8 +#define reg_lnk_mbx_rd_length_7_0_lsb 0 +#define p_reg_lnk_mbx_rd_length_15_8 0xFB91 +#define reg_lnk_mbx_rd_length_15_8_pos 0 +#define reg_lnk_mbx_rd_length_15_8_len 8 +#define reg_lnk_mbx_rd_length_15_8_lsb 8 +#define p_reg_lnk_mbx_rd_length_17_16 0xFB92 +#define reg_lnk_mbx_rd_length_17_16_pos 0 +#define reg_lnk_mbx_rd_length_17_16_len 2 +#define reg_lnk_mbx_rd_length_17_16_lsb 16 +#define p_reg_lnk_rd_data_sel 0xFB93 +#define reg_lnk_rd_data_sel_pos 0 +#define reg_lnk_rd_data_sel_len 2 +#define reg_lnk_rd_data_sel_lsb 0 +#define p_reg_ofdm2lnk_data_7_0 0xFB96 +#define reg_ofdm2lnk_data_7_0_pos 0 +#define reg_ofdm2lnk_data_7_0_len 8 +#define reg_ofdm2lnk_data_7_0_lsb 0 +#define p_reg_ofdm2lnk_data_15_8 0xFB97 +#define reg_ofdm2lnk_data_15_8_pos 0 +#define reg_ofdm2lnk_data_15_8_len 8 +#define reg_ofdm2lnk_data_15_8_lsb 8 +#define p_reg_ofdm2lnk_data_23_16 0xFB98 +#define reg_ofdm2lnk_data_23_16_pos 0 +#define reg_ofdm2lnk_data_23_16_len 8 +#define reg_ofdm2lnk_data_23_16_lsb 16 +#define p_reg_ofdm2lnk_data_31_24 0xFB99 +#define reg_ofdm2lnk_data_31_24_pos 0 +#define reg_ofdm2lnk_data_31_24_len 8 +#define reg_ofdm2lnk_data_31_24_lsb 24 +#define p_reg_ofdm2lnk_data_39_32 0xFB9A +#define reg_ofdm2lnk_data_39_32_pos 0 +#define reg_ofdm2lnk_data_39_32_len 8 +#define reg_ofdm2lnk_data_39_32_lsb 32 +#define p_reg_ofdm2lnk_data_47_40 0xFB9B +#define reg_ofdm2lnk_data_47_40_pos 0 +#define reg_ofdm2lnk_data_47_40_len 8 +#define reg_ofdm2lnk_data_47_40_lsb 40 +#define p_reg_ofdm2lnk_data_55_48 0xFB9C +#define reg_ofdm2lnk_data_55_48_pos 0 +#define reg_ofdm2lnk_data_55_48_len 8 +#define reg_ofdm2lnk_data_55_48_lsb 48 +#define p_reg_ofdm2lnk_data_63_56 0xFB9D +#define reg_ofdm2lnk_data_63_56_pos 0 +#define reg_ofdm2lnk_data_63_56_len 8 +#define reg_ofdm2lnk_data_63_56_lsb 56 +#define p_reg_lnktoofdm_data_7_0 0xFB9E +#define reg_lnktoofdm_data_7_0_pos 0 +#define reg_lnktoofdm_data_7_0_len 8 +#define reg_lnktoofdm_data_7_0_lsb 0 +#define p_reg_lnktoofdm_data_15_8 0xFB9F +#define reg_lnktoofdm_data_15_8_pos 0 +#define reg_lnktoofdm_data_15_8_len 8 +#define reg_lnktoofdm_data_15_8_lsb 8 +#define p_reg_lnktoofdm_data_23_16 0xFBA0 +#define reg_lnktoofdm_data_23_16_pos 0 +#define reg_lnktoofdm_data_23_16_len 8 +#define reg_lnktoofdm_data_23_16_lsb 16 +#define p_reg_lnktoofdm_data_31_24 0xFBA1 +#define reg_lnktoofdm_data_31_24_pos 0 +#define reg_lnktoofdm_data_31_24_len 8 +#define reg_lnktoofdm_data_31_24_lsb 24 +#define p_reg_lnktoofdm_data_39_32 0xFBA2 +#define reg_lnktoofdm_data_39_32_pos 0 +#define reg_lnktoofdm_data_39_32_len 8 +#define reg_lnktoofdm_data_39_32_lsb 32 +#define p_reg_lnktoofdm_data_47_40 0xFBA3 +#define reg_lnktoofdm_data_47_40_pos 0 +#define reg_lnktoofdm_data_47_40_len 8 +#define reg_lnktoofdm_data_47_40_lsb 40 +#define p_reg_lnktoofdm_data_55_48 0xFBA4 +#define reg_lnktoofdm_data_55_48_pos 0 +#define reg_lnktoofdm_data_55_48_len 8 +#define reg_lnktoofdm_data_55_48_lsb 48 +#define p_reg_lnktoofdm_data_63_56 0xFBA5 +#define reg_lnktoofdm_data_63_56_pos 0 +#define reg_lnktoofdm_data_63_56_len 8 +#define reg_lnktoofdm_data_63_56_lsb 56 +#define p_reg_dbgif32_sel 0xFBA6 +#define reg_dbgif32_sel_pos 0 +#define reg_dbgif32_sel_len 2 +#define reg_dbgif32_sel_lsb 0 +#define p_reg_dyn1_clk 0xFBA7 +#define reg_dyn1_clk_pos 0 +#define reg_dyn1_clk_len 1 +#define reg_dyn1_clk_lsb 0 +#define p_reg_dyn0_clk 0xFBA8 +#define reg_dyn0_clk_pos 0 +#define reg_dyn0_clk_len 1 +#define reg_dyn0_clk_lsb 0 +#define p_reg_free_clk 0xFBA9 +#define reg_free_clk_pos 0 +#define reg_free_clk_len 1 +#define reg_free_clk_lsb 0 +#define p_reg_ofdm_stick_mem_end_7_0 0xFBAD +#define reg_ofdm_stick_mem_end_7_0_pos 0 +#define reg_ofdm_stick_mem_end_7_0_len 8 +#define reg_ofdm_stick_mem_end_7_0_lsb 0 +#define p_reg_ofdm_stick_mem_end_15_8 0xFBAE +#define reg_ofdm_stick_mem_end_15_8_pos 0 +#define reg_ofdm_stick_mem_end_15_8_len 8 +#define reg_ofdm_stick_mem_end_15_8_lsb 8 +#define p_reg_ofdm_cpu_reset 0xFBAF +#define reg_ofdm_cpu_reset_pos 0 +#define reg_ofdm_cpu_reset_len 1 +#define reg_ofdm_cpu_reset_lsb 0 +#define p_reg_ofdm_bank_float_en 0xFBB0 +#define reg_ofdm_bank_float_en_pos 0 +#define reg_ofdm_bank_float_en_len 1 +#define reg_ofdm_bank_float_en_lsb 0 +#define p_reg_ofdm_bank_float_start 0xFBB1 +#define reg_ofdm_bank_float_start_pos 0 +#define reg_ofdm_bank_float_start_len 8 +#define reg_ofdm_bank_float_start_lsb 0 +#define p_reg_ofdm_bank_float_stop 0xFBB2 +#define reg_ofdm_bank_float_stop_pos 0 +#define reg_ofdm_bank_float_stop_len 8 +#define reg_ofdm_bank_float_stop_lsb 0 +#define r_ofsm_bond0_i 0xFBB3 +#define ofsm_bond0_i_pos 0 +#define ofsm_bond0_i_len 1 +#define ofsm_bond0_i_lsb 0 +#define r_ofsm_bond1_i 0xFBB4 +#define ofsm_bond1_i_pos 0 +#define ofsm_bond1_i_len 1 +#define ofsm_bond1_i_lsb 0 +#define r_io_mux_pwron_clk_strap 0xD800 +#define io_mux_pwron_clk_strap_pos 0 +#define io_mux_pwron_clk_strap_len 4 +#define io_mux_pwron_clk_strap_lsb 0 +#define r_io_mux_pwron_mode_strap 0xD801 +#define io_mux_pwron_mode_strap_pos 0 +#define io_mux_pwron_mode_strap_len 4 +#define io_mux_pwron_mode_strap_lsb 0 +#define r_io_mux_pwron_hosta 0xD802 +#define io_mux_pwron_hosta_pos 0 +#define io_mux_pwron_hosta_len 1 +#define io_mux_pwron_hosta_lsb 0 +#define r_reg_top_revid 0xD803 +#define reg_top_revid_pos 0 +#define reg_top_revid_len 4 +#define reg_top_revid_lsb 0 +#define r_io_mux_bond0_i 0xD804 +#define io_mux_bond0_i_pos 0 +#define io_mux_bond0_i_len 1 +#define io_mux_bond0_i_lsb 0 +#define r_io_mux_bondu0_i 0xD805 +#define io_mux_bondu0_i_pos 0 +#define io_mux_bondu0_i_len 1 +#define io_mux_bondu0_i_lsb 0 +#define p_reg_ofsm_suspend 0xD806 +#define reg_ofsm_suspend_pos 0 +#define reg_ofsm_suspend_len 1 +#define reg_ofsm_suspend_lsb 0 +#define p_reg_tslice_off 0xD807 +#define reg_tslice_off_pos 0 +#define reg_tslice_off_len 1 +#define reg_tslice_off_lsb 0 +#define p_io_mux_wake_int 0xD808 +#define io_mux_wake_int_pos 0 +#define io_mux_wake_int_len 1 +#define io_mux_wake_int_lsb 0 +#define p_reg_top_pwrdw_hwen 0xD809 +#define reg_top_pwrdw_hwen_pos 0 +#define reg_top_pwrdw_hwen_len 1 +#define reg_top_pwrdw_hwen_lsb 0 +#define p_reg_top_pwrdw_inv 0xD80A +#define reg_top_pwrdw_inv_pos 0 +#define reg_top_pwrdw_inv_len 1 +#define reg_top_pwrdw_inv_lsb 0 +#define p_reg_top_pwrdw 0xD80B +#define reg_top_pwrdw_pos 0 +#define reg_top_pwrdw_len 1 +#define reg_top_pwrdw_lsb 0 +#define p_io_mux_wake_int_en 0xD80C +#define io_mux_wake_int_en_pos 0 +#define io_mux_wake_int_en_len 1 +#define io_mux_wake_int_en_lsb 0 +#define p_io_mux_pwrdw_int 0xD80D +#define io_mux_pwrdw_int_pos 0 +#define io_mux_pwrdw_int_len 1 +#define io_mux_pwrdw_int_lsb 0 +#define p_reg_top_adcdly 0xD80E +#define reg_top_adcdly_pos 0 +#define reg_top_adcdly_len 2 +#define reg_top_adcdly_lsb 0 +#define p_reg_top_debug 0xD80F +#define reg_top_debug_pos 0 +#define reg_top_debug_len 1 +#define reg_top_debug_lsb 0 +#define p_reg_top_pcout 0xD810 +#define reg_top_pcout_pos 0 +#define reg_top_pcout_len 1 +#define reg_top_pcout_lsb 0 +#define p_reg_top_rs232 0xD811 +#define reg_top_rs232_pos 0 +#define reg_top_rs232_len 1 +#define reg_top_rs232_lsb 0 +#define p_reg_iqmode 0xD812 +#define reg_iqmode_pos 0 +#define reg_iqmode_len 1 +#define reg_iqmode_lsb 0 +#define p_reg_top_rstfd 0xD813 +#define reg_top_rstfd_pos 0 +#define reg_top_rstfd_len 1 +#define reg_top_rstfd_lsb 0 +#define p_reg_sdio_clksel 0xD814 +#define reg_sdio_clksel_pos 0 +#define reg_sdio_clksel_len 1 +#define reg_sdio_clksel_lsb 0 +#define p_reg_utmi_clksel 0xD815 +#define reg_utmi_clksel_pos 0 +#define reg_utmi_clksel_len 8 +#define reg_utmi_clksel_lsb 0 +#define p_reg_top_suscnt 0xD816 +#define reg_top_suscnt_pos 0 +#define reg_top_suscnt_len 2 +#define reg_top_suscnt_lsb 0 +#define p_reg_top_dist2f 0xD817 +#define reg_top_dist2f_pos 0 +#define reg_top_dist2f_len 1 +#define reg_top_dist2f_lsb 0 +#define p_reg_top_extusb 0xD818 +#define reg_top_extusb_pos 0 +#define reg_top_extusb_len 1 +#define reg_top_extusb_lsb 0 +#define p_reg_top_adcfifo 0xD819 +#define reg_top_adcfifo_pos 0 +#define reg_top_adcfifo_len 1 +#define reg_top_adcfifo_lsb 0 +#define p_reg_top_clkoen 0xD81A +#define reg_top_clkoen_pos 0 +#define reg_top_clkoen_len 1 +#define reg_top_clkoen_lsb 0 +#define p_reg_top_stpck 0xD81B +#define reg_top_stpck_pos 0 +#define reg_top_stpck_len 1 +#define reg_top_stpck_lsb 0 +#define p_reg_top_freeck 0xD81C +#define reg_top_freeck_pos 0 +#define reg_top_freeck_len 1 +#define reg_top_freeck_lsb 0 +#define p_reg_top_dio_sel 0xD81D +#define reg_top_dio_sel_pos 0 +#define reg_top_dio_sel_len 1 +#define reg_top_dio_sel_lsb 0 +#define p_reg_top_int_en 0xD81E +#define reg_top_int_en_pos 0 +#define reg_top_int_en_len 1 +#define reg_top_int_en_lsb 0 +#define p_reg_top_int_inv 0xD81F +#define reg_top_int_inv_pos 0 +#define reg_top_int_inv_len 1 +#define reg_top_int_inv_lsb 0 +#define p_reg_tsip_clk_inv 0xD820 +#define reg_tsip_clk_inv_pos 0 +#define reg_tsip_clk_inv_len 1 +#define reg_tsip_clk_inv_lsb 0 +#define p_reg_ts_clk_inv 0xD821 +#define reg_ts_clk_inv_pos 0 +#define reg_ts_clk_inv_len 1 +#define reg_ts_clk_inv_lsb 0 +#define p_reg_ts_hybrid 0xD822 +#define reg_ts_hybrid_pos 0 +#define reg_ts_hybrid_len 1 +#define reg_ts_hybrid_lsb 0 +#define p_reg_ccir_sel 0xD823 +#define reg_ccir_sel_pos 0 +#define reg_ccir_sel_len 4 +#define reg_ccir_sel_lsb 0 +#define p_reg_top_sys_gate 0xD824 +#define reg_top_sys_gate_pos 0 +#define reg_top_sys_gate_len 1 +#define reg_top_sys_gate_lsb 0 +#define p_reg_top_padpu 0xD825 +#define reg_top_padpu_pos 0 +#define reg_top_padpu_len 1 +#define reg_top_padpu_lsb 0 +#define p_reg_top_padpd 0xD826 +#define reg_top_padpd_pos 0 +#define reg_top_padpd_len 1 +#define reg_top_padpd_lsb 0 +#define p_reg_top_padodpu 0xD827 +#define reg_top_padodpu_pos 0 +#define reg_top_padodpu_len 1 +#define reg_top_padodpu_lsb 0 +#define p_reg_top_thirdodpu 0xD828 +#define reg_top_thirdodpu_pos 0 +#define reg_top_thirdodpu_len 1 +#define reg_top_thirdodpu_lsb 0 +#define p_reg_top_agc_od 0xD829 +#define reg_top_agc_od_pos 0 +#define reg_top_agc_od_len 1 +#define reg_top_agc_od_lsb 0 +#define p_reg_top_padmpdr2 0xD82A +#define reg_top_padmpdr2_pos 0 +#define reg_top_padmpdr2_len 1 +#define reg_top_padmpdr2_lsb 0 +#define p_reg_top_padmpdr4 0xD82B +#define reg_top_padmpdr4_pos 0 +#define reg_top_padmpdr4_len 1 +#define reg_top_padmpdr4_lsb 0 +#define p_reg_top_padmpdr8 0xD82C +#define reg_top_padmpdr8_pos 0 +#define reg_top_padmpdr8_len 1 +#define reg_top_padmpdr8_lsb 0 +#define p_reg_top_padmpdrsr 0xD82D +#define reg_top_padmpdrsr_pos 0 +#define reg_top_padmpdrsr_len 1 +#define reg_top_padmpdrsr_lsb 0 +#define p_reg_top_padmppu 0xD82E +#define reg_top_padmppu_pos 0 +#define reg_top_padmppu_len 1 +#define reg_top_padmppu_lsb 0 +#define p_reg_top_padmppd 0xD82F +#define reg_top_padmppd_pos 0 +#define reg_top_padmppd_len 1 +#define reg_top_padmppd_lsb 0 +#define p_reg_top_padmiscdr2 0xD830 +#define reg_top_padmiscdr2_pos 0 +#define reg_top_padmiscdr2_len 1 +#define reg_top_padmiscdr2_lsb 0 +#define p_reg_top_padmiscdr4 0xD831 +#define reg_top_padmiscdr4_pos 0 +#define reg_top_padmiscdr4_len 1 +#define reg_top_padmiscdr4_lsb 0 +#define p_reg_top_padmiscdr8 0xD832 +#define reg_top_padmiscdr8_pos 0 +#define reg_top_padmiscdr8_len 1 +#define reg_top_padmiscdr8_lsb 0 +#define p_reg_top_padmiscdrsr 0xD833 +#define reg_top_padmiscdrsr_pos 0 +#define reg_top_padmiscdrsr_len 1 +#define reg_top_padmiscdrsr_lsb 0 +#define p_reg_top_padmiscpu 0xD834 +#define reg_top_padmiscpu_pos 0 +#define reg_top_padmiscpu_len 1 +#define reg_top_padmiscpu_lsb 0 +#define p_reg_top_padmiscpd 0xD835 +#define reg_top_padmiscpd_pos 0 +#define reg_top_padmiscpd_len 1 +#define reg_top_padmiscpd_lsb 0 +#define p_reg_host_b0_smt 0xD836 +#define reg_host_b0_smt_pos 0 +#define reg_host_b0_smt_len 1 +#define reg_host_b0_smt_lsb 0 +#define p_reg_host_b1_smt 0xD837 +#define reg_host_b1_smt_pos 0 +#define reg_host_b1_smt_len 1 +#define reg_host_b1_smt_lsb 0 +#define p_reg_host_b2_smt 0xD838 +#define reg_host_b2_smt_pos 0 +#define reg_host_b2_smt_len 1 +#define reg_host_b2_smt_lsb 0 +#define p_reg_host_b3_smt 0xD839 +#define reg_host_b3_smt_pos 0 +#define reg_host_b3_smt_len 1 +#define reg_host_b3_smt_lsb 0 +#define p_reg_host_b4_smt 0xD83A +#define reg_host_b4_smt_pos 0 +#define reg_host_b4_smt_len 1 +#define reg_host_b4_smt_lsb 0 +#define p_reg_host_b5_smt 0xD83B +#define reg_host_b5_smt_pos 0 +#define reg_host_b5_smt_len 1 +#define reg_host_b5_smt_lsb 0 +#define p_reg_host_b6_smt 0xD83C +#define reg_host_b6_smt_pos 0 +#define reg_host_b6_smt_len 1 +#define reg_host_b6_smt_lsb 0 +#define p_reg_host_b7_smt 0xD83D +#define reg_host_b7_smt_pos 0 +#define reg_host_b7_smt_len 1 +#define reg_host_b7_smt_lsb 0 +#define p_reg_host_b8_smt 0xD83E +#define reg_host_b8_smt_pos 0 +#define reg_host_b8_smt_len 1 +#define reg_host_b8_smt_lsb 0 +#define p_reg_host_b9_smt 0xD83F +#define reg_host_b9_smt_pos 0 +#define reg_host_b9_smt_len 1 +#define reg_host_b9_smt_lsb 0 +#define p_reg_host_b10_smt 0xD840 +#define reg_host_b10_smt_pos 0 +#define reg_host_b10_smt_len 1 +#define reg_host_b10_smt_lsb 0 +#define p_reg_host_b11_smt 0xD841 +#define reg_host_b11_smt_pos 0 +#define reg_host_b11_smt_len 1 +#define reg_host_b11_smt_lsb 0 +#define p_reg_host_a0_smt 0xD842 +#define reg_host_a0_smt_pos 0 +#define reg_host_a0_smt_len 1 +#define reg_host_a0_smt_lsb 0 +#define p_reg_host_a1_smt 0xD843 +#define reg_host_a1_smt_pos 0 +#define reg_host_a1_smt_len 1 +#define reg_host_a1_smt_lsb 0 +#define p_reg_host_a2_smt 0xD844 +#define reg_host_a2_smt_pos 0 +#define reg_host_a2_smt_len 1 +#define reg_host_a2_smt_lsb 0 +#define p_reg_host_a3_smt 0xD845 +#define reg_host_a3_smt_pos 0 +#define reg_host_a3_smt_len 1 +#define reg_host_a3_smt_lsb 0 +#define p_reg_host_a4_smt 0xD846 +#define reg_host_a4_smt_pos 0 +#define reg_host_a4_smt_len 1 +#define reg_host_a4_smt_lsb 0 +#define p_reg_host_a5_smt 0xD847 +#define reg_host_a5_smt_pos 0 +#define reg_host_a5_smt_len 1 +#define reg_host_a5_smt_lsb 0 +#define p_reg_host_a6_smt 0xD848 +#define reg_host_a6_smt_pos 0 +#define reg_host_a6_smt_len 1 +#define reg_host_a6_smt_lsb 0 +#define p_reg_host_a7_smt 0xD849 +#define reg_host_a7_smt_pos 0 +#define reg_host_a7_smt_len 1 +#define reg_host_a7_smt_lsb 0 +#define p_reg_host_a8_smt 0xD84A +#define reg_host_a8_smt_pos 0 +#define reg_host_a8_smt_len 1 +#define reg_host_a8_smt_lsb 0 +#define p_reg_host_a9_smt 0xD84B +#define reg_host_a9_smt_pos 0 +#define reg_host_a9_smt_len 1 +#define reg_host_a9_smt_lsb 0 +#define p_reg_host_a10_smt 0xD84C +#define reg_host_a10_smt_pos 0 +#define reg_host_a10_smt_len 1 +#define reg_host_a10_smt_lsb 0 +#define p_reg_host_a11_smt 0xD84D +#define reg_host_a11_smt_pos 0 +#define reg_host_a11_smt_len 1 +#define reg_host_a11_smt_lsb 0 +#define p_reg_testmode_pds 0xD84E +#define reg_testmode_pds_pos 0 +#define reg_testmode_pds_len 3 +#define reg_testmode_pds_lsb 0 +#define p_reg_debug31_pds 0xD84F +#define reg_debug31_pds_pos 0 +#define reg_debug31_pds_len 3 +#define reg_debug31_pds_lsb 0 +#define p_reg_debug30_pds 0xD850 +#define reg_debug30_pds_pos 0 +#define reg_debug30_pds_len 3 +#define reg_debug30_pds_lsb 0 +#define p_reg_debug29_pds 0xD851 +#define reg_debug29_pds_pos 0 +#define reg_debug29_pds_len 3 +#define reg_debug29_pds_lsb 0 +#define p_reg_debug28_pds 0xD852 +#define reg_debug28_pds_pos 0 +#define reg_debug28_pds_len 3 +#define reg_debug28_pds_lsb 0 +#define p_reg_debug27_pds 0xD853 +#define reg_debug27_pds_pos 0 +#define reg_debug27_pds_len 3 +#define reg_debug27_pds_lsb 0 +#define p_reg_debug26_pds 0xD854 +#define reg_debug26_pds_pos 0 +#define reg_debug26_pds_len 3 +#define reg_debug26_pds_lsb 0 +#define p_reg_debug25_pds 0xD855 +#define reg_debug25_pds_pos 0 +#define reg_debug25_pds_len 3 +#define reg_debug25_pds_lsb 0 +#define p_reg_debug24_pds 0xD856 +#define reg_debug24_pds_pos 0 +#define reg_debug24_pds_len 3 +#define reg_debug24_pds_lsb 0 +#define p_reg_debug23_pds 0xD857 +#define reg_debug23_pds_pos 0 +#define reg_debug23_pds_len 3 +#define reg_debug23_pds_lsb 0 +#define p_reg_debug22_pds 0xD858 +#define reg_debug22_pds_pos 0 +#define reg_debug22_pds_len 3 +#define reg_debug22_pds_lsb 0 +#define p_reg_gpioh1_pds 0xD859 +#define reg_gpioh1_pds_pos 0 +#define reg_gpioh1_pds_len 3 +#define reg_gpioh1_pds_lsb 0 +#define p_reg_gpioh2_pds 0xD85A +#define reg_gpioh2_pds_pos 0 +#define reg_gpioh2_pds_len 3 +#define reg_gpioh2_pds_lsb 0 +#define p_reg_gpioh3_pds 0xD85B +#define reg_gpioh3_pds_pos 0 +#define reg_gpioh3_pds_len 3 +#define reg_gpioh3_pds_lsb 0 +#define p_reg_gpioh4_pds 0xD85C +#define reg_gpioh4_pds_pos 0 +#define reg_gpioh4_pds_len 3 +#define reg_gpioh4_pds_lsb 0 +#define p_reg_iosda_pds 0xD85D +#define reg_iosda_pds_pos 0 +#define reg_iosda_pds_len 3 +#define reg_iosda_pds_lsb 0 +#define p_reg_ioscl_pds 0xD85E +#define reg_ioscl_pds_pos 0 +#define reg_ioscl_pds_len 3 +#define reg_ioscl_pds_lsb 0 +#define p_reg_gpioh5_pds 0xD85F +#define reg_gpioh5_pds_pos 0 +#define reg_gpioh5_pds_len 3 +#define reg_gpioh5_pds_lsb 0 +#define p_reg_bond0_pds 0xD860 +#define reg_bond0_pds_pos 0 +#define reg_bond0_pds_len 3 +#define reg_bond0_pds_lsb 0 +#define p_reg_i2caddr6_pds 0xD861 +#define reg_i2caddr6_pds_pos 0 +#define reg_i2caddr6_pds_len 3 +#define reg_i2caddr6_pds_lsb 0 +#define p_reg_i2caddr5_pds 0xD862 +#define reg_i2caddr5_pds_pos 0 +#define reg_i2caddr5_pds_len 3 +#define reg_i2caddr5_pds_lsb 0 +#define p_reg_i2caddr4_pds 0xD863 +#define reg_i2caddr4_pds_pos 0 +#define reg_i2caddr4_pds_len 3 +#define reg_i2caddr4_pds_lsb 0 +#define p_reg_host_a0_pds 0xD864 +#define reg_host_a0_pds_pos 0 +#define reg_host_a0_pds_len 3 +#define reg_host_a0_pds_lsb 0 +#define p_reg_host_a1_pds 0xD865 +#define reg_host_a1_pds_pos 0 +#define reg_host_a1_pds_len 3 +#define reg_host_a1_pds_lsb 0 +#define p_reg_debug21_pds 0xD866 +#define reg_debug21_pds_pos 0 +#define reg_debug21_pds_len 3 +#define reg_debug21_pds_lsb 0 +#define p_reg_debug20_pds 0xD867 +#define reg_debug20_pds_pos 0 +#define reg_debug20_pds_len 3 +#define reg_debug20_pds_lsb 0 +#define p_reg_debug19_pds 0xD868 +#define reg_debug19_pds_pos 0 +#define reg_debug19_pds_len 3 +#define reg_debug19_pds_lsb 0 +#define p_reg_debug18_pds 0xD869 +#define reg_debug18_pds_pos 0 +#define reg_debug18_pds_len 3 +#define reg_debug18_pds_lsb 0 +#define p_reg_debug17_pds 0xD86A +#define reg_debug17_pds_pos 0 +#define reg_debug17_pds_len 3 +#define reg_debug17_pds_lsb 0 +#define p_reg_host_a2_pds 0xD86B +#define reg_host_a2_pds_pos 0 +#define reg_host_a2_pds_len 3 +#define reg_host_a2_pds_lsb 0 +#define p_reg_host_a3_pds 0xD86C +#define reg_host_a3_pds_pos 0 +#define reg_host_a3_pds_len 3 +#define reg_host_a3_pds_lsb 0 +#define p_reg_host_a4_pds 0xD86D +#define reg_host_a4_pds_pos 0 +#define reg_host_a4_pds_len 3 +#define reg_host_a4_pds_lsb 0 +#define p_reg_host_a5_pds 0xD86E +#define reg_host_a5_pds_pos 0 +#define reg_host_a5_pds_len 3 +#define reg_host_a5_pds_lsb 0 +#define p_reg_host_a6_pds 0xD86F +#define reg_host_a6_pds_pos 0 +#define reg_host_a6_pds_len 3 +#define reg_host_a6_pds_lsb 0 +#define p_reg_p160sel_pds 0xD870 +#define reg_p160sel_pds_pos 0 +#define reg_p160sel_pds_len 3 +#define reg_p160sel_pds_lsb 0 +#define p_reg_gpioh13_pds 0xD871 +#define reg_gpioh13_pds_pos 0 +#define reg_gpioh13_pds_len 3 +#define reg_gpioh13_pds_lsb 0 +#define p_reg_gpioh12_pds 0xD872 +#define reg_gpioh12_pds_pos 0 +#define reg_gpioh12_pds_len 3 +#define reg_gpioh12_pds_lsb 0 +#define p_reg_gpioh11_pds 0xD873 +#define reg_gpioh11_pds_pos 0 +#define reg_gpioh11_pds_len 3 +#define reg_gpioh11_pds_lsb 0 +#define p_reg_host_a7_pds 0xD874 +#define reg_host_a7_pds_pos 0 +#define reg_host_a7_pds_len 3 +#define reg_host_a7_pds_lsb 0 +#define p_reg_host_a8_pds 0xD875 +#define reg_host_a8_pds_pos 0 +#define reg_host_a8_pds_len 3 +#define reg_host_a8_pds_lsb 0 +#define p_reg_host_a9_pds 0xD876 +#define reg_host_a9_pds_pos 0 +#define reg_host_a9_pds_len 3 +#define reg_host_a9_pds_lsb 0 +#define p_reg_host_a10_pds 0xD877 +#define reg_host_a10_pds_pos 0 +#define reg_host_a10_pds_len 3 +#define reg_host_a10_pds_lsb 0 +#define p_reg_host_a11_pds 0xD878 +#define reg_host_a11_pds_pos 0 +#define reg_host_a11_pds_len 3 +#define reg_host_a11_pds_lsb 0 +#define p_reg_bondu0_pds 0xD879 +#define reg_bondu0_pds_pos 0 +#define reg_bondu0_pds_len 3 +#define reg_bondu0_pds_lsb 0 +#define p_reg_host_b0_pds 0xD87A +#define reg_host_b0_pds_pos 0 +#define reg_host_b0_pds_len 3 +#define reg_host_b0_pds_lsb 0 +#define p_reg_host_b1_pds 0xD87B +#define reg_host_b1_pds_pos 0 +#define reg_host_b1_pds_len 3 +#define reg_host_b1_pds_lsb 0 +#define p_reg_host_b2_pds 0xD87C +#define reg_host_b2_pds_pos 0 +#define reg_host_b2_pds_len 3 +#define reg_host_b2_pds_lsb 0 +#define p_reg_host_b3_pds 0xD87D +#define reg_host_b3_pds_pos 0 +#define reg_host_b3_pds_len 3 +#define reg_host_b3_pds_lsb 0 +#define p_reg_host_b4_pds 0xD87E +#define reg_host_b4_pds_pos 0 +#define reg_host_b4_pds_len 3 +#define reg_host_b4_pds_lsb 0 +#define p_reg_host_b5_pds 0xD87F +#define reg_host_b5_pds_pos 0 +#define reg_host_b5_pds_len 3 +#define reg_host_b5_pds_lsb 0 +#define p_reg_host_b6_pds 0xD880 +#define reg_host_b6_pds_pos 0 +#define reg_host_b6_pds_len 3 +#define reg_host_b6_pds_lsb 0 +#define p_reg_host_b7_pds 0xD881 +#define reg_host_b7_pds_pos 0 +#define reg_host_b7_pds_len 3 +#define reg_host_b7_pds_lsb 0 +#define p_reg_afe_f12_pds 0xD882 +#define reg_afe_f12_pds_pos 0 +#define reg_afe_f12_pds_len 3 +#define reg_afe_f12_pds_lsb 0 +#define p_reg_host_b8_pds 0xD883 +#define reg_host_b8_pds_pos 0 +#define reg_host_b8_pds_len 3 +#define reg_host_b8_pds_lsb 0 +#define p_reg_host_b9_pds 0xD884 +#define reg_host_b9_pds_pos 0 +#define reg_host_b9_pds_len 3 +#define reg_host_b9_pds_lsb 0 +#define p_reg_host_b10_pds 0xD885 +#define reg_host_b10_pds_pos 0 +#define reg_host_b10_pds_len 3 +#define reg_host_b10_pds_lsb 0 +#define p_reg_host_b11_pds 0xD886 +#define reg_host_b11_pds_pos 0 +#define reg_host_b11_pds_len 3 +#define reg_host_b11_pds_lsb 0 +#define p_reg_debug16_pds 0xD887 +#define reg_debug16_pds_pos 0 +#define reg_debug16_pds_len 3 +#define reg_debug16_pds_lsb 0 +#define p_reg_debug15_pds 0xD888 +#define reg_debug15_pds_pos 0 +#define reg_debug15_pds_len 3 +#define reg_debug15_pds_lsb 0 +#define p_reg_debug14_pds 0xD889 +#define reg_debug14_pds_pos 0 +#define reg_debug14_pds_len 3 +#define reg_debug14_pds_lsb 0 +#define p_reg_debug13_pds 0xD88A +#define reg_debug13_pds_pos 0 +#define reg_debug13_pds_len 3 +#define reg_debug13_pds_lsb 0 +#define p_reg_debug12_pds 0xD88B +#define reg_debug12_pds_pos 0 +#define reg_debug12_pds_len 3 +#define reg_debug12_pds_lsb 0 +#define p_reg_debug11_pds 0xD88C +#define reg_debug11_pds_pos 0 +#define reg_debug11_pds_len 3 +#define reg_debug11_pds_lsb 0 +#define p_reg_debug10_pds 0xD88D +#define reg_debug10_pds_pos 0 +#define reg_debug10_pds_len 3 +#define reg_debug10_pds_lsb 0 +#define p_reg_debug9_pds 0xD88E +#define reg_debug9_pds_pos 0 +#define reg_debug9_pds_len 3 +#define reg_debug9_pds_lsb 0 +#define p_reg_debug8_pds 0xD88F +#define reg_debug8_pds_pos 0 +#define reg_debug8_pds_len 3 +#define reg_debug8_pds_lsb 0 +#define p_reg_debug7_pds 0xD890 +#define reg_debug7_pds_pos 0 +#define reg_debug7_pds_len 3 +#define reg_debug7_pds_lsb 0 +#define p_reg_debug6_pds 0xD891 +#define reg_debug6_pds_pos 0 +#define reg_debug6_pds_len 3 +#define reg_debug6_pds_lsb 0 +#define p_reg_debug5_pds 0xD892 +#define reg_debug5_pds_pos 0 +#define reg_debug5_pds_len 3 +#define reg_debug5_pds_lsb 0 +#define p_reg_debug4_pds 0xD893 +#define reg_debug4_pds_pos 0 +#define reg_debug4_pds_len 3 +#define reg_debug4_pds_lsb 0 +#define p_reg_clko_pds 0xD894 +#define reg_clko_pds_pos 0 +#define reg_clko_pds_len 3 +#define reg_clko_pds_lsb 0 +#define p_reg_gpioh6_pds 0xD895 +#define reg_gpioh6_pds_pos 0 +#define reg_gpioh6_pds_len 3 +#define reg_gpioh6_pds_lsb 0 +#define p_reg_gpioh7_pds 0xD896 +#define reg_gpioh7_pds_pos 0 +#define reg_gpioh7_pds_len 3 +#define reg_gpioh7_pds_lsb 0 +#define p_reg_gpioh8_pds 0xD897 +#define reg_gpioh8_pds_pos 0 +#define reg_gpioh8_pds_len 3 +#define reg_gpioh8_pds_lsb 0 +#define p_reg_gpioh9_pds 0xD898 +#define reg_gpioh9_pds_pos 0 +#define reg_gpioh9_pds_len 3 +#define reg_gpioh9_pds_lsb 0 +#define p_reg_gpioh10_pds 0xD899 +#define reg_gpioh10_pds_pos 0 +#define reg_gpioh10_pds_len 3 +#define reg_gpioh10_pds_lsb 0 +#define p_reg_debug3_pds 0xD89A +#define reg_debug3_pds_pos 0 +#define reg_debug3_pds_len 3 +#define reg_debug3_pds_lsb 0 +#define p_reg_debug2_pds 0xD89B +#define reg_debug2_pds_pos 0 +#define reg_debug2_pds_len 3 +#define reg_debug2_pds_lsb 0 +#define p_reg_debug1_pds 0xD89C +#define reg_debug1_pds_pos 0 +#define reg_debug1_pds_len 3 +#define reg_debug1_pds_lsb 0 +#define p_reg_debug0_pds 0xD89D +#define reg_debug0_pds_pos 0 +#define reg_debug0_pds_len 3 +#define reg_debug0_pds_lsb 0 +#define p_reg_gpiot1_pds 0xD89E +#define reg_gpiot1_pds_pos 0 +#define reg_gpiot1_pds_len 3 +#define reg_gpiot1_pds_lsb 0 +#define p_reg_gpiot2_pds 0xD89F +#define reg_gpiot2_pds_pos 0 +#define reg_gpiot2_pds_len 3 +#define reg_gpiot2_pds_lsb 0 +#define p_reg_rfagc_pds 0xD8A0 +#define reg_rfagc_pds_pos 0 +#define reg_rfagc_pds_len 3 +#define reg_rfagc_pds_lsb 0 +#define p_reg_ifagc_pds 0xD8A1 +#define reg_ifagc_pds_pos 0 +#define reg_ifagc_pds_len 3 +#define reg_ifagc_pds_lsb 0 +#define p_reg_gpiot3_pds 0xD8A2 +#define reg_gpiot3_pds_pos 0 +#define reg_gpiot3_pds_len 3 +#define reg_gpiot3_pds_lsb 0 +#define p_reg_i2caddr3_pds 0xD8A3 +#define reg_i2caddr3_pds_pos 0 +#define reg_i2caddr3_pds_len 3 +#define reg_i2caddr3_pds_lsb 0 +#define p_reg_i2caddr2_pds 0xD8A4 +#define reg_i2caddr2_pds_pos 0 +#define reg_i2caddr2_pds_len 3 +#define reg_i2caddr2_pds_lsb 0 +#define p_reg_i2caddr1_pds 0xD8A5 +#define reg_i2caddr1_pds_pos 0 +#define reg_i2caddr1_pds_len 3 +#define reg_i2caddr1_pds_lsb 0 +#define p_reg_afe_sel33_pds 0xD8A6 +#define reg_afe_sel33_pds_pos 0 +#define reg_afe_sel33_pds_len 3 +#define reg_afe_sel33_pds_lsb 0 +#define p_reg_iotunscl_pds 0xD8A7 +#define reg_iotunscl_pds_pos 0 +#define reg_iotunscl_pds_len 3 +#define reg_iotunscl_pds_lsb 0 +#define p_reg_iotunsda_pds 0xD8A8 +#define reg_iotunsda_pds_pos 0 +#define reg_iotunsda_pds_len 3 +#define reg_iotunsda_pds_lsb 0 +#define p_reg_rxdofsm_pds 0xD8A9 +#define reg_rxdofsm_pds_pos 0 +#define reg_rxdofsm_pds_len 3 +#define reg_rxdofsm_pds_lsb 0 +#define p_reg_txdofsm_pds 0xD8AA +#define reg_txdofsm_pds_pos 0 +#define reg_txdofsm_pds_len 3 +#define reg_txdofsm_pds_lsb 0 +#define p_reg_rxdlink_pds 0xD8AB +#define reg_rxdlink_pds_pos 0 +#define reg_rxdlink_pds_len 3 +#define reg_rxdlink_pds_lsb 0 +#define p_reg_txdlink_pds 0xD8AC +#define reg_txdlink_pds_pos 0 +#define reg_txdlink_pds_len 3 +#define reg_txdlink_pds_lsb 0 +#define p_reg_ck_test_pds 0xD8AD +#define reg_ck_test_pds_pos 0 +#define reg_ck_test_pds_len 3 +#define reg_ck_test_pds_lsb 0 +#define r_reg_top_gpioh1_i 0xD8AE +#define reg_top_gpioh1_i_pos 0 +#define reg_top_gpioh1_i_len 1 +#define reg_top_gpioh1_i_lsb 0 +#define p_reg_top_gpioh1_o 0xD8AF +#define reg_top_gpioh1_o_pos 0 +#define reg_top_gpioh1_o_len 1 +#define reg_top_gpioh1_o_lsb 0 +#define p_reg_top_gpioh1_en 0xD8B0 +#define reg_top_gpioh1_en_pos 0 +#define reg_top_gpioh1_en_len 1 +#define reg_top_gpioh1_en_lsb 0 +#define p_reg_top_gpioh1_on 0xD8B1 +#define reg_top_gpioh1_on_pos 0 +#define reg_top_gpioh1_on_len 1 +#define reg_top_gpioh1_on_lsb 0 +#define r_reg_top_gpioh3_i 0xD8B2 +#define reg_top_gpioh3_i_pos 0 +#define reg_top_gpioh3_i_len 1 +#define reg_top_gpioh3_i_lsb 0 +#define p_reg_top_gpioh3_o 0xD8B3 +#define reg_top_gpioh3_o_pos 0 +#define reg_top_gpioh3_o_len 1 +#define reg_top_gpioh3_o_lsb 0 +#define p_reg_top_gpioh3_en 0xD8B4 +#define reg_top_gpioh3_en_pos 0 +#define reg_top_gpioh3_en_len 1 +#define reg_top_gpioh3_en_lsb 0 +#define p_reg_top_gpioh3_on 0xD8B5 +#define reg_top_gpioh3_on_pos 0 +#define reg_top_gpioh3_on_len 1 +#define reg_top_gpioh3_on_lsb 0 +#define r_reg_top_gpioh2_i 0xD8B6 +#define reg_top_gpioh2_i_pos 0 +#define reg_top_gpioh2_i_len 1 +#define reg_top_gpioh2_i_lsb 0 +#define p_reg_top_gpioh2_o 0xD8B7 +#define reg_top_gpioh2_o_pos 0 +#define reg_top_gpioh2_o_len 1 +#define reg_top_gpioh2_o_lsb 0 +#define p_reg_top_gpioh2_en 0xD8B8 +#define reg_top_gpioh2_en_pos 0 +#define reg_top_gpioh2_en_len 1 +#define reg_top_gpioh2_en_lsb 0 +#define p_reg_top_gpioh2_on 0xD8B9 +#define reg_top_gpioh2_on_pos 0 +#define reg_top_gpioh2_on_len 1 +#define reg_top_gpioh2_on_lsb 0 +#define r_reg_top_gpioh5_i 0xD8BA +#define reg_top_gpioh5_i_pos 0 +#define reg_top_gpioh5_i_len 1 +#define reg_top_gpioh5_i_lsb 0 +#define p_reg_top_gpioh5_o 0xD8BB +#define reg_top_gpioh5_o_pos 0 +#define reg_top_gpioh5_o_len 1 +#define reg_top_gpioh5_o_lsb 0 +#define p_reg_top_gpioh5_en 0xD8BC +#define reg_top_gpioh5_en_pos 0 +#define reg_top_gpioh5_en_len 1 +#define reg_top_gpioh5_en_lsb 0 +#define p_reg_top_gpioh5_on 0xD8BD +#define reg_top_gpioh5_on_pos 0 +#define reg_top_gpioh5_on_len 1 +#define reg_top_gpioh5_on_lsb 0 +#define r_reg_top_gpioh4_i 0xD8BE +#define reg_top_gpioh4_i_pos 0 +#define reg_top_gpioh4_i_len 1 +#define reg_top_gpioh4_i_lsb 0 +#define p_reg_top_gpioh4_o 0xD8BF +#define reg_top_gpioh4_o_pos 0 +#define reg_top_gpioh4_o_len 1 +#define reg_top_gpioh4_o_lsb 0 +#define p_reg_top_gpioh4_en 0xD8C0 +#define reg_top_gpioh4_en_pos 0 +#define reg_top_gpioh4_en_len 1 +#define reg_top_gpioh4_en_lsb 0 +#define p_reg_top_gpioh4_on 0xD8C1 +#define reg_top_gpioh4_on_pos 0 +#define reg_top_gpioh4_on_len 1 +#define reg_top_gpioh4_on_lsb 0 +#define r_reg_top_gpioh7_i 0xD8C2 +#define reg_top_gpioh7_i_pos 0 +#define reg_top_gpioh7_i_len 1 +#define reg_top_gpioh7_i_lsb 0 +#define p_reg_top_gpioh7_o 0xD8C3 +#define reg_top_gpioh7_o_pos 0 +#define reg_top_gpioh7_o_len 1 +#define reg_top_gpioh7_o_lsb 0 +#define p_reg_top_gpioh7_en 0xD8C4 +#define reg_top_gpioh7_en_pos 0 +#define reg_top_gpioh7_en_len 1 +#define reg_top_gpioh7_en_lsb 0 +#define p_reg_top_gpioh7_on 0xD8C5 +#define reg_top_gpioh7_on_pos 0 +#define reg_top_gpioh7_on_len 1 +#define reg_top_gpioh7_on_lsb 0 +#define r_reg_top_gpioh6_i 0xD8C6 +#define reg_top_gpioh6_i_pos 0 +#define reg_top_gpioh6_i_len 1 +#define reg_top_gpioh6_i_lsb 0 +#define p_reg_top_gpioh6_o 0xD8C7 +#define reg_top_gpioh6_o_pos 0 +#define reg_top_gpioh6_o_len 1 +#define reg_top_gpioh6_o_lsb 0 +#define p_reg_top_gpioh6_en 0xD8C8 +#define reg_top_gpioh6_en_pos 0 +#define reg_top_gpioh6_en_len 1 +#define reg_top_gpioh6_en_lsb 0 +#define p_reg_top_gpioh6_on 0xD8C9 +#define reg_top_gpioh6_on_pos 0 +#define reg_top_gpioh6_on_len 1 +#define reg_top_gpioh6_on_lsb 0 +#define r_reg_top_gpioh9_i 0xD8CA +#define reg_top_gpioh9_i_pos 0 +#define reg_top_gpioh9_i_len 1 +#define reg_top_gpioh9_i_lsb 0 +#define p_reg_top_gpioh9_o 0xD8CB +#define reg_top_gpioh9_o_pos 0 +#define reg_top_gpioh9_o_len 1 +#define reg_top_gpioh9_o_lsb 0 +#define p_reg_top_gpioh9_en 0xD8CC +#define reg_top_gpioh9_en_pos 0 +#define reg_top_gpioh9_en_len 1 +#define reg_top_gpioh9_en_lsb 0 +#define p_reg_top_gpioh9_on 0xD8CD +#define reg_top_gpioh9_on_pos 0 +#define reg_top_gpioh9_on_len 1 +#define reg_top_gpioh9_on_lsb 0 +#define r_reg_top_gpioh8_i 0xD8CE +#define reg_top_gpioh8_i_pos 0 +#define reg_top_gpioh8_i_len 1 +#define reg_top_gpioh8_i_lsb 0 +#define p_reg_top_gpioh8_o 0xD8CF +#define reg_top_gpioh8_o_pos 0 +#define reg_top_gpioh8_o_len 1 +#define reg_top_gpioh8_o_lsb 0 +#define p_reg_top_gpioh8_en 0xD8D0 +#define reg_top_gpioh8_en_pos 0 +#define reg_top_gpioh8_en_len 1 +#define reg_top_gpioh8_en_lsb 0 +#define p_reg_top_gpioh8_on 0xD8D1 +#define reg_top_gpioh8_on_pos 0 +#define reg_top_gpioh8_on_len 1 +#define reg_top_gpioh8_on_lsb 0 +#define r_reg_top_gpioh11_i 0xD8D2 +#define reg_top_gpioh11_i_pos 0 +#define reg_top_gpioh11_i_len 1 +#define reg_top_gpioh11_i_lsb 0 +#define p_reg_top_gpioh11_o 0xD8D3 +#define reg_top_gpioh11_o_pos 0 +#define reg_top_gpioh11_o_len 1 +#define reg_top_gpioh11_o_lsb 0 +#define p_reg_top_gpioh11_en 0xD8D4 +#define reg_top_gpioh11_en_pos 0 +#define reg_top_gpioh11_en_len 1 +#define reg_top_gpioh11_en_lsb 0 +#define p_reg_top_gpioh11_on 0xD8D5 +#define reg_top_gpioh11_on_pos 0 +#define reg_top_gpioh11_on_len 1 +#define reg_top_gpioh11_on_lsb 0 +#define r_reg_top_gpioh10_i 0xD8D6 +#define reg_top_gpioh10_i_pos 0 +#define reg_top_gpioh10_i_len 1 +#define reg_top_gpioh10_i_lsb 0 +#define p_reg_top_gpioh10_o 0xD8D7 +#define reg_top_gpioh10_o_pos 0 +#define reg_top_gpioh10_o_len 1 +#define reg_top_gpioh10_o_lsb 0 +#define p_reg_top_gpioh10_en 0xD8D8 +#define reg_top_gpioh10_en_pos 0 +#define reg_top_gpioh10_en_len 1 +#define reg_top_gpioh10_en_lsb 0 +#define p_reg_top_gpioh10_on 0xD8D9 +#define reg_top_gpioh10_on_pos 0 +#define reg_top_gpioh10_on_len 1 +#define reg_top_gpioh10_on_lsb 0 +#define r_reg_top_gpioh13_i 0xD8DA +#define reg_top_gpioh13_i_pos 0 +#define reg_top_gpioh13_i_len 1 +#define reg_top_gpioh13_i_lsb 0 +#define p_reg_top_gpioh13_o 0xD8DB +#define reg_top_gpioh13_o_pos 0 +#define reg_top_gpioh13_o_len 1 +#define reg_top_gpioh13_o_lsb 0 +#define p_reg_top_gpioh13_en 0xD8DC +#define reg_top_gpioh13_en_pos 0 +#define reg_top_gpioh13_en_len 1 +#define reg_top_gpioh13_en_lsb 0 +#define p_reg_top_gpioh13_on 0xD8DD +#define reg_top_gpioh13_on_pos 0 +#define reg_top_gpioh13_on_len 1 +#define reg_top_gpioh13_on_lsb 0 +#define r_reg_top_gpioh12_i 0xD8DE +#define reg_top_gpioh12_i_pos 0 +#define reg_top_gpioh12_i_len 1 +#define reg_top_gpioh12_i_lsb 0 +#define p_reg_top_gpioh12_o 0xD8DF +#define reg_top_gpioh12_o_pos 0 +#define reg_top_gpioh12_o_len 1 +#define reg_top_gpioh12_o_lsb 0 +#define p_reg_top_gpioh12_en 0xD8E0 +#define reg_top_gpioh12_en_pos 0 +#define reg_top_gpioh12_en_len 1 +#define reg_top_gpioh12_en_lsb 0 +#define p_reg_top_gpioh12_on 0xD8E1 +#define reg_top_gpioh12_on_pos 0 +#define reg_top_gpioh12_on_len 1 +#define reg_top_gpioh12_on_lsb 0 +#define r_reg_top_gpiot1_i 0xD8E2 +#define reg_top_gpiot1_i_pos 0 +#define reg_top_gpiot1_i_len 1 +#define reg_top_gpiot1_i_lsb 0 +#define p_reg_top_gpiot1_o 0xD8E3 +#define reg_top_gpiot1_o_pos 0 +#define reg_top_gpiot1_o_len 1 +#define reg_top_gpiot1_o_lsb 0 +#define p_reg_top_gpiot1_en 0xD8E4 +#define reg_top_gpiot1_en_pos 0 +#define reg_top_gpiot1_en_len 1 +#define reg_top_gpiot1_en_lsb 0 +#define p_reg_top_gpiot1_on 0xD8E5 +#define reg_top_gpiot1_on_pos 0 +#define reg_top_gpiot1_on_len 1 +#define reg_top_gpiot1_on_lsb 0 +#define r_reg_top_gpiot3_i 0xD8E6 +#define reg_top_gpiot3_i_pos 0 +#define reg_top_gpiot3_i_len 1 +#define reg_top_gpiot3_i_lsb 0 +#define p_reg_top_gpiot3_o 0xD8E7 +#define reg_top_gpiot3_o_pos 0 +#define reg_top_gpiot3_o_len 1 +#define reg_top_gpiot3_o_lsb 0 +#define p_reg_top_gpiot3_en 0xD8E8 +#define reg_top_gpiot3_en_pos 0 +#define reg_top_gpiot3_en_len 1 +#define reg_top_gpiot3_en_lsb 0 +#define p_reg_top_gpiot3_on 0xD8E9 +#define reg_top_gpiot3_on_pos 0 +#define reg_top_gpiot3_on_len 1 +#define reg_top_gpiot3_on_lsb 0 +#define r_reg_top_gpiot2_i 0xD8EA +#define reg_top_gpiot2_i_pos 0 +#define reg_top_gpiot2_i_len 1 +#define reg_top_gpiot2_i_lsb 0 +#define p_reg_top_gpiot2_o 0xD8EB +#define reg_top_gpiot2_o_pos 0 +#define reg_top_gpiot2_o_len 1 +#define reg_top_gpiot2_o_lsb 0 +#define p_reg_top_gpiot2_en 0xD8EC +#define reg_top_gpiot2_en_pos 0 +#define reg_top_gpiot2_en_len 1 +#define reg_top_gpiot2_en_lsb 0 +#define p_reg_top_gpiot2_on 0xD8ED +#define reg_top_gpiot2_on_pos 0 +#define reg_top_gpiot2_on_len 1 +#define reg_top_gpiot2_on_lsb 0 +#define p_reg_top_lock2_out 0xD8EE +#define reg_top_lock2_out_pos 0 +#define reg_top_lock2_out_len 1 +#define reg_top_lock2_out_lsb 0 +#define p_reg_top_lock2_tpsd 0xD8EF +#define reg_top_lock2_tpsd_pos 0 +#define reg_top_lock2_tpsd_len 1 +#define reg_top_lock2_tpsd_lsb 0 +#define p_reg_top_lock2_o 0xD8F0 +#define reg_top_lock2_o_pos 0 +#define reg_top_lock2_o_len 1 +#define reg_top_lock2_o_lsb 0 +#define p_reg_top_lock2_en 0xD8F1 +#define reg_top_lock2_en_pos 0 +#define reg_top_lock2_en_len 1 +#define reg_top_lock2_en_lsb 0 +#define p_reg_top_lock2_on 0xD8F2 +#define reg_top_lock2_on_pos 0 +#define reg_top_lock2_on_len 1 +#define reg_top_lock2_on_lsb 0 +#define p_reg_top_lock1_out 0xD8F3 +#define reg_top_lock1_out_pos 0 +#define reg_top_lock1_out_len 1 +#define reg_top_lock1_out_lsb 0 +#define p_reg_top_lock1_tpsd 0xD8F4 +#define reg_top_lock1_tpsd_pos 0 +#define reg_top_lock1_tpsd_len 1 +#define reg_top_lock1_tpsd_lsb 0 +#define p_reg_top_lock1_o 0xD8F5 +#define reg_top_lock1_o_pos 0 +#define reg_top_lock1_o_len 1 +#define reg_top_lock1_o_lsb 0 +#define p_reg_top_lock1_en 0xD8F6 +#define reg_top_lock1_en_pos 0 +#define reg_top_lock1_en_len 1 +#define reg_top_lock1_en_lsb 0 +#define p_reg_top_lock1_on 0xD8F7 +#define reg_top_lock1_on_pos 0 +#define reg_top_lock1_on_len 1 +#define reg_top_lock1_on_lsb 0 +#define p_reg_top_lock4_out 0xD8F8 +#define reg_top_lock4_out_pos 0 +#define reg_top_lock4_out_len 1 +#define reg_top_lock4_out_lsb 0 +#define p_reg_top_lock4_tpsd 0xD8F9 +#define reg_top_lock4_tpsd_pos 0 +#define reg_top_lock4_tpsd_len 1 +#define reg_top_lock4_tpsd_lsb 0 +#define p_reg_top_lock4_o 0xD8FA +#define reg_top_lock4_o_pos 0 +#define reg_top_lock4_o_len 1 +#define reg_top_lock4_o_lsb 0 +#define p_reg_top_lock4_en 0xD8FB +#define reg_top_lock4_en_pos 0 +#define reg_top_lock4_en_len 1 +#define reg_top_lock4_en_lsb 0 +#define p_reg_top_lock4_on 0xD8FC +#define reg_top_lock4_on_pos 0 +#define reg_top_lock4_on_len 1 +#define reg_top_lock4_on_lsb 0 +#define p_reg_top_lock3_out 0xD8FD +#define reg_top_lock3_out_pos 0 +#define reg_top_lock3_out_len 1 +#define reg_top_lock3_out_lsb 0 +#define p_reg_top_lock3_tpsd 0xD8FE +#define reg_top_lock3_tpsd_pos 0 +#define reg_top_lock3_tpsd_len 1 +#define reg_top_lock3_tpsd_lsb 0 +#define p_reg_top_lock3_o 0xD8FF +#define reg_top_lock3_o_pos 0 +#define reg_top_lock3_o_len 1 +#define reg_top_lock3_o_lsb 0 +#define p_reg_top_lock3_en 0xD900 +#define reg_top_lock3_en_pos 0 +#define reg_top_lock3_en_len 1 +#define reg_top_lock3_en_lsb 0 +#define p_reg_top_lock3_on 0xD901 +#define reg_top_lock3_on_pos 0 +#define reg_top_lock3_on_len 1 +#define reg_top_lock3_on_lsb 0 +#define p_reg_top_pwm0_en 0xD902 +#define reg_top_pwm0_en_pos 0 +#define reg_top_pwm0_en_len 1 +#define reg_top_pwm0_en_lsb 0 +#define p_reg_top_pwm1_en 0xD903 +#define reg_top_pwm1_en_pos 0 +#define reg_top_pwm1_en_len 1 +#define reg_top_pwm1_en_lsb 0 +#define p_reg_top_pwm2_en 0xD904 +#define reg_top_pwm2_en_pos 0 +#define reg_top_pwm2_en_len 1 +#define reg_top_pwm2_en_lsb 0 +#define p_reg_top_pwm3_en 0xD905 +#define reg_top_pwm3_en_pos 0 +#define reg_top_pwm3_en_len 1 +#define reg_top_pwm3_en_lsb 0 +#define p_reg_top_pwm0_gpio 0xD906 +#define reg_top_pwm0_gpio_pos 0 +#define reg_top_pwm0_gpio_len 1 +#define reg_top_pwm0_gpio_lsb 0 +#define p_reg_top_pwm0_pos 0xD907 +#define reg_top_pwm0_pos_pos 0 +#define reg_top_pwm0_pos_len 3 +#define reg_top_pwm0_pos_lsb 0 +#define p_reg_top_pwm0_width 0xD908 +#define reg_top_pwm0_width_pos 0 +#define reg_top_pwm0_width_len 2 +#define reg_top_pwm0_width_lsb 0 +#define p_reg_top_pwm0_duration 0xD909 +#define reg_top_pwm0_duration_pos 0 +#define reg_top_pwm0_duration_len 8 +#define reg_top_pwm0_duration_lsb 0 +#define p_reg_top_pwm1_gpio 0xD90A +#define reg_top_pwm1_gpio_pos 0 +#define reg_top_pwm1_gpio_len 1 +#define reg_top_pwm1_gpio_lsb 0 +#define p_reg_top_pwm1_pos 0xD90B +#define reg_top_pwm1_pos_pos 0 +#define reg_top_pwm1_pos_len 3 +#define reg_top_pwm1_pos_lsb 0 +#define p_reg_top_pwm1_width 0xD90C +#define reg_top_pwm1_width_pos 0 +#define reg_top_pwm1_width_len 2 +#define reg_top_pwm1_width_lsb 0 +#define p_reg_top_pwm1_duration 0xD90D +#define reg_top_pwm1_duration_pos 0 +#define reg_top_pwm1_duration_len 8 +#define reg_top_pwm1_duration_lsb 0 +#define p_reg_top_pwm2_gpio 0xD90E +#define reg_top_pwm2_gpio_pos 0 +#define reg_top_pwm2_gpio_len 1 +#define reg_top_pwm2_gpio_lsb 0 +#define p_reg_top_pwm2_pos 0xD90F +#define reg_top_pwm2_pos_pos 0 +#define reg_top_pwm2_pos_len 3 +#define reg_top_pwm2_pos_lsb 0 +#define p_reg_top_pwm2_width 0xD910 +#define reg_top_pwm2_width_pos 0 +#define reg_top_pwm2_width_len 2 +#define reg_top_pwm2_width_lsb 0 +#define p_reg_top_pwm2_duration 0xD911 +#define reg_top_pwm2_duration_pos 0 +#define reg_top_pwm2_duration_len 8 +#define reg_top_pwm2_duration_lsb 0 +#define p_reg_top_pwm3_gpio 0xD912 +#define reg_top_pwm3_gpio_pos 0 +#define reg_top_pwm3_gpio_len 1 +#define reg_top_pwm3_gpio_lsb 0 +#define p_reg_top_pwm3_pos 0xD913 +#define reg_top_pwm3_pos_pos 0 +#define reg_top_pwm3_pos_len 3 +#define reg_top_pwm3_pos_lsb 0 +#define p_reg_top_pwm3_width 0xD914 +#define reg_top_pwm3_width_pos 0 +#define reg_top_pwm3_width_len 2 +#define reg_top_pwm3_width_lsb 0 +#define p_reg_top_pwm3_duration 0xD915 +#define reg_top_pwm3_duration_pos 0 +#define reg_top_pwm3_duration_len 8 +#define reg_top_pwm3_duration_lsb 0 +#define p_reg_top_hosta_mpeg_par_mode 0xD916 +#define reg_top_hosta_mpeg_par_mode_pos 0 +#define reg_top_hosta_mpeg_par_mode_len 1 +#define reg_top_hosta_mpeg_par_mode_lsb 0 +#define p_reg_top_hosta_mpeg_ser_mode 0xD917 +#define reg_top_hosta_mpeg_ser_mode_pos 0 +#define reg_top_hosta_mpeg_ser_mode_len 1 +#define reg_top_hosta_mpeg_ser_mode_lsb 0 +#define p_reg_top_hosta_mpeg_ser_do7 0xD918 +#define reg_top_hosta_mpeg_ser_do7_pos 0 +#define reg_top_hosta_mpeg_ser_do7_len 1 +#define reg_top_hosta_mpeg_ser_do7_lsb 0 +#define p_reg_top_hosta_dca_upper 0xD919 +#define reg_top_hosta_dca_upper_pos 0 +#define reg_top_hosta_dca_upper_len 1 +#define reg_top_hosta_dca_upper_lsb 0 +#define p_reg_top_hosta_dca_lower 0xD91A +#define reg_top_hosta_dca_lower_pos 0 +#define reg_top_hosta_dca_lower_len 1 +#define reg_top_hosta_dca_lower_lsb 0 +#define p_reg_top_hostb_mpeg_par_mode 0xD91B +#define reg_top_hostb_mpeg_par_mode_pos 0 +#define reg_top_hostb_mpeg_par_mode_len 1 +#define reg_top_hostb_mpeg_par_mode_lsb 0 +#define p_reg_top_hostb_mpeg_ser_mode 0xD91C +#define reg_top_hostb_mpeg_ser_mode_pos 0 +#define reg_top_hostb_mpeg_ser_mode_len 1 +#define reg_top_hostb_mpeg_ser_mode_lsb 0 +#define p_reg_top_hostb_mpeg_ser_do7 0xD91D +#define reg_top_hostb_mpeg_ser_do7_pos 0 +#define reg_top_hostb_mpeg_ser_do7_len 1 +#define reg_top_hostb_mpeg_ser_do7_lsb 0 +#define p_reg_top_hostb_dca_upper 0xD91E +#define reg_top_hostb_dca_upper_pos 0 +#define reg_top_hostb_dca_upper_len 1 +#define reg_top_hostb_dca_upper_lsb 0 +#define p_reg_top_hostb_dca_lower 0xD91F +#define reg_top_hostb_dca_lower_pos 0 +#define reg_top_hostb_dca_lower_len 1 +#define reg_top_hostb_dca_lower_lsb 0 +#define p_reg_top_host_reverse 0xD920 +#define reg_top_host_reverse_pos 0 +#define reg_top_host_reverse_len 1 +#define reg_top_host_reverse_lsb 0 +#define p_reg_top_hosta_ccir 0xD921 +#define reg_top_hosta_ccir_pos 0 +#define reg_top_hosta_ccir_len 1 +#define reg_top_hosta_ccir_lsb 0 +#define p_reg_top_hostb_ccir 0xD922 +#define reg_top_hostb_ccir_pos 0 +#define reg_top_hostb_ccir_len 1 +#define reg_top_hostb_ccir_lsb 0 +#define p_reg_top_i2s_master_mode 0xD923 +#define reg_top_i2s_master_mode_pos 0 +#define reg_top_i2s_master_mode_len 1 +#define reg_top_i2s_master_mode_lsb 0 +#define p_reg_usb_cfg_speed 0xDD00 +#define reg_usb_cfg_speed_pos 0 +#define reg_usb_cfg_speed_len 1 +#define reg_usb_cfg_speed_lsb 0 +#define p_reg_usb_cfg_utmi16 0xDD00 +#define reg_usb_cfg_utmi16_pos 1 +#define reg_usb_cfg_utmi16_len 1 +#define reg_usb_cfg_utmi16_lsb 0 +#define p_reg_usb_cfg_test 0xDD00 +#define reg_usb_cfg_test_pos 3 +#define reg_usb_cfg_test_len 3 +#define reg_usb_cfg_test_lsb 0 +#define p_reg_usb_port_sim_reset 0xDD00 +#define reg_usb_port_sim_reset_pos 6 +#define reg_usb_port_sim_reset_len 1 +#define reg_usb_port_sim_reset_lsb 0 +#define p_reg_usb_port_run 0xDD00 +#define reg_usb_port_run_pos 7 +#define reg_usb_port_run_len 1 +#define reg_usb_port_run_lsb 0 +#define r_usb_line_state_0 0xDD01 +#define usb_line_state_0_pos 0 +#define usb_line_state_0_len 1 +#define usb_line_state_0_lsb 0 +#define r_usb_line_state_1 0xDD01 +#define usb_line_state_1_pos 1 +#define usb_line_state_1_len 1 +#define usb_line_state_1_lsb 0 +#define r_reg_usb_status_speed 0xDD01 +#define reg_usb_status_speed_pos 2 +#define reg_usb_status_speed_len 1 +#define reg_usb_status_speed_lsb 0 +#define r_reg_usb_status_connect 0xDD01 +#define reg_usb_status_connect_pos 3 +#define reg_usb_status_connect_len 1 +#define reg_usb_status_connect_lsb 0 +#define r_reg_usb_rx_buf 0xDD01 +#define reg_usb_rx_buf_pos 4 +#define reg_usb_rx_buf_len 1 +#define reg_usb_rx_buf_lsb 0 +#define r_reg_usb_port_reset 0xDD01 +#define reg_usb_port_reset_pos 5 +#define reg_usb_port_reset_len 1 +#define reg_usb_port_reset_lsb 0 +#define r_reg_usb_port_suspend 0xDD01 +#define reg_usb_port_suspend_pos 6 +#define reg_usb_port_suspend_len 1 +#define reg_usb_port_suspend_lsb 0 +#define p_reg_ep1_tx_type 0xDD07 +#define reg_ep1_tx_type_pos 2 +#define reg_ep1_tx_type_len 1 +#define reg_ep1_tx_type_lsb 0 +#define p_reg_ep2_rx_type 0xDD07 +#define reg_ep2_rx_type_pos 3 +#define reg_ep2_rx_type_len 1 +#define reg_ep2_rx_type_lsb 0 +#define p_reg_ep3_tx_type 0xDD07 +#define reg_ep3_tx_type_pos 4 +#define reg_ep3_tx_type_len 1 +#define reg_ep3_tx_type_lsb 0 +#define p_reg_ep4_tx_type 0xDD07 +#define reg_ep4_tx_type_pos 5 +#define reg_ep4_tx_type_len 1 +#define reg_ep4_tx_type_lsb 0 +#define p_reg_ep5_tx_type 0xDD07 +#define reg_ep5_tx_type_pos 6 +#define reg_ep5_tx_type_len 1 +#define reg_ep5_tx_type_lsb 0 +#define p_reg_ep6_tx_type 0xDD07 +#define reg_ep6_tx_type_pos 7 +#define reg_ep6_tx_type_len 1 +#define reg_ep6_tx_type_lsb 0 +#define p_reg_ep0_max_pkt 0xDD08 +#define reg_ep0_max_pkt_pos 0 +#define reg_ep0_max_pkt_len 8 +#define reg_ep0_max_pkt_lsb 0 +#define p_reg_ep2_max_pkt 0xDD0A +#define reg_ep2_max_pkt_pos 0 +#define reg_ep2_max_pkt_len 8 +#define reg_ep2_max_pkt_lsb 0 +#define p_reg_ep4_max_pkt 0xDD0C +#define reg_ep4_max_pkt_pos 0 +#define reg_ep4_max_pkt_len 8 +#define reg_ep4_max_pkt_lsb 0 +#define p_reg_ep5_max_pkt 0xDD0D +#define reg_ep5_max_pkt_pos 0 +#define reg_ep5_max_pkt_len 8 +#define reg_ep5_max_pkt_lsb 0 +#define p_reg_ep6_max_pkt_7_0 0xDD0E +#define reg_ep6_max_pkt_7_0_pos 0 +#define reg_ep6_max_pkt_7_0_len 8 +#define reg_ep6_max_pkt_7_0_lsb 0 +#define p_reg_ep6_max_pkt_15_8 0xDD0F +#define reg_ep6_max_pkt_15_8_pos 0 +#define reg_ep6_max_pkt_15_8_len 8 +#define reg_ep6_max_pkt_15_8_lsb 8 +#define p_reg_usb_addr 0xDD10 +#define reg_usb_addr_pos 0 +#define reg_usb_addr_len 7 +#define reg_usb_addr_lsb 0 +#define p_reg_usb_addr_now 0xDD10 +#define reg_usb_addr_now_pos 7 +#define reg_usb_addr_now_len 1 +#define reg_usb_addr_now_lsb 0 +#define p_reg_ep0_tx_en 0xDD11 +#define reg_ep0_tx_en_pos 0 +#define reg_ep0_tx_en_len 1 +#define reg_ep0_tx_en_lsb 0 +#define p_reg_ep0_rx_en 0xDD11 +#define reg_ep0_rx_en_pos 1 +#define reg_ep0_rx_en_len 1 +#define reg_ep0_rx_en_lsb 0 +#define p_reg_ep1_tx_en 0xDD11 +#define reg_ep1_tx_en_pos 2 +#define reg_ep1_tx_en_len 1 +#define reg_ep1_tx_en_lsb 0 +#define p_reg_ep2_rx_en 0xDD11 +#define reg_ep2_rx_en_pos 3 +#define reg_ep2_rx_en_len 1 +#define reg_ep2_rx_en_lsb 0 +#define p_reg_ep3_tx_en 0xDD11 +#define reg_ep3_tx_en_pos 4 +#define reg_ep3_tx_en_len 1 +#define reg_ep3_tx_en_lsb 0 +#define p_reg_ep4_tx_en 0xDD11 +#define reg_ep4_tx_en_pos 5 +#define reg_ep4_tx_en_len 1 +#define reg_ep4_tx_en_lsb 0 +#define p_reg_ep5_tx_en 0xDD11 +#define reg_ep5_tx_en_pos 6 +#define reg_ep5_tx_en_len 1 +#define reg_ep5_tx_en_lsb 0 +#define p_reg_ep6_tx_en 0xDD11 +#define reg_ep6_tx_en_pos 7 +#define reg_ep6_tx_en_len 1 +#define reg_ep6_tx_en_lsb 0 +#define p_reg_ep0_tx_stall 0xDD12 +#define reg_ep0_tx_stall_pos 0 +#define reg_ep0_tx_stall_len 1 +#define reg_ep0_tx_stall_lsb 0 +#define p_reg_ep0_rx_stall 0xDD12 +#define reg_ep0_rx_stall_pos 1 +#define reg_ep0_rx_stall_len 1 +#define reg_ep0_rx_stall_lsb 0 +#define p_reg_ep1_tx_stall 0xDD12 +#define reg_ep1_tx_stall_pos 2 +#define reg_ep1_tx_stall_len 1 +#define reg_ep1_tx_stall_lsb 0 +#define p_reg_ep2_rx_stall 0xDD12 +#define reg_ep2_rx_stall_pos 3 +#define reg_ep2_rx_stall_len 1 +#define reg_ep2_rx_stall_lsb 0 +#define p_reg_ep3_tx_stall 0xDD12 +#define reg_ep3_tx_stall_pos 4 +#define reg_ep3_tx_stall_len 1 +#define reg_ep3_tx_stall_lsb 0 +#define p_reg_ep4_tx_stall 0xDD12 +#define reg_ep4_tx_stall_pos 5 +#define reg_ep4_tx_stall_len 1 +#define reg_ep4_tx_stall_lsb 0 +#define p_reg_ep5_tx_stall 0xDD12 +#define reg_ep5_tx_stall_pos 6 +#define reg_ep5_tx_stall_len 1 +#define reg_ep5_tx_stall_lsb 0 +#define p_reg_ep6_tx_stall 0xDD12 +#define reg_ep6_tx_stall_pos 7 +#define reg_ep6_tx_stall_len 1 +#define reg_ep6_tx_stall_lsb 0 +#define p_reg_ep0_tx_nak 0xDD13 +#define reg_ep0_tx_nak_pos 0 +#define reg_ep0_tx_nak_len 1 +#define reg_ep0_tx_nak_lsb 0 +#define p_reg_ep0_rx_nak 0xDD13 +#define reg_ep0_rx_nak_pos 1 +#define reg_ep0_rx_nak_len 1 +#define reg_ep0_rx_nak_lsb 0 +#define p_reg_ep1_tx_nak 0xDD13 +#define reg_ep1_tx_nak_pos 2 +#define reg_ep1_tx_nak_len 1 +#define reg_ep1_tx_nak_lsb 0 +#define p_reg_ep2_rx_nak 0xDD13 +#define reg_ep2_rx_nak_pos 3 +#define reg_ep2_rx_nak_len 1 +#define reg_ep2_rx_nak_lsb 0 +#define p_reg_ep3_tx_nak 0xDD13 +#define reg_ep3_tx_nak_pos 4 +#define reg_ep3_tx_nak_len 1 +#define reg_ep3_tx_nak_lsb 0 +#define p_reg_ep4_tx_nak 0xDD13 +#define reg_ep4_tx_nak_pos 5 +#define reg_ep4_tx_nak_len 1 +#define reg_ep4_tx_nak_lsb 0 +#define p_reg_ep5_tx_nak 0xDD13 +#define reg_ep5_tx_nak_pos 6 +#define reg_ep5_tx_nak_len 1 +#define reg_ep5_tx_nak_lsb 0 +#define p_reg_ep6_tx_nak 0xDD13 +#define reg_ep6_tx_nak_pos 7 +#define reg_ep6_tx_nak_len 1 +#define reg_ep6_tx_nak_lsb 0 +#define p_reg_ep0_tx_nak_int_en 0xDD14 +#define reg_ep0_tx_nak_int_en_pos 0 +#define reg_ep0_tx_nak_int_en_len 1 +#define reg_ep0_tx_nak_int_en_lsb 0 +#define p_reg_ep0_rx_nak_int_en 0xDD14 +#define reg_ep0_rx_nak_int_en_pos 1 +#define reg_ep0_rx_nak_int_en_len 1 +#define reg_ep0_rx_nak_int_en_lsb 0 +#define p_reg_ep1_tx_nak_int_en 0xDD14 +#define reg_ep1_tx_nak_int_en_pos 2 +#define reg_ep1_tx_nak_int_en_len 1 +#define reg_ep1_tx_nak_int_en_lsb 0 +#define p_reg_ep2_rx_nak_int_en 0xDD14 +#define reg_ep2_rx_nak_int_en_pos 3 +#define reg_ep2_rx_nak_int_en_len 1 +#define reg_ep2_rx_nak_int_en_lsb 0 +#define p_reg_ep3_tx_nak_int_en 0xDD14 +#define reg_ep3_tx_nak_int_en_pos 4 +#define reg_ep3_tx_nak_int_en_len 1 +#define reg_ep3_tx_nak_int_en_lsb 0 +#define p_reg_ep4_tx_nak_int_en 0xDD14 +#define reg_ep4_tx_nak_int_en_pos 5 +#define reg_ep4_tx_nak_int_en_len 1 +#define reg_ep4_tx_nak_int_en_lsb 0 +#define p_reg_ep5_tx_nak_int_en 0xDD14 +#define reg_ep5_tx_nak_int_en_pos 6 +#define reg_ep5_tx_nak_int_en_len 1 +#define reg_ep5_tx_nak_int_en_lsb 0 +#define p_reg_ep6_tx_nak_int_en 0xDD14 +#define reg_ep6_tx_nak_int_en_pos 7 +#define reg_ep6_tx_nak_int_en_len 1 +#define reg_ep6_tx_nak_int_en_lsb 0 +#define p_reg_ep0_tx_done_int_en 0xDD15 +#define reg_ep0_tx_done_int_en_pos 0 +#define reg_ep0_tx_done_int_en_len 1 +#define reg_ep0_tx_done_int_en_lsb 0 +#define p_reg_ep0_rx_done_int_en 0xDD15 +#define reg_ep0_rx_done_int_en_pos 1 +#define reg_ep0_rx_done_int_en_len 1 +#define reg_ep0_rx_done_int_en_lsb 0 +#define p_reg_ep1_tx_done_int_en 0xDD15 +#define reg_ep1_tx_done_int_en_pos 2 +#define reg_ep1_tx_done_int_en_len 1 +#define reg_ep1_tx_done_int_en_lsb 0 +#define p_reg_ep2_rx_done_int_en 0xDD15 +#define reg_ep2_rx_done_int_en_pos 3 +#define reg_ep2_rx_done_int_en_len 1 +#define reg_ep2_rx_done_int_en_lsb 0 +#define p_reg_ep3_tx_done_int_en 0xDD15 +#define reg_ep3_tx_done_int_en_pos 4 +#define reg_ep3_tx_done_int_en_len 1 +#define reg_ep3_tx_done_int_en_lsb 0 +#define p_reg_ep4_tx_done_int_en 0xDD15 +#define reg_ep4_tx_done_int_en_pos 5 +#define reg_ep4_tx_done_int_en_len 1 +#define reg_ep4_tx_done_int_en_lsb 0 +#define p_reg_ep5_tx_done_int_en 0xDD15 +#define reg_ep5_tx_done_int_en_pos 6 +#define reg_ep5_tx_done_int_en_len 1 +#define reg_ep5_tx_done_int_en_lsb 0 +#define p_reg_ep6_tx_done_int_en 0xDD15 +#define reg_ep6_tx_done_int_en_pos 7 +#define reg_ep6_tx_done_int_en_len 1 +#define reg_ep6_tx_done_int_en_lsb 0 +#define p_reg_ep0_tx_fail_int_en 0xDD16 +#define reg_ep0_tx_fail_int_en_pos 0 +#define reg_ep0_tx_fail_int_en_len 1 +#define reg_ep0_tx_fail_int_en_lsb 0 +#define p_reg_ep0_rx_fail_int_en 0xDD16 +#define reg_ep0_rx_fail_int_en_pos 1 +#define reg_ep0_rx_fail_int_en_len 1 +#define reg_ep0_rx_fail_int_en_lsb 0 +#define p_reg_ep1_tx_fail_int_en 0xDD16 +#define reg_ep1_tx_fail_int_en_pos 2 +#define reg_ep1_tx_fail_int_en_len 1 +#define reg_ep1_tx_fail_int_en_lsb 0 +#define p_reg_ep2_rx_fail_int_en 0xDD16 +#define reg_ep2_rx_fail_int_en_pos 3 +#define reg_ep2_rx_fail_int_en_len 1 +#define reg_ep2_rx_fail_int_en_lsb 0 +#define p_reg_ep3_tx_fail_int_en 0xDD16 +#define reg_ep3_tx_fail_int_en_pos 4 +#define reg_ep3_tx_fail_int_en_len 1 +#define reg_ep3_tx_fail_int_en_lsb 0 +#define p_reg_ep4_tx_fail_int_en 0xDD16 +#define reg_ep4_tx_fail_int_en_pos 5 +#define reg_ep4_tx_fail_int_en_len 1 +#define reg_ep4_tx_fail_int_en_lsb 0 +#define p_reg_ep5_tx_fail_int_en 0xDD16 +#define reg_ep5_tx_fail_int_en_pos 6 +#define reg_ep5_tx_fail_int_en_len 1 +#define reg_ep5_tx_fail_int_en_lsb 0 +#define p_reg_ep6_tx_fail_int_en 0xDD16 +#define reg_ep6_tx_fail_int_en_pos 7 +#define reg_ep6_tx_fail_int_en_len 1 +#define reg_ep6_tx_fail_int_en_lsb 0 +#define p_reg_suspend_int_en 0xDD17 +#define reg_suspend_int_en_pos 0 +#define reg_suspend_int_en_len 1 +#define reg_suspend_int_en_lsb 0 +#define p_reg_bus_reset_int_en 0xDD17 +#define reg_bus_reset_int_en_pos 1 +#define reg_bus_reset_int_en_len 1 +#define reg_bus_reset_int_en_lsb 0 +#define p_reg_ep0_setup_int_en 0xDD17 +#define reg_ep0_setup_int_en_pos 2 +#define reg_ep0_setup_int_en_len 1 +#define reg_ep0_setup_int_en_lsb 0 +#define p_reg_ep0_tx_nak_int 0xDD18 +#define reg_ep0_tx_nak_int_pos 0 +#define reg_ep0_tx_nak_int_len 1 +#define reg_ep0_tx_nak_int_lsb 0 +#define p_reg_ep0_rx_nak_int 0xDD18 +#define reg_ep0_rx_nak_int_pos 1 +#define reg_ep0_rx_nak_int_len 1 +#define reg_ep0_rx_nak_int_lsb 0 +#define p_reg_ep1_tx_nak_int 0xDD18 +#define reg_ep1_tx_nak_int_pos 2 +#define reg_ep1_tx_nak_int_len 1 +#define reg_ep1_tx_nak_int_lsb 0 +#define p_reg_ep2_rx_nak_int 0xDD18 +#define reg_ep2_rx_nak_int_pos 3 +#define reg_ep2_rx_nak_int_len 1 +#define reg_ep2_rx_nak_int_lsb 0 +#define p_reg_ep3_tx_nak_int 0xDD18 +#define reg_ep3_tx_nak_int_pos 4 +#define reg_ep3_tx_nak_int_len 1 +#define reg_ep3_tx_nak_int_lsb 0 +#define p_reg_ep4_tx_nak_int 0xDD18 +#define reg_ep4_tx_nak_int_pos 5 +#define reg_ep4_tx_nak_int_len 1 +#define reg_ep4_tx_nak_int_lsb 0 +#define p_reg_ep5_tx_nak_int 0xDD18 +#define reg_ep5_tx_nak_int_pos 6 +#define reg_ep5_tx_nak_int_len 1 +#define reg_ep5_tx_nak_int_lsb 0 +#define p_reg_ep6_tx_nak_int 0xDD18 +#define reg_ep6_tx_nak_int_pos 7 +#define reg_ep6_tx_nak_int_len 1 +#define reg_ep6_tx_nak_int_lsb 0 +#define p_reg_ep0_tx_done_int 0xDD19 +#define reg_ep0_tx_done_int_pos 0 +#define reg_ep0_tx_done_int_len 1 +#define reg_ep0_tx_done_int_lsb 0 +#define p_reg_ep0_rx_done_int 0xDD19 +#define reg_ep0_rx_done_int_pos 1 +#define reg_ep0_rx_done_int_len 1 +#define reg_ep0_rx_done_int_lsb 0 +#define p_reg_ep1_tx_done_int 0xDD19 +#define reg_ep1_tx_done_int_pos 2 +#define reg_ep1_tx_done_int_len 1 +#define reg_ep1_tx_done_int_lsb 0 +#define p_reg_ep2_rx_done_int 0xDD19 +#define reg_ep2_rx_done_int_pos 3 +#define reg_ep2_rx_done_int_len 1 +#define reg_ep2_rx_done_int_lsb 0 +#define p_reg_ep3_tx_done_int 0xDD19 +#define reg_ep3_tx_done_int_pos 4 +#define reg_ep3_tx_done_int_len 1 +#define reg_ep3_tx_done_int_lsb 0 +#define p_reg_ep4_tx_done_int 0xDD19 +#define reg_ep4_tx_done_int_pos 5 +#define reg_ep4_tx_done_int_len 1 +#define reg_ep4_tx_done_int_lsb 0 +#define p_reg_ep5_tx_done_int 0xDD19 +#define reg_ep5_tx_done_int_pos 6 +#define reg_ep5_tx_done_int_len 1 +#define reg_ep5_tx_done_int_lsb 0 +#define p_reg_ep6_tx_done_int 0xDD19 +#define reg_ep6_tx_done_int_pos 7 +#define reg_ep6_tx_done_int_len 1 +#define reg_ep6_tx_done_int_lsb 0 +#define p_reg_ep0_tx_fail_int 0xDD1A +#define reg_ep0_tx_fail_int_pos 0 +#define reg_ep0_tx_fail_int_len 1 +#define reg_ep0_tx_fail_int_lsb 0 +#define p_reg_ep0_rx_fail_int 0xDD1A +#define reg_ep0_rx_fail_int_pos 1 +#define reg_ep0_rx_fail_int_len 1 +#define reg_ep0_rx_fail_int_lsb 0 +#define p_reg_ep1_tx_fail_int 0xDD1A +#define reg_ep1_tx_fail_int_pos 2 +#define reg_ep1_tx_fail_int_len 1 +#define reg_ep1_tx_fail_int_lsb 0 +#define p_reg_ep2_rx_fail_int 0xDD1A +#define reg_ep2_rx_fail_int_pos 3 +#define reg_ep2_rx_fail_int_len 1 +#define reg_ep2_rx_fail_int_lsb 0 +#define p_reg_ep3_tx_fail_int 0xDD1A +#define reg_ep3_tx_fail_int_pos 4 +#define reg_ep3_tx_fail_int_len 1 +#define reg_ep3_tx_fail_int_lsb 0 +#define p_reg_ep4_tx_fail_int 0xDD1A +#define reg_ep4_tx_fail_int_pos 5 +#define reg_ep4_tx_fail_int_len 1 +#define reg_ep4_tx_fail_int_lsb 0 +#define p_reg_ep5_tx_fail_int 0xDD1A +#define reg_ep5_tx_fail_int_pos 6 +#define reg_ep5_tx_fail_int_len 1 +#define reg_ep5_tx_fail_int_lsb 0 +#define p_reg_ep6_tx_fail_int 0xDD1A +#define reg_ep6_tx_fail_int_pos 7 +#define reg_ep6_tx_fail_int_len 1 +#define reg_ep6_tx_fail_int_lsb 0 +#define p_reg_suspend_int 0xDD1B +#define reg_suspend_int_pos 0 +#define reg_suspend_int_len 1 +#define reg_suspend_int_lsb 0 +#define p_reg_bus_reset_int 0xDD1B +#define reg_bus_reset_int_pos 1 +#define reg_bus_reset_int_len 1 +#define reg_bus_reset_int_lsb 0 +#define p_reg_ep0_setup_int 0xDD1B +#define reg_ep0_setup_int_pos 2 +#define reg_ep0_setup_int_len 1 +#define reg_ep0_setup_int_lsb 0 +#define r_usbc_int 0xDD1B +#define usbc_int_pos 3 +#define usbc_int_len 1 +#define usbc_int_lsb 0 +#define r_usb_ir_int 0xDD1B +#define usb_ir_int_pos 4 +#define usb_ir_int_len 1 +#define usb_ir_int_lsb 0 +#define p_reg_ep0_tx_rst 0xDD1D +#define reg_ep0_tx_rst_pos 0 +#define reg_ep0_tx_rst_len 1 +#define reg_ep0_tx_rst_lsb 0 +#define p_reg_ep0_rx_rst 0xDD1D +#define reg_ep0_rx_rst_pos 1 +#define reg_ep0_rx_rst_len 1 +#define reg_ep0_rx_rst_lsb 0 +#define p_reg_ep1_tx_rst 0xDD1D +#define reg_ep1_tx_rst_pos 2 +#define reg_ep1_tx_rst_len 1 +#define reg_ep1_tx_rst_lsb 0 +#define p_reg_ep2_rx_rst 0xDD1D +#define reg_ep2_rx_rst_pos 3 +#define reg_ep2_rx_rst_len 1 +#define reg_ep2_rx_rst_lsb 0 +#define p_reg_ep3_tx_rst 0xDD1D +#define reg_ep3_tx_rst_pos 4 +#define reg_ep3_tx_rst_len 1 +#define reg_ep3_tx_rst_lsb 0 +#define p_reg_ep4_tx_rst 0xDD1D +#define reg_ep4_tx_rst_pos 5 +#define reg_ep4_tx_rst_len 1 +#define reg_ep4_tx_rst_lsb 0 +#define p_reg_ep5_tx_rst 0xDD1D +#define reg_ep5_tx_rst_pos 6 +#define reg_ep5_tx_rst_len 1 +#define reg_ep5_tx_rst_lsb 0 +#define p_reg_ep6_tx_rst 0xDD1D +#define reg_ep6_tx_rst_pos 7 +#define reg_ep6_tx_rst_len 1 +#define reg_ep6_tx_rst_lsb 0 +#define r_reg_ep0_tx_active 0xDD1E +#define reg_ep0_tx_active_pos 0 +#define reg_ep0_tx_active_len 1 +#define reg_ep0_tx_active_lsb 0 +#define r_reg_ep0_rx_active 0xDD1E +#define reg_ep0_rx_active_pos 1 +#define reg_ep0_rx_active_len 1 +#define reg_ep0_rx_active_lsb 0 +#define r_reg_ep1_tx_active 0xDD1E +#define reg_ep1_tx_active_pos 2 +#define reg_ep1_tx_active_len 1 +#define reg_ep1_tx_active_lsb 0 +#define r_reg_ep2_rx_active 0xDD1E +#define reg_ep2_rx_active_pos 3 +#define reg_ep2_rx_active_len 1 +#define reg_ep2_rx_active_lsb 0 +#define r_reg_ep3_tx_active 0xDD1E +#define reg_ep3_tx_active_pos 4 +#define reg_ep3_tx_active_len 1 +#define reg_ep3_tx_active_lsb 0 +#define r_reg_ep4_tx_active 0xDD1E +#define reg_ep4_tx_active_pos 5 +#define reg_ep4_tx_active_len 1 +#define reg_ep4_tx_active_lsb 0 +#define r_reg_ep5_tx_active 0xDD1E +#define reg_ep5_tx_active_pos 6 +#define reg_ep5_tx_active_len 1 +#define reg_ep5_tx_active_lsb 0 +#define r_reg_ep6_tx_active 0xDD1E +#define reg_ep6_tx_active_pos 7 +#define reg_ep6_tx_active_len 1 +#define reg_ep6_tx_active_lsb 0 +#define p_reg_usb_setup_reset 0xDD1F +#define reg_usb_setup_reset_pos 0 +#define reg_usb_setup_reset_len 1 +#define reg_usb_setup_reset_lsb 0 +#define p_reg_usb_ep4_retry_new 0xDD1F +#define reg_usb_ep4_retry_new_pos 1 +#define reg_usb_ep4_retry_new_len 1 +#define reg_usb_ep4_retry_new_lsb 0 +#define p_reg_usb_ep5_retry_new 0xDD1F +#define reg_usb_ep5_retry_new_pos 2 +#define reg_usb_ep5_retry_new_len 1 +#define reg_usb_ep5_retry_new_lsb 0 +#define p_reg_usb_ep6_retry_new 0xDD1F +#define reg_usb_ep6_retry_new_pos 3 +#define reg_usb_ep6_retry_new_len 1 +#define reg_usb_ep6_retry_new_lsb 0 +#define p_reg_usb_iso_mult_cnt 0xDD20 +#define reg_usb_iso_mult_cnt_pos 0 +#define reg_usb_iso_mult_cnt_len 2 +#define reg_usb_iso_mult_cnt_lsb 0 +#define p_reg_p_iso_fix_en 0xDD21 +#define reg_p_iso_fix_en_pos 0 +#define reg_p_iso_fix_en_len 1 +#define reg_p_iso_fix_en_lsb 0 +#define p_reg_p_iso_fix_rst 0xDD22 +#define reg_p_iso_fix_rst_pos 0 +#define reg_p_iso_fix_rst_len 1 +#define reg_p_iso_fix_rst_lsb 0 +#define p_reg_p_read_point_7_0 0xDD23 +#define reg_p_read_point_7_0_pos 0 +#define reg_p_read_point_7_0_len 8 +#define reg_p_read_point_7_0_lsb 0 +#define p_reg_p_read_point_11_8 0xDD24 +#define reg_p_read_point_11_8_pos 0 +#define reg_p_read_point_11_8_len 4 +#define reg_p_read_point_11_8_lsb 8 +#define p_reg_p_dbg_ctrl 0xDD25 +#define reg_p_dbg_ctrl_pos 0 +#define reg_p_dbg_ctrl_len 3 +#define reg_p_dbg_ctrl_lsb 0 +#define p_reg_p_data_swap 0xDD26 +#define reg_p_data_swap_pos 0 +#define reg_p_data_swap_len 2 +#define reg_p_data_swap_lsb 0 +#define p_reg_ep_rx_addr 0xDD80 +#define reg_ep_rx_addr_pos 2 +#define reg_ep_rx_addr_len 6 +#define reg_ep_rx_addr_lsb 0 +#define p_reg_ep0_tx_addr 0xDD81 +#define reg_ep0_tx_addr_pos 2 +#define reg_ep0_tx_addr_len 6 +#define reg_ep0_tx_addr_lsb 0 +#define p_reg_ep1_tx_addr 0xDD82 +#define reg_ep1_tx_addr_pos 2 +#define reg_ep1_tx_addr_len 6 +#define reg_ep1_tx_addr_lsb 0 +#define p_reg_ep3_tx_addr 0xDD83 +#define reg_ep3_tx_addr_pos 2 +#define reg_ep3_tx_addr_len 6 +#define reg_ep3_tx_addr_lsb 0 +#define p_reg_ep_rx_len 0xDD84 +#define reg_ep_rx_len_pos 0 +#define reg_ep_rx_len_len 8 +#define reg_ep_rx_len_lsb 0 +#define p_reg_ep0_tx_len 0xDD85 +#define reg_ep0_tx_len_pos 0 +#define reg_ep0_tx_len_len 8 +#define reg_ep0_tx_len_lsb 0 +#define p_reg_ep1_tx_len 0xDD86 +#define reg_ep1_tx_len_pos 0 +#define reg_ep1_tx_len_len 8 +#define reg_ep1_tx_len_lsb 0 +#define p_reg_ep3_tx_len 0xDD87 +#define reg_ep3_tx_len_pos 0 +#define reg_ep3_tx_len_len 8 +#define reg_ep3_tx_len_lsb 0 +#define p_reg_ep4_tx_len_7_0 0xDD88 +#define reg_ep4_tx_len_7_0_pos 0 +#define reg_ep4_tx_len_7_0_len 8 +#define reg_ep4_tx_len_7_0_lsb 0 +#define p_reg_ep4_tx_len_15_8 0xDD89 +#define reg_ep4_tx_len_15_8_pos 0 +#define reg_ep4_tx_len_15_8_len 8 +#define reg_ep4_tx_len_15_8_lsb 8 +#define p_reg_ep5_tx_len_7_0 0xDD8A +#define reg_ep5_tx_len_7_0_pos 0 +#define reg_ep5_tx_len_7_0_len 8 +#define reg_ep5_tx_len_7_0_lsb 0 +#define p_reg_ep5_tx_len_15_8 0xDD8B +#define reg_ep5_tx_len_15_8_pos 0 +#define reg_ep5_tx_len_15_8_len 8 +#define reg_ep5_tx_len_15_8_lsb 8 +#define p_reg_usb_reset_addr 0xDD8C +#define reg_usb_reset_addr_pos 0 +#define reg_usb_reset_addr_len 7 +#define reg_usb_reset_addr_lsb 0 +#define p_reg_usb_reset 0xDD8C +#define reg_usb_reset_pos 7 +#define reg_usb_reset_len 1 +#define reg_usb_reset_lsb 0 +#define p_reg_usb_sync_in 0xDD8D +#define reg_usb_sync_in_pos 0 +#define reg_usb_sync_in_len 1 +#define reg_usb_sync_in_lsb 0 +#define p_reg_usb_sync_txready 0xDD8D +#define reg_usb_sync_txready_pos 1 +#define reg_usb_sync_txready_len 1 +#define reg_usb_sync_txready_lsb 0 +#define p_reg_utmi_phy_suspend 0xDD8D +#define reg_utmi_phy_suspend_pos 2 +#define reg_utmi_phy_suspend_len 1 +#define reg_utmi_phy_suspend_lsb 0 +#define p_reg_usb_min_len 0xDD8D +#define reg_usb_min_len_pos 3 +#define reg_usb_min_len_len 1 +#define reg_usb_min_len_lsb 0 +#define p_reg_usb_phy_clksel 0xDD8D +#define reg_usb_phy_clksel_pos 4 +#define reg_usb_phy_clksel_len 1 +#define reg_usb_phy_clksel_lsb 0 +#define p_reg_ep6_tx_len_7_0 0xDD8E +#define reg_ep6_tx_len_7_0_pos 0 +#define reg_ep6_tx_len_7_0_len 8 +#define reg_ep6_tx_len_7_0_lsb 0 +#define p_reg_ep6_tx_len_15_8 0xDD8F +#define reg_ep6_tx_len_15_8_pos 0 +#define reg_ep6_tx_len_15_8_len 8 +#define reg_ep6_tx_len_15_8_lsb 8 +#define p_reg_usb_clk_phase 0xDD93 +#define reg_usb_clk_phase_pos 0 +#define reg_usb_clk_phase_len 2 +#define reg_usb_clk_phase_lsb 0 +#define p_reg_usb_clk_sel 0xDD93 +#define reg_usb_clk_sel_pos 4 +#define reg_usb_clk_sel_len 4 +#define reg_usb_clk_sel_lsb 0 +#define p_reg_usb_fifo_ptr 0xDD94 +#define reg_usb_fifo_ptr_pos 0 +#define reg_usb_fifo_ptr_len 3 +#define reg_usb_fifo_ptr_lsb 0 +#define p_reg_usb_fifo_byte 0xDD94 +#define reg_usb_fifo_byte_pos 3 +#define reg_usb_fifo_byte_len 2 +#define reg_usb_fifo_byte_lsb 0 +#define p_reg_usb_fifo_sys 0xDD94 +#define reg_usb_fifo_sys_pos 5 +#define reg_usb_fifo_sys_len 1 +#define reg_usb_fifo_sys_lsb 0 +#define p_usbdma_utmi_d_ctl_7_0 0xDD9E +#define usbdma_utmi_d_ctl_7_0_pos 0 +#define usbdma_utmi_d_ctl_7_0_len 8 +#define usbdma_utmi_d_ctl_7_0_lsb 0 +#define p_usbdma_utmi_d_ctl_13_8 0xDD9F +#define usbdma_utmi_d_ctl_13_8_pos 0 +#define usbdma_utmi_d_ctl_13_8_len 6 +#define usbdma_utmi_d_ctl_13_8_lsb 8 +#define p_usbdma_utmi_a_ctl_7_0 0xDDA0 +#define usbdma_utmi_a_ctl_7_0_pos 0 +#define usbdma_utmi_a_ctl_7_0_len 8 +#define usbdma_utmi_a_ctl_7_0_lsb 0 +#define p_usbdma_utmi_a_ctl_15_8 0xDDA1 +#define usbdma_utmi_a_ctl_15_8_pos 0 +#define usbdma_utmi_a_ctl_15_8_len 8 +#define usbdma_utmi_a_ctl_15_8_lsb 8 +#define p_usbdma_utmi_a_ctl_23_16 0xDDA2 +#define usbdma_utmi_a_ctl_23_16_pos 0 +#define usbdma_utmi_a_ctl_23_16_len 8 +#define usbdma_utmi_a_ctl_23_16_lsb 16 +#define p_usbdma_utmi_a_ctl_31_24 0xDDA3 +#define usbdma_utmi_a_ctl_31_24_pos 0 +#define usbdma_utmi_a_ctl_31_24_len 8 +#define usbdma_utmi_a_ctl_31_24_lsb 24 +#define p_usbdma_utmi_a_ctl_39_32 0xDDA4 +#define usbdma_utmi_a_ctl_39_32_pos 0 +#define usbdma_utmi_a_ctl_39_32_len 8 +#define usbdma_utmi_a_ctl_39_32_lsb 32 +#define p_usbdma_utmi_a_ctl_47_40 0xDDA5 +#define usbdma_utmi_a_ctl_47_40_pos 0 +#define usbdma_utmi_a_ctl_47_40_len 8 +#define usbdma_utmi_a_ctl_47_40_lsb 40 +#define p_usbdma_utmi_pwrmode 0xDDA6 +#define usbdma_utmi_pwrmode_pos 3 +#define usbdma_utmi_pwrmode_len 1 +#define usbdma_utmi_pwrmode_lsb 0 +#define p_usbdma_utmi_test_out 0xDDA6 +#define usbdma_utmi_test_out_pos 4 +#define usbdma_utmi_test_out_len 1 +#define usbdma_utmi_test_out_lsb 0 +#define p_usbdma_utmi_vbus_int_en 0xDDA7 +#define usbdma_utmi_vbus_int_en_pos 0 +#define usbdma_utmi_vbus_int_en_len 1 +#define usbdma_utmi_vbus_int_en_lsb 0 +#define p_usbdma_utmi_vbus_int_pol 0xDDA7 +#define usbdma_utmi_vbus_int_pol_pos 1 +#define usbdma_utmi_vbus_int_pol_len 1 +#define usbdma_utmi_vbus_int_pol_lsb 0 +#define r_usbdma_utmi_vbus_int 0xDDA8 +#define usbdma_utmi_vbus_int_pos 0 +#define usbdma_utmi_vbus_int_len 1 +#define usbdma_utmi_vbus_int_lsb 0 +#define r_usbdma_utmi_vbus_status 0xDDA8 +#define usbdma_utmi_vbus_status_pos 1 +#define usbdma_utmi_vbus_status_len 1 +#define usbdma_utmi_vbus_status_lsb 0 +#define r_usbdma_utmi_clkrdy 0xDDA8 +#define usbdma_utmi_clkrdy_pos 2 +#define usbdma_utmi_clkrdy_len 1 +#define usbdma_utmi_clkrdy_lsb 0 +#define p_reg_p_usb_iso_ccir_rst 0xDDA9 +#define reg_p_usb_iso_ccir_rst_pos 0 +#define reg_p_usb_iso_ccir_rst_len 1 +#define reg_p_usb_iso_ccir_rst_lsb 0 +#define p_reg_p_usb_iso_ccir 0xDDA9 +#define reg_p_usb_iso_ccir_pos 1 +#define reg_p_usb_iso_ccir_len 1 +#define reg_p_usb_iso_ccir_lsb 0 +#define p_reg_p_ccir_fix_en 0xDDAA +#define reg_p_ccir_fix_en_pos 0 +#define reg_p_ccir_fix_en_len 1 +#define reg_p_ccir_fix_en_lsb 0 +#define p_ir_sys_clk 0xDF80 +#define ir_sys_clk_pos 0 +#define ir_sys_clk_len 8 +#define ir_sys_clk_lsb 0 +#define p_ir_sample_clk 0xDF81 +#define ir_sample_clk_pos 0 +#define ir_sample_clk_len 2 +#define ir_sample_clk_lsb 0 +#define p_ir_idle_polarity 0xDF81 +#define ir_idle_polarity_pos 2 +#define ir_idle_polarity_len 1 +#define ir_idle_polarity_lsb 0 +#define p_ir_fifo_ovfl 0xDF82 +#define ir_fifo_ovfl_pos 0 +#define ir_fifo_ovfl_len 1 +#define ir_fifo_ovfl_lsb 0 +#define r_ir_fifo_empty 0xDF82 +#define ir_fifo_empty_pos 1 +#define ir_fifo_empty_len 1 +#define ir_fifo_empty_lsb 0 +#define r_ir_fifo_cnt 0xDF82 +#define ir_fifo_cnt_pos 2 +#define ir_fifo_cnt_len 3 +#define ir_fifo_cnt_lsb 0 +#define p_ir_fifo_rst 0xDF82 +#define ir_fifo_rst_pos 5 +#define ir_fifo_rst_len 1 +#define ir_fifo_rst_lsb 0 +#define p_reg_ir_out_th0_7_0 0xDF84 +#define reg_ir_out_th0_7_0_pos 0 +#define reg_ir_out_th0_7_0_len 8 +#define reg_ir_out_th0_7_0_lsb 0 +#define p_reg_ir_out_th0_14_8 0xDF85 +#define reg_ir_out_th0_14_8_pos 0 +#define reg_ir_out_th0_14_8_len 7 +#define reg_ir_out_th0_14_8_lsb 8 +#define p_reg_ir_out_th1_7_0 0xDF86 +#define reg_ir_out_th1_7_0_pos 0 +#define reg_ir_out_th1_7_0_len 8 +#define reg_ir_out_th1_7_0_lsb 0 +#define p_reg_ir_out_th1_14_8 0xDF87 +#define reg_ir_out_th1_14_8_pos 0 +#define reg_ir_out_th1_14_8_len 7 +#define reg_ir_out_th1_14_8_lsb 8 +#define p_reg_ir_out_th2_7_0 0xDF88 +#define reg_ir_out_th2_7_0_pos 0 +#define reg_ir_out_th2_7_0_len 8 +#define reg_ir_out_th2_7_0_lsb 0 +#define p_reg_ir_out_th2_14_8 0xDF89 +#define reg_ir_out_th2_14_8_pos 0 +#define reg_ir_out_th2_14_8_len 7 +#define reg_ir_out_th2_14_8_lsb 8 +#define p_reg_ir_out_th3_7_0 0xDF8A +#define reg_ir_out_th3_7_0_pos 0 +#define reg_ir_out_th3_7_0_len 8 +#define reg_ir_out_th3_7_0_lsb 0 +#define p_reg_ir_out_th3_14_8 0xDF8B +#define reg_ir_out_th3_14_8_pos 0 +#define reg_ir_out_th3_14_8_len 7 +#define reg_ir_out_th3_14_8_lsb 8 +#define p_reg_ir_out_th4_7_0 0xDF8C +#define reg_ir_out_th4_7_0_pos 0 +#define reg_ir_out_th4_7_0_len 8 +#define reg_ir_out_th4_7_0_lsb 0 +#define p_reg_ir_out_th4_14_8 0xDF8D +#define reg_ir_out_th4_14_8_pos 0 +#define reg_ir_out_th4_14_8_len 7 +#define reg_ir_out_th4_14_8_lsb 8 +#define p_reg_ir_out_th5_7_0 0xDF8E +#define reg_ir_out_th5_7_0_pos 0 +#define reg_ir_out_th5_7_0_len 8 +#define reg_ir_out_th5_7_0_lsb 0 +#define p_reg_ir_out_th5_14_8 0xDF8F +#define reg_ir_out_th5_14_8_pos 0 +#define reg_ir_out_th5_14_8_len 7 +#define reg_ir_out_th5_14_8_lsb 8 +#define p_reg_ir_out_th6_7_0 0xDF90 +#define reg_ir_out_th6_7_0_pos 0 +#define reg_ir_out_th6_7_0_len 8 +#define reg_ir_out_th6_7_0_lsb 0 +#define p_reg_ir_out_th6_14_8 0xDF91 +#define reg_ir_out_th6_14_8_pos 0 +#define reg_ir_out_th6_14_8_len 7 +#define reg_ir_out_th6_14_8_lsb 8 +#define p_reg_ir_out_th7_7_0 0xDF92 +#define reg_ir_out_th7_7_0_pos 0 +#define reg_ir_out_th7_7_0_len 8 +#define reg_ir_out_th7_7_0_lsb 0 +#define p_reg_ir_out_th7_14_8 0xDF93 +#define reg_ir_out_th7_14_8_pos 0 +#define reg_ir_out_th7_14_8_len 7 +#define reg_ir_out_th7_14_8_lsb 8 +#define p_reg_ir_out_th8_7_0 0xDF94 +#define reg_ir_out_th8_7_0_pos 0 +#define reg_ir_out_th8_7_0_len 8 +#define reg_ir_out_th8_7_0_lsb 0 +#define p_reg_ir_out_th8_14_8 0xDF95 +#define reg_ir_out_th8_14_8_pos 0 +#define reg_ir_out_th8_14_8_len 7 +#define reg_ir_out_th8_14_8_lsb 8 +#define p_reg_ir_out_th9_7_0 0xDF96 +#define reg_ir_out_th9_7_0_pos 0 +#define reg_ir_out_th9_7_0_len 8 +#define reg_ir_out_th9_7_0_lsb 0 +#define p_reg_ir_out_th9_14_8 0xDF97 +#define reg_ir_out_th9_14_8_pos 0 +#define reg_ir_out_th9_14_8_len 7 +#define reg_ir_out_th9_14_8_lsb 8 +#define p_reg_ir_out_th10_7_0 0xDF98 +#define reg_ir_out_th10_7_0_pos 0 +#define reg_ir_out_th10_7_0_len 8 +#define reg_ir_out_th10_7_0_lsb 0 +#define p_reg_ir_out_th10_14_8 0xDF99 +#define reg_ir_out_th10_14_8_pos 0 +#define reg_ir_out_th10_14_8_len 7 +#define reg_ir_out_th10_14_8_lsb 8 +#define p_reg_ir_out_th11_7_0 0xDF9A +#define reg_ir_out_th11_7_0_pos 0 +#define reg_ir_out_th11_7_0_len 8 +#define reg_ir_out_th11_7_0_lsb 0 +#define p_reg_ir_out_th11_14_8 0xDF9B +#define reg_ir_out_th11_14_8_pos 0 +#define reg_ir_out_th11_14_8_len 7 +#define reg_ir_out_th11_14_8_lsb 8 +#define p_reg_ir_out_th12_7_0 0xDF9C +#define reg_ir_out_th12_7_0_pos 0 +#define reg_ir_out_th12_7_0_len 8 +#define reg_ir_out_th12_7_0_lsb 0 +#define p_reg_ir_out_th12_14_8 0xDF9D +#define reg_ir_out_th12_14_8_pos 0 +#define reg_ir_out_th12_14_8_len 7 +#define reg_ir_out_th12_14_8_lsb 8 +#define p_reg_ir_out_th13_7_0 0xDF9E +#define reg_ir_out_th13_7_0_pos 0 +#define reg_ir_out_th13_7_0_len 8 +#define reg_ir_out_th13_7_0_lsb 0 +#define p_reg_ir_out_th13_14_8 0xDF9F +#define reg_ir_out_th13_14_8_pos 0 +#define reg_ir_out_th13_14_8_len 7 +#define reg_ir_out_th13_14_8_lsb 8 +#define p_reg_ir_out_th14_7_0 0xDFA0 +#define reg_ir_out_th14_7_0_pos 0 +#define reg_ir_out_th14_7_0_len 8 +#define reg_ir_out_th14_7_0_lsb 0 +#define p_reg_ir_out_th14_14_8 0xDFA1 +#define reg_ir_out_th14_14_8_pos 0 +#define reg_ir_out_th14_14_8_len 7 +#define reg_ir_out_th14_14_8_lsb 8 +#define p_reg_tuner_data_7_0 0xF000 +#define reg_tuner_data_7_0_pos 0 +#define reg_tuner_data_7_0_len 8 +#define reg_tuner_data_7_0_lsb 0 +#define p_reg_tuner_data_15_8 0xF001 +#define reg_tuner_data_15_8_pos 0 +#define reg_tuner_data_15_8_len 8 +#define reg_tuner_data_15_8_lsb 8 +#define p_reg_tuner_data_23_16 0xF002 +#define reg_tuner_data_23_16_pos 0 +#define reg_tuner_data_23_16_len 8 +#define reg_tuner_data_23_16_lsb 16 +#define p_reg_tuner_data_31_24 0xF003 +#define reg_tuner_data_31_24_pos 0 +#define reg_tuner_data_31_24_len 8 +#define reg_tuner_data_31_24_lsb 24 +#define p_reg_tuner_data_39_32 0xF004 +#define reg_tuner_data_39_32_pos 0 +#define reg_tuner_data_39_32_len 8 +#define reg_tuner_data_39_32_lsb 32 +#define p_reg_tuner_data_47_40 0xF005 +#define reg_tuner_data_47_40_pos 0 +#define reg_tuner_data_47_40_len 8 +#define reg_tuner_data_47_40_lsb 40 +#define p_reg_tuner_data_55_48 0xF006 +#define reg_tuner_data_55_48_pos 0 +#define reg_tuner_data_55_48_len 8 +#define reg_tuner_data_55_48_lsb 48 +#define p_reg_tuner_data_63_56 0xF007 +#define reg_tuner_data_63_56_pos 0 +#define reg_tuner_data_63_56_len 8 +#define reg_tuner_data_63_56_lsb 56 +#define p_reg_tuner_data_71_64 0xF008 +#define reg_tuner_data_71_64_pos 0 +#define reg_tuner_data_71_64_len 8 +#define reg_tuner_data_71_64_lsb 64 +#define p_reg_tuner_data_79_72 0xF009 +#define reg_tuner_data_79_72_pos 0 +#define reg_tuner_data_79_72_len 8 +#define reg_tuner_data_79_72_lsb 72 +#define p_reg_tuner_data_87_80 0xF00A +#define reg_tuner_data_87_80_pos 0 +#define reg_tuner_data_87_80_len 8 +#define reg_tuner_data_87_80_lsb 80 +#define p_reg_tuner_data_95_88 0xF00B +#define reg_tuner_data_95_88_pos 0 +#define reg_tuner_data_95_88_len 8 +#define reg_tuner_data_95_88_lsb 88 +#define p_reg_tuner_data_103_96 0xF00C +#define reg_tuner_data_103_96_pos 0 +#define reg_tuner_data_103_96_len 8 +#define reg_tuner_data_103_96_lsb 96 +#define p_reg_tuner_data_111_104 0xF00D +#define reg_tuner_data_111_104_pos 0 +#define reg_tuner_data_111_104_len 8 +#define reg_tuner_data_111_104_lsb 104 +#define p_reg_tuner_data_119_112 0xF00E +#define reg_tuner_data_119_112_pos 0 +#define reg_tuner_data_119_112_len 8 +#define reg_tuner_data_119_112_lsb 112 +#define p_reg_tuner_data_127_120 0xF00F +#define reg_tuner_data_127_120_pos 0 +#define reg_tuner_data_127_120_len 8 +#define reg_tuner_data_127_120_lsb 120 +#define p_reg_tuner_data_135_128 0xF010 +#define reg_tuner_data_135_128_pos 0 +#define reg_tuner_data_135_128_len 8 +#define reg_tuner_data_135_128_lsb 128 +#define p_reg_tuner_data_143_136 0xF011 +#define reg_tuner_data_143_136_pos 0 +#define reg_tuner_data_143_136_len 8 +#define reg_tuner_data_143_136_lsb 136 +#define p_reg_tuner_data_151_144 0xF012 +#define reg_tuner_data_151_144_pos 0 +#define reg_tuner_data_151_144_len 8 +#define reg_tuner_data_151_144_lsb 144 +#define p_reg_tuner_data_159_152 0xF013 +#define reg_tuner_data_159_152_pos 0 +#define reg_tuner_data_159_152_len 8 +#define reg_tuner_data_159_152_lsb 152 +#define p_reg_tuner_data_167_160 0xF014 +#define reg_tuner_data_167_160_pos 0 +#define reg_tuner_data_167_160_len 8 +#define reg_tuner_data_167_160_lsb 160 +#define p_reg_tuner_data_175_168 0xF015 +#define reg_tuner_data_175_168_pos 0 +#define reg_tuner_data_175_168_len 8 +#define reg_tuner_data_175_168_lsb 168 +#define p_reg_tuner_data_183_176 0xF016 +#define reg_tuner_data_183_176_pos 0 +#define reg_tuner_data_183_176_len 8 +#define reg_tuner_data_183_176_lsb 176 +#define p_reg_tuner_data_191_184 0xF017 +#define reg_tuner_data_191_184_pos 0 +#define reg_tuner_data_191_184_len 8 +#define reg_tuner_data_191_184_lsb 184 +#define p_reg_tuner_data_199_192 0xF018 +#define reg_tuner_data_199_192_pos 0 +#define reg_tuner_data_199_192_len 8 +#define reg_tuner_data_199_192_lsb 192 +#define p_reg_tuner_data_207_200 0xF019 +#define reg_tuner_data_207_200_pos 0 +#define reg_tuner_data_207_200_len 8 +#define reg_tuner_data_207_200_lsb 200 +#define p_reg_tuner_data_215_208 0xF01A +#define reg_tuner_data_215_208_pos 0 +#define reg_tuner_data_215_208_len 8 +#define reg_tuner_data_215_208_lsb 208 +#define p_reg_tuner_data_223_216 0xF01B +#define reg_tuner_data_223_216_pos 0 +#define reg_tuner_data_223_216_len 8 +#define reg_tuner_data_223_216_lsb 216 +#define p_reg_tuner_data_231_224 0xF01C +#define reg_tuner_data_231_224_pos 0 +#define reg_tuner_data_231_224_len 8 +#define reg_tuner_data_231_224_lsb 224 +#define p_reg_tuner_data_239_232 0xF01D +#define reg_tuner_data_239_232_pos 0 +#define reg_tuner_data_239_232_len 8 +#define reg_tuner_data_239_232_lsb 232 +#define p_reg_tuner_data_247_240 0xF01E +#define reg_tuner_data_247_240_pos 0 +#define reg_tuner_data_247_240_len 8 +#define reg_tuner_data_247_240_lsb 240 +#define p_reg_tuner_data_255_248 0xF01F +#define reg_tuner_data_255_248_pos 0 +#define reg_tuner_data_255_248_len 8 +#define reg_tuner_data_255_248_lsb 248 +#define p_reg_tuner_data_263_256 0xF020 +#define reg_tuner_data_263_256_pos 0 +#define reg_tuner_data_263_256_len 8 +#define reg_tuner_data_263_256_lsb 256 +#define p_reg_tuner_data_271_264 0xF021 +#define reg_tuner_data_271_264_pos 0 +#define reg_tuner_data_271_264_len 8 +#define reg_tuner_data_271_264_lsb 264 +#define p_reg_tuner_data_279_272 0xF022 +#define reg_tuner_data_279_272_pos 0 +#define reg_tuner_data_279_272_len 8 +#define reg_tuner_data_279_272_lsb 272 +#define p_reg_tuner_data_287_280 0xF023 +#define reg_tuner_data_287_280_pos 0 +#define reg_tuner_data_287_280_len 8 +#define reg_tuner_data_287_280_lsb 280 +#define p_reg_tuner_data_295_288 0xF024 +#define reg_tuner_data_295_288_pos 0 +#define reg_tuner_data_295_288_len 8 +#define reg_tuner_data_295_288_lsb 288 +#define p_reg_tuner_data_303_296 0xF025 +#define reg_tuner_data_303_296_pos 0 +#define reg_tuner_data_303_296_len 8 +#define reg_tuner_data_303_296_lsb 296 +#define p_reg_tuner_data_311_304 0xF026 +#define reg_tuner_data_311_304_pos 0 +#define reg_tuner_data_311_304_len 8 +#define reg_tuner_data_311_304_lsb 304 +#define p_reg_tuner_data_319_312 0xF027 +#define reg_tuner_data_319_312_pos 0 +#define reg_tuner_data_319_312_len 8 +#define reg_tuner_data_319_312_lsb 312 +#define p_reg_tuner_data_327_320 0xF028 +#define reg_tuner_data_327_320_pos 0 +#define reg_tuner_data_327_320_len 8 +#define reg_tuner_data_327_320_lsb 320 +#define p_reg_tuner_data_335_328 0xF029 +#define reg_tuner_data_335_328_pos 0 +#define reg_tuner_data_335_328_len 8 +#define reg_tuner_data_335_328_lsb 328 +#define p_reg_tuner_data_343_336 0xF02A +#define reg_tuner_data_343_336_pos 0 +#define reg_tuner_data_343_336_len 8 +#define reg_tuner_data_343_336_lsb 336 +#define p_reg_tuner_data_351_344 0xF02B +#define reg_tuner_data_351_344_pos 0 +#define reg_tuner_data_351_344_len 8 +#define reg_tuner_data_351_344_lsb 344 +#define p_reg_tuner_data_359_352 0xF02C +#define reg_tuner_data_359_352_pos 0 +#define reg_tuner_data_359_352_len 8 +#define reg_tuner_data_359_352_lsb 352 +#define p_reg_tuner_data_367_360 0xF02D +#define reg_tuner_data_367_360_pos 0 +#define reg_tuner_data_367_360_len 8 +#define reg_tuner_data_367_360_lsb 360 +#define p_reg_tuner_data_375_368 0xF02E +#define reg_tuner_data_375_368_pos 0 +#define reg_tuner_data_375_368_len 8 +#define reg_tuner_data_375_368_lsb 368 +#define p_reg_tuner_data_383_376 0xF02F +#define reg_tuner_data_383_376_pos 0 +#define reg_tuner_data_383_376_len 8 +#define reg_tuner_data_383_376_lsb 376 +#define p_reg_tuner_data_391_384 0xF030 +#define reg_tuner_data_391_384_pos 0 +#define reg_tuner_data_391_384_len 8 +#define reg_tuner_data_391_384_lsb 384 +#define p_reg_tuner_data_399_392 0xF031 +#define reg_tuner_data_399_392_pos 0 +#define reg_tuner_data_399_392_len 8 +#define reg_tuner_data_399_392_lsb 392 +#define p_reg_tuner_data_407_400 0xF032 +#define reg_tuner_data_407_400_pos 0 +#define reg_tuner_data_407_400_len 8 +#define reg_tuner_data_407_400_lsb 400 +#define p_reg_tuner_data_415_408 0xF033 +#define reg_tuner_data_415_408_pos 0 +#define reg_tuner_data_415_408_len 8 +#define reg_tuner_data_415_408_lsb 408 +#define p_reg_tuner_data_423_416 0xF034 +#define reg_tuner_data_423_416_pos 0 +#define reg_tuner_data_423_416_len 8 +#define reg_tuner_data_423_416_lsb 416 +#define p_reg_tuner_data_431_424 0xF035 +#define reg_tuner_data_431_424_pos 0 +#define reg_tuner_data_431_424_len 8 +#define reg_tuner_data_431_424_lsb 424 +#define p_reg_tuner_data_439_432 0xF036 +#define reg_tuner_data_439_432_pos 0 +#define reg_tuner_data_439_432_len 8 +#define reg_tuner_data_439_432_lsb 432 +#define p_reg_tuner_data_447_440 0xF037 +#define reg_tuner_data_447_440_pos 0 +#define reg_tuner_data_447_440_len 8 +#define reg_tuner_data_447_440_lsb 440 +#define p_reg_tuner_data_455_448 0xF038 +#define reg_tuner_data_455_448_pos 0 +#define reg_tuner_data_455_448_len 8 +#define reg_tuner_data_455_448_lsb 448 +#define p_reg_tuner_data_463_456 0xF039 +#define reg_tuner_data_463_456_pos 0 +#define reg_tuner_data_463_456_len 8 +#define reg_tuner_data_463_456_lsb 456 +#define p_reg_tuner_data_471_464 0xF03A +#define reg_tuner_data_471_464_pos 0 +#define reg_tuner_data_471_464_len 8 +#define reg_tuner_data_471_464_lsb 464 +#define p_reg_tuner_data_479_472 0xF03B +#define reg_tuner_data_479_472_pos 0 +#define reg_tuner_data_479_472_len 8 +#define reg_tuner_data_479_472_lsb 472 +#define p_reg_tuner_data_487_480 0xF03C +#define reg_tuner_data_487_480_pos 0 +#define reg_tuner_data_487_480_len 8 +#define reg_tuner_data_487_480_lsb 480 +#define p_reg_tuner_data_495_488 0xF03D +#define reg_tuner_data_495_488_pos 0 +#define reg_tuner_data_495_488_len 8 +#define reg_tuner_data_495_488_lsb 488 +#define p_reg_tuner_data_503_496 0xF03E +#define reg_tuner_data_503_496_pos 0 +#define reg_tuner_data_503_496_len 8 +#define reg_tuner_data_503_496_lsb 496 +#define p_reg_tuner_data_511_504 0xF03F +#define reg_tuner_data_511_504_pos 0 +#define reg_tuner_data_511_504_len 8 +#define reg_tuner_data_511_504_lsb 504 +#define p_reg_tuner_data_519_512 0xF040 +#define reg_tuner_data_519_512_pos 0 +#define reg_tuner_data_519_512_len 8 +#define reg_tuner_data_519_512_lsb 512 +#define p_reg_tuner_data_527_520 0xF041 +#define reg_tuner_data_527_520_pos 0 +#define reg_tuner_data_527_520_len 8 +#define reg_tuner_data_527_520_lsb 520 +#define p_reg_tuner_data_535_528 0xF042 +#define reg_tuner_data_535_528_pos 0 +#define reg_tuner_data_535_528_len 8 +#define reg_tuner_data_535_528_lsb 528 +#define p_reg_tuner_data_543_536 0xF043 +#define reg_tuner_data_543_536_pos 0 +#define reg_tuner_data_543_536_len 8 +#define reg_tuner_data_543_536_lsb 536 +#define p_reg_tuner_data_551_544 0xF044 +#define reg_tuner_data_551_544_pos 0 +#define reg_tuner_data_551_544_len 8 +#define reg_tuner_data_551_544_lsb 544 +#define p_reg_tuner_data_559_552 0xF045 +#define reg_tuner_data_559_552_pos 0 +#define reg_tuner_data_559_552_len 8 +#define reg_tuner_data_559_552_lsb 552 +#define p_reg_tuner_data_567_560 0xF046 +#define reg_tuner_data_567_560_pos 0 +#define reg_tuner_data_567_560_len 8 +#define reg_tuner_data_567_560_lsb 560 +#define p_reg_tuner_data_575_568 0xF047 +#define reg_tuner_data_575_568_pos 0 +#define reg_tuner_data_575_568_len 8 +#define reg_tuner_data_575_568_lsb 568 +#define p_reg_tuner_data_583_576 0xF048 +#define reg_tuner_data_583_576_pos 0 +#define reg_tuner_data_583_576_len 8 +#define reg_tuner_data_583_576_lsb 576 +#define p_reg_tuner_data_591_584 0xF049 +#define reg_tuner_data_591_584_pos 0 +#define reg_tuner_data_591_584_len 8 +#define reg_tuner_data_591_584_lsb 584 +#define p_reg_tuner_data_599_592 0xF04A +#define reg_tuner_data_599_592_pos 0 +#define reg_tuner_data_599_592_len 8 +#define reg_tuner_data_599_592_lsb 592 +#define p_reg_tuner_data_607_600 0xF04B +#define reg_tuner_data_607_600_pos 0 +#define reg_tuner_data_607_600_len 8 +#define reg_tuner_data_607_600_lsb 600 +#define p_reg_tuner_data_615_608 0xF04C +#define reg_tuner_data_615_608_pos 0 +#define reg_tuner_data_615_608_len 8 +#define reg_tuner_data_615_608_lsb 608 +#define p_reg_tuner_data_623_616 0xF04D +#define reg_tuner_data_623_616_pos 0 +#define reg_tuner_data_623_616_len 8 +#define reg_tuner_data_623_616_lsb 616 +#define p_reg_tuner_data_631_624 0xF04E +#define reg_tuner_data_631_624_pos 0 +#define reg_tuner_data_631_624_len 8 +#define reg_tuner_data_631_624_lsb 624 +#define p_reg_tuner_data_639_632 0xF04F +#define reg_tuner_data_639_632_pos 0 +#define reg_tuner_data_639_632_len 8 +#define reg_tuner_data_639_632_lsb 632 +#define p_reg_tuner_data_647_640 0xF050 +#define reg_tuner_data_647_640_pos 0 +#define reg_tuner_data_647_640_len 8 +#define reg_tuner_data_647_640_lsb 640 +#define p_reg_tuner_data_655_648 0xF051 +#define reg_tuner_data_655_648_pos 0 +#define reg_tuner_data_655_648_len 8 +#define reg_tuner_data_655_648_lsb 648 +#define p_reg_tuner_data_663_656 0xF052 +#define reg_tuner_data_663_656_pos 0 +#define reg_tuner_data_663_656_len 8 +#define reg_tuner_data_663_656_lsb 656 +#define p_reg_tuner_data_671_664 0xF053 +#define reg_tuner_data_671_664_pos 0 +#define reg_tuner_data_671_664_len 8 +#define reg_tuner_data_671_664_lsb 664 +#define p_reg_tuner_data_679_672 0xF054 +#define reg_tuner_data_679_672_pos 0 +#define reg_tuner_data_679_672_len 8 +#define reg_tuner_data_679_672_lsb 672 +#define p_reg_tuner_data_687_680 0xF055 +#define reg_tuner_data_687_680_pos 0 +#define reg_tuner_data_687_680_len 8 +#define reg_tuner_data_687_680_lsb 680 +#define p_reg_tuner_data_695_688 0xF056 +#define reg_tuner_data_695_688_pos 0 +#define reg_tuner_data_695_688_len 8 +#define reg_tuner_data_695_688_lsb 688 +#define p_reg_tuner_data_703_696 0xF057 +#define reg_tuner_data_703_696_pos 0 +#define reg_tuner_data_703_696_len 8 +#define reg_tuner_data_703_696_lsb 696 +#define p_reg_tuner_data_711_704 0xF058 +#define reg_tuner_data_711_704_pos 0 +#define reg_tuner_data_711_704_len 8 +#define reg_tuner_data_711_704_lsb 704 +#define p_reg_tuner_data_719_712 0xF059 +#define reg_tuner_data_719_712_pos 0 +#define reg_tuner_data_719_712_len 8 +#define reg_tuner_data_719_712_lsb 712 +#define p_reg_tuner_data_727_720 0xF05A +#define reg_tuner_data_727_720_pos 0 +#define reg_tuner_data_727_720_len 8 +#define reg_tuner_data_727_720_lsb 720 +#define p_reg_tuner_data_735_728 0xF05B +#define reg_tuner_data_735_728_pos 0 +#define reg_tuner_data_735_728_len 8 +#define reg_tuner_data_735_728_lsb 728 +#define p_reg_tuner_data_743_736 0xF05C +#define reg_tuner_data_743_736_pos 0 +#define reg_tuner_data_743_736_len 8 +#define reg_tuner_data_743_736_lsb 736 +#define p_reg_tuner_data_751_744 0xF05D +#define reg_tuner_data_751_744_pos 0 +#define reg_tuner_data_751_744_len 8 +#define reg_tuner_data_751_744_lsb 744 +#define p_reg_tuner_data_759_752 0xF05E +#define reg_tuner_data_759_752_pos 0 +#define reg_tuner_data_759_752_len 8 +#define reg_tuner_data_759_752_lsb 752 +#define p_reg_tuner_data_767_760 0xF05F +#define reg_tuner_data_767_760_pos 0 +#define reg_tuner_data_767_760_len 8 +#define reg_tuner_data_767_760_lsb 760 +#define p_reg_tuner_data_775_768 0xF060 +#define reg_tuner_data_775_768_pos 0 +#define reg_tuner_data_775_768_len 8 +#define reg_tuner_data_775_768_lsb 768 +#define p_reg_tuner_data_783_776 0xF061 +#define reg_tuner_data_783_776_pos 0 +#define reg_tuner_data_783_776_len 8 +#define reg_tuner_data_783_776_lsb 776 +#define p_reg_tuner_data_791_784 0xF062 +#define reg_tuner_data_791_784_pos 0 +#define reg_tuner_data_791_784_len 8 +#define reg_tuner_data_791_784_lsb 784 +#define p_reg_tuner_data_799_792 0xF063 +#define reg_tuner_data_799_792_pos 0 +#define reg_tuner_data_799_792_len 8 +#define reg_tuner_data_799_792_lsb 792 +#define p_reg_tuner_data_807_800 0xF064 +#define reg_tuner_data_807_800_pos 0 +#define reg_tuner_data_807_800_len 8 +#define reg_tuner_data_807_800_lsb 800 +#define p_reg_tuner_data_815_808 0xF065 +#define reg_tuner_data_815_808_pos 0 +#define reg_tuner_data_815_808_len 8 +#define reg_tuner_data_815_808_lsb 808 +#define p_reg_tuner_data_823_816 0xF066 +#define reg_tuner_data_823_816_pos 0 +#define reg_tuner_data_823_816_len 8 +#define reg_tuner_data_823_816_lsb 816 +#define p_reg_tuner_data_831_824 0xF067 +#define reg_tuner_data_831_824_pos 0 +#define reg_tuner_data_831_824_len 8 +#define reg_tuner_data_831_824_lsb 824 +#define p_reg_tuner_data_839_832 0xF068 +#define reg_tuner_data_839_832_pos 0 +#define reg_tuner_data_839_832_len 8 +#define reg_tuner_data_839_832_lsb 832 +#define p_reg_tuner_data_847_840 0xF069 +#define reg_tuner_data_847_840_pos 0 +#define reg_tuner_data_847_840_len 8 +#define reg_tuner_data_847_840_lsb 840 +#define p_reg_tuner_data_855_848 0xF06A +#define reg_tuner_data_855_848_pos 0 +#define reg_tuner_data_855_848_len 8 +#define reg_tuner_data_855_848_lsb 848 +#define p_reg_tuner_data_863_856 0xF06B +#define reg_tuner_data_863_856_pos 0 +#define reg_tuner_data_863_856_len 8 +#define reg_tuner_data_863_856_lsb 856 +#define p_reg_tuner_data_871_864 0xF06C +#define reg_tuner_data_871_864_pos 0 +#define reg_tuner_data_871_864_len 8 +#define reg_tuner_data_871_864_lsb 864 +#define p_reg_tuner_data_879_872 0xF06D +#define reg_tuner_data_879_872_pos 0 +#define reg_tuner_data_879_872_len 8 +#define reg_tuner_data_879_872_lsb 872 +#define p_reg_tuner_data_887_880 0xF06E +#define reg_tuner_data_887_880_pos 0 +#define reg_tuner_data_887_880_len 8 +#define reg_tuner_data_887_880_lsb 880 +#define p_reg_tuner_data_895_888 0xF06F +#define reg_tuner_data_895_888_pos 0 +#define reg_tuner_data_895_888_len 8 +#define reg_tuner_data_895_888_lsb 888 +#define p_reg_tuner_data_903_896 0xF070 +#define reg_tuner_data_903_896_pos 0 +#define reg_tuner_data_903_896_len 8 +#define reg_tuner_data_903_896_lsb 896 +#define p_reg_tuner_data_911_904 0xF071 +#define reg_tuner_data_911_904_pos 0 +#define reg_tuner_data_911_904_len 8 +#define reg_tuner_data_911_904_lsb 904 +#define p_reg_tuner_data_919_912 0xF072 +#define reg_tuner_data_919_912_pos 0 +#define reg_tuner_data_919_912_len 8 +#define reg_tuner_data_919_912_lsb 912 +#define p_reg_tuner_data_927_920 0xF073 +#define reg_tuner_data_927_920_pos 0 +#define reg_tuner_data_927_920_len 8 +#define reg_tuner_data_927_920_lsb 920 +#define p_reg_tuner_data_935_928 0xF074 +#define reg_tuner_data_935_928_pos 0 +#define reg_tuner_data_935_928_len 8 +#define reg_tuner_data_935_928_lsb 928 +#define p_reg_tuner_data_943_936 0xF075 +#define reg_tuner_data_943_936_pos 0 +#define reg_tuner_data_943_936_len 8 +#define reg_tuner_data_943_936_lsb 936 +#define p_reg_tuner_data_951_944 0xF076 +#define reg_tuner_data_951_944_pos 0 +#define reg_tuner_data_951_944_len 8 +#define reg_tuner_data_951_944_lsb 944 +#define p_reg_tuner_data_959_952 0xF077 +#define reg_tuner_data_959_952_pos 0 +#define reg_tuner_data_959_952_len 8 +#define reg_tuner_data_959_952_lsb 952 +#define p_reg_tuner_data_967_960 0xF078 +#define reg_tuner_data_967_960_pos 0 +#define reg_tuner_data_967_960_len 8 +#define reg_tuner_data_967_960_lsb 960 +#define p_reg_tuner_data_975_968 0xF079 +#define reg_tuner_data_975_968_pos 0 +#define reg_tuner_data_975_968_len 8 +#define reg_tuner_data_975_968_lsb 968 +#define p_reg_tuner_data_983_976 0xF07A +#define reg_tuner_data_983_976_pos 0 +#define reg_tuner_data_983_976_len 8 +#define reg_tuner_data_983_976_lsb 976 +#define p_reg_tuner_data_991_984 0xF07B +#define reg_tuner_data_991_984_pos 0 +#define reg_tuner_data_991_984_len 8 +#define reg_tuner_data_991_984_lsb 984 +#define p_reg_tuner_data_999_992 0xF07C +#define reg_tuner_data_999_992_pos 0 +#define reg_tuner_data_999_992_len 8 +#define reg_tuner_data_999_992_lsb 992 +#define p_reg_tuner_data_1007_1000 0xF07D +#define reg_tuner_data_1007_1000_pos 0 +#define reg_tuner_data_1007_1000_len 8 +#define reg_tuner_data_1007_1000_lsb 1000 +#define p_reg_tuner_data_1015_1008 0xF07E +#define reg_tuner_data_1015_1008_pos 0 +#define reg_tuner_data_1015_1008_len 8 +#define reg_tuner_data_1015_1008_lsb 1008 +#define p_reg_tuner_data_1023_1016 0xF07F +#define reg_tuner_data_1023_1016_pos 0 +#define reg_tuner_data_1023_1016_len 8 +#define reg_tuner_data_1023_1016_lsb 1016 +#define p_reg_tuner_data_1031_1024 0xF080 +#define reg_tuner_data_1031_1024_pos 0 +#define reg_tuner_data_1031_1024_len 8 +#define reg_tuner_data_1031_1024_lsb 1024 +#define p_reg_tuner_data_1039_1032 0xF081 +#define reg_tuner_data_1039_1032_pos 0 +#define reg_tuner_data_1039_1032_len 8 +#define reg_tuner_data_1039_1032_lsb 1032 +#define p_reg_tuner_data_1047_1040 0xF082 +#define reg_tuner_data_1047_1040_pos 0 +#define reg_tuner_data_1047_1040_len 8 +#define reg_tuner_data_1047_1040_lsb 1040 +#define p_reg_tuner_data_1055_1048 0xF083 +#define reg_tuner_data_1055_1048_pos 0 +#define reg_tuner_data_1055_1048_len 8 +#define reg_tuner_data_1055_1048_lsb 1048 +#define p_reg_tuner_data_1063_1056 0xF084 +#define reg_tuner_data_1063_1056_pos 0 +#define reg_tuner_data_1063_1056_len 8 +#define reg_tuner_data_1063_1056_lsb 1056 +#define p_reg_tuner_data_1071_1064 0xF085 +#define reg_tuner_data_1071_1064_pos 0 +#define reg_tuner_data_1071_1064_len 8 +#define reg_tuner_data_1071_1064_lsb 1064 +#define p_reg_tuner_data_1079_1072 0xF086 +#define reg_tuner_data_1079_1072_pos 0 +#define reg_tuner_data_1079_1072_len 8 +#define reg_tuner_data_1079_1072_lsb 1072 +#define p_reg_tuner_data_1087_1080 0xF087 +#define reg_tuner_data_1087_1080_pos 0 +#define reg_tuner_data_1087_1080_len 8 +#define reg_tuner_data_1087_1080_lsb 1080 +#define p_reg_tuner_data_1095_1088 0xF088 +#define reg_tuner_data_1095_1088_pos 0 +#define reg_tuner_data_1095_1088_len 8 +#define reg_tuner_data_1095_1088_lsb 1088 +#define p_reg_tuner_data_1103_1096 0xF089 +#define reg_tuner_data_1103_1096_pos 0 +#define reg_tuner_data_1103_1096_len 8 +#define reg_tuner_data_1103_1096_lsb 1096 +#define p_reg_tuner_data_1111_1104 0xF08A +#define reg_tuner_data_1111_1104_pos 0 +#define reg_tuner_data_1111_1104_len 8 +#define reg_tuner_data_1111_1104_lsb 1104 +#define p_reg_tuner_data_1119_1112 0xF08B +#define reg_tuner_data_1119_1112_pos 0 +#define reg_tuner_data_1119_1112_len 8 +#define reg_tuner_data_1119_1112_lsb 1112 +#define p_reg_tuner_data_1127_1120 0xF08C +#define reg_tuner_data_1127_1120_pos 0 +#define reg_tuner_data_1127_1120_len 8 +#define reg_tuner_data_1127_1120_lsb 1120 +#define p_reg_tuner_data_1135_1128 0xF08D +#define reg_tuner_data_1135_1128_pos 0 +#define reg_tuner_data_1135_1128_len 8 +#define reg_tuner_data_1135_1128_lsb 1128 +#define p_reg_tuner_data_1143_1136 0xF08E +#define reg_tuner_data_1143_1136_pos 0 +#define reg_tuner_data_1143_1136_len 8 +#define reg_tuner_data_1143_1136_lsb 1136 +#define p_reg_tuner_data_1151_1144 0xF08F +#define reg_tuner_data_1151_1144_pos 0 +#define reg_tuner_data_1151_1144_len 8 +#define reg_tuner_data_1151_1144_lsb 1144 +#define p_reg_tuner_data_1159_1152 0xF090 +#define reg_tuner_data_1159_1152_pos 0 +#define reg_tuner_data_1159_1152_len 8 +#define reg_tuner_data_1159_1152_lsb 1152 +#define p_reg_tuner_data_1167_1160 0xF091 +#define reg_tuner_data_1167_1160_pos 0 +#define reg_tuner_data_1167_1160_len 8 +#define reg_tuner_data_1167_1160_lsb 1160 +#define p_reg_tuner_data_1175_1168 0xF092 +#define reg_tuner_data_1175_1168_pos 0 +#define reg_tuner_data_1175_1168_len 8 +#define reg_tuner_data_1175_1168_lsb 1168 +#define p_reg_tuner_data_1183_1176 0xF093 +#define reg_tuner_data_1183_1176_pos 0 +#define reg_tuner_data_1183_1176_len 8 +#define reg_tuner_data_1183_1176_lsb 1176 +#define p_reg_tuner_data_1191_1184 0xF094 +#define reg_tuner_data_1191_1184_pos 0 +#define reg_tuner_data_1191_1184_len 8 +#define reg_tuner_data_1191_1184_lsb 1184 +#define p_reg_tuner_data_1199_1192 0xF095 +#define reg_tuner_data_1199_1192_pos 0 +#define reg_tuner_data_1199_1192_len 8 +#define reg_tuner_data_1199_1192_lsb 1192 +#define p_reg_tuner_data_1207_1200 0xF096 +#define reg_tuner_data_1207_1200_pos 0 +#define reg_tuner_data_1207_1200_len 8 +#define reg_tuner_data_1207_1200_lsb 1200 +#define p_reg_tuner_data_1215_1208 0xF097 +#define reg_tuner_data_1215_1208_pos 0 +#define reg_tuner_data_1215_1208_len 8 +#define reg_tuner_data_1215_1208_lsb 1208 +#define p_reg_tuner_data_1223_1216 0xF098 +#define reg_tuner_data_1223_1216_pos 0 +#define reg_tuner_data_1223_1216_len 8 +#define reg_tuner_data_1223_1216_lsb 1216 +#define p_reg_tuner_data_1231_1224 0xF099 +#define reg_tuner_data_1231_1224_pos 0 +#define reg_tuner_data_1231_1224_len 8 +#define reg_tuner_data_1231_1224_lsb 1224 +#define p_reg_tuner_data_1239_1232 0xF09A +#define reg_tuner_data_1239_1232_pos 0 +#define reg_tuner_data_1239_1232_len 8 +#define reg_tuner_data_1239_1232_lsb 1232 +#define p_reg_tuner_data_1247_1240 0xF09B +#define reg_tuner_data_1247_1240_pos 0 +#define reg_tuner_data_1247_1240_len 8 +#define reg_tuner_data_1247_1240_lsb 1240 +#define p_reg_tuner_data_1255_1248 0xF09C +#define reg_tuner_data_1255_1248_pos 0 +#define reg_tuner_data_1255_1248_len 8 +#define reg_tuner_data_1255_1248_lsb 1248 +#define p_reg_tuner_data_1263_1256 0xF09D +#define reg_tuner_data_1263_1256_pos 0 +#define reg_tuner_data_1263_1256_len 8 +#define reg_tuner_data_1263_1256_lsb 1256 +#define p_reg_tuner_data_1271_1264 0xF09E +#define reg_tuner_data_1271_1264_pos 0 +#define reg_tuner_data_1271_1264_len 8 +#define reg_tuner_data_1271_1264_lsb 1264 +#define p_reg_tuner_data_1279_1272 0xF09F +#define reg_tuner_data_1279_1272_pos 0 +#define reg_tuner_data_1279_1272_len 8 +#define reg_tuner_data_1279_1272_lsb 1272 +#define p_reg_tuner_data_1287_1280 0xF0A0 +#define reg_tuner_data_1287_1280_pos 0 +#define reg_tuner_data_1287_1280_len 8 +#define reg_tuner_data_1287_1280_lsb 1280 +#define p_reg_tuner_data_1295_1288 0xF0A1 +#define reg_tuner_data_1295_1288_pos 0 +#define reg_tuner_data_1295_1288_len 8 +#define reg_tuner_data_1295_1288_lsb 1288 +#define p_reg_tuner_data_1303_1296 0xF0A2 +#define reg_tuner_data_1303_1296_pos 0 +#define reg_tuner_data_1303_1296_len 8 +#define reg_tuner_data_1303_1296_lsb 1296 +#define p_reg_tuner_data_1311_1304 0xF0A3 +#define reg_tuner_data_1311_1304_pos 0 +#define reg_tuner_data_1311_1304_len 8 +#define reg_tuner_data_1311_1304_lsb 1304 +#define p_reg_tuner_data_1319_1312 0xF0A4 +#define reg_tuner_data_1319_1312_pos 0 +#define reg_tuner_data_1319_1312_len 8 +#define reg_tuner_data_1319_1312_lsb 1312 +#define p_reg_tuner_data_1327_1320 0xF0A5 +#define reg_tuner_data_1327_1320_pos 0 +#define reg_tuner_data_1327_1320_len 8 +#define reg_tuner_data_1327_1320_lsb 1320 +#define p_reg_tuner_data_1335_1328 0xF0A6 +#define reg_tuner_data_1335_1328_pos 0 +#define reg_tuner_data_1335_1328_len 8 +#define reg_tuner_data_1335_1328_lsb 1328 +#define p_reg_tuner_data_1343_1336 0xF0A7 +#define reg_tuner_data_1343_1336_pos 0 +#define reg_tuner_data_1343_1336_len 8 +#define reg_tuner_data_1343_1336_lsb 1336 +#define p_reg_tuner_data_1351_1344 0xF0A8 +#define reg_tuner_data_1351_1344_pos 0 +#define reg_tuner_data_1351_1344_len 8 +#define reg_tuner_data_1351_1344_lsb 1344 +#define p_reg_tuner_data_1359_1352 0xF0A9 +#define reg_tuner_data_1359_1352_pos 0 +#define reg_tuner_data_1359_1352_len 8 +#define reg_tuner_data_1359_1352_lsb 1352 +#define p_reg_tuner_data_1367_1360 0xF0AA +#define reg_tuner_data_1367_1360_pos 0 +#define reg_tuner_data_1367_1360_len 8 +#define reg_tuner_data_1367_1360_lsb 1360 +#define p_reg_tuner_data_1375_1368 0xF0AB +#define reg_tuner_data_1375_1368_pos 0 +#define reg_tuner_data_1375_1368_len 8 +#define reg_tuner_data_1375_1368_lsb 1368 +#define p_reg_tuner_data_1383_1376 0xF0AC +#define reg_tuner_data_1383_1376_pos 0 +#define reg_tuner_data_1383_1376_len 8 +#define reg_tuner_data_1383_1376_lsb 1376 +#define p_reg_tuner_data_1391_1384 0xF0AD +#define reg_tuner_data_1391_1384_pos 0 +#define reg_tuner_data_1391_1384_len 8 +#define reg_tuner_data_1391_1384_lsb 1384 +#define p_reg_tuner_data_1399_1392 0xF0AE +#define reg_tuner_data_1399_1392_pos 0 +#define reg_tuner_data_1399_1392_len 8 +#define reg_tuner_data_1399_1392_lsb 1392 +#define p_reg_tuner_data_1407_1400 0xF0AF +#define reg_tuner_data_1407_1400_pos 0 +#define reg_tuner_data_1407_1400_len 8 +#define reg_tuner_data_1407_1400_lsb 1400 +#define p_reg_tuner_data_1415_1408 0xF0B0 +#define reg_tuner_data_1415_1408_pos 0 +#define reg_tuner_data_1415_1408_len 8 +#define reg_tuner_data_1415_1408_lsb 1408 +#define p_reg_tuner_data_1423_1416 0xF0B1 +#define reg_tuner_data_1423_1416_pos 0 +#define reg_tuner_data_1423_1416_len 8 +#define reg_tuner_data_1423_1416_lsb 1416 +#define p_reg_tuner_data_1431_1424 0xF0B2 +#define reg_tuner_data_1431_1424_pos 0 +#define reg_tuner_data_1431_1424_len 8 +#define reg_tuner_data_1431_1424_lsb 1424 +#define p_reg_tuner_data_1439_1432 0xF0B3 +#define reg_tuner_data_1439_1432_pos 0 +#define reg_tuner_data_1439_1432_len 8 +#define reg_tuner_data_1439_1432_lsb 1432 +#define p_reg_tuner_data_1447_1440 0xF0B4 +#define reg_tuner_data_1447_1440_pos 0 +#define reg_tuner_data_1447_1440_len 8 +#define reg_tuner_data_1447_1440_lsb 1440 +#define p_reg_tuner_data_1455_1448 0xF0B5 +#define reg_tuner_data_1455_1448_pos 0 +#define reg_tuner_data_1455_1448_len 8 +#define reg_tuner_data_1455_1448_lsb 1448 +#define p_reg_tuner_data_1463_1456 0xF0B6 +#define reg_tuner_data_1463_1456_pos 0 +#define reg_tuner_data_1463_1456_len 8 +#define reg_tuner_data_1463_1456_lsb 1456 +#define p_reg_tuner_data_1471_1464 0xF0B7 +#define reg_tuner_data_1471_1464_pos 0 +#define reg_tuner_data_1471_1464_len 8 +#define reg_tuner_data_1471_1464_lsb 1464 +#define p_reg_tuner_data_1479_1472 0xF0B8 +#define reg_tuner_data_1479_1472_pos 0 +#define reg_tuner_data_1479_1472_len 8 +#define reg_tuner_data_1479_1472_lsb 1472 +#define p_reg_tuner_data_1487_1480 0xF0B9 +#define reg_tuner_data_1487_1480_pos 0 +#define reg_tuner_data_1487_1480_len 8 +#define reg_tuner_data_1487_1480_lsb 1480 +#define p_reg_tuner_data_1495_1488 0xF0BA +#define reg_tuner_data_1495_1488_pos 0 +#define reg_tuner_data_1495_1488_len 8 +#define reg_tuner_data_1495_1488_lsb 1488 +#define p_reg_tuner_data_1503_1496 0xF0BB +#define reg_tuner_data_1503_1496_pos 0 +#define reg_tuner_data_1503_1496_len 8 +#define reg_tuner_data_1503_1496_lsb 1496 +#define p_reg_tuner_data_1511_1504 0xF0BC +#define reg_tuner_data_1511_1504_pos 0 +#define reg_tuner_data_1511_1504_len 8 +#define reg_tuner_data_1511_1504_lsb 1504 +#define p_reg_tuner_data_1519_1512 0xF0BD +#define reg_tuner_data_1519_1512_pos 0 +#define reg_tuner_data_1519_1512_len 8 +#define reg_tuner_data_1519_1512_lsb 1512 +#define p_reg_tuner_data_1527_1520 0xF0BE +#define reg_tuner_data_1527_1520_pos 0 +#define reg_tuner_data_1527_1520_len 8 +#define reg_tuner_data_1527_1520_lsb 1520 +#define p_reg_tuner_data_1535_1528 0xF0BF +#define reg_tuner_data_1535_1528_pos 0 +#define reg_tuner_data_1535_1528_len 8 +#define reg_tuner_data_1535_1528_lsb 1528 +#define p_reg_tuner_data_1543_1536 0xF0C0 +#define reg_tuner_data_1543_1536_pos 0 +#define reg_tuner_data_1543_1536_len 8 +#define reg_tuner_data_1543_1536_lsb 1536 +#define p_reg_tuner_data_1551_1544 0xF0C1 +#define reg_tuner_data_1551_1544_pos 0 +#define reg_tuner_data_1551_1544_len 8 +#define reg_tuner_data_1551_1544_lsb 1544 +#define p_reg_tuner_data_1559_1552 0xF0C2 +#define reg_tuner_data_1559_1552_pos 0 +#define reg_tuner_data_1559_1552_len 8 +#define reg_tuner_data_1559_1552_lsb 1552 +#define p_reg_tuner_data_1567_1560 0xF0C3 +#define reg_tuner_data_1567_1560_pos 0 +#define reg_tuner_data_1567_1560_len 8 +#define reg_tuner_data_1567_1560_lsb 1560 +#define p_reg_tuner_data_1575_1568 0xF0C4 +#define reg_tuner_data_1575_1568_pos 0 +#define reg_tuner_data_1575_1568_len 8 +#define reg_tuner_data_1575_1568_lsb 1568 +#define p_reg_tuner_data_1583_1576 0xF0C5 +#define reg_tuner_data_1583_1576_pos 0 +#define reg_tuner_data_1583_1576_len 8 +#define reg_tuner_data_1583_1576_lsb 1576 +#define p_reg_tuner_data_1591_1584 0xF0C6 +#define reg_tuner_data_1591_1584_pos 0 +#define reg_tuner_data_1591_1584_len 8 +#define reg_tuner_data_1591_1584_lsb 1584 +#define p_reg_tuner_data_1599_1592 0xF0C7 +#define reg_tuner_data_1599_1592_pos 0 +#define reg_tuner_data_1599_1592_len 8 +#define reg_tuner_data_1599_1592_lsb 1592 +#define p_reg_tuner_data_1607_1600 0xF0C8 +#define reg_tuner_data_1607_1600_pos 0 +#define reg_tuner_data_1607_1600_len 8 +#define reg_tuner_data_1607_1600_lsb 1600 +#define p_reg_tuner_data_1615_1608 0xF0C9 +#define reg_tuner_data_1615_1608_pos 0 +#define reg_tuner_data_1615_1608_len 8 +#define reg_tuner_data_1615_1608_lsb 1608 +#define p_reg_tuner_data_1623_1616 0xF0CA +#define reg_tuner_data_1623_1616_pos 0 +#define reg_tuner_data_1623_1616_len 8 +#define reg_tuner_data_1623_1616_lsb 1616 +#define p_reg_tuner_data_1631_1624 0xF0CB +#define reg_tuner_data_1631_1624_pos 0 +#define reg_tuner_data_1631_1624_len 8 +#define reg_tuner_data_1631_1624_lsb 1624 +#define p_reg_tuner_data_1639_1632 0xF0CC +#define reg_tuner_data_1639_1632_pos 0 +#define reg_tuner_data_1639_1632_len 8 +#define reg_tuner_data_1639_1632_lsb 1632 +#define p_reg_tuner_data_1647_1640 0xF0CD +#define reg_tuner_data_1647_1640_pos 0 +#define reg_tuner_data_1647_1640_len 8 +#define reg_tuner_data_1647_1640_lsb 1640 +#define p_reg_tuner_data_1655_1648 0xF0CE +#define reg_tuner_data_1655_1648_pos 0 +#define reg_tuner_data_1655_1648_len 8 +#define reg_tuner_data_1655_1648_lsb 1648 +#define p_reg_tuner_data_1663_1656 0xF0CF +#define reg_tuner_data_1663_1656_pos 0 +#define reg_tuner_data_1663_1656_len 8 +#define reg_tuner_data_1663_1656_lsb 1656 +#define p_reg_tuner_data_1671_1664 0xF0D0 +#define reg_tuner_data_1671_1664_pos 0 +#define reg_tuner_data_1671_1664_len 8 +#define reg_tuner_data_1671_1664_lsb 1664 +#define p_reg_tuner_data_1679_1672 0xF0D1 +#define reg_tuner_data_1679_1672_pos 0 +#define reg_tuner_data_1679_1672_len 8 +#define reg_tuner_data_1679_1672_lsb 1672 +#define p_reg_tuner_data_1687_1680 0xF0D2 +#define reg_tuner_data_1687_1680_pos 0 +#define reg_tuner_data_1687_1680_len 8 +#define reg_tuner_data_1687_1680_lsb 1680 +#define p_reg_tuner_data_1695_1688 0xF0D3 +#define reg_tuner_data_1695_1688_pos 0 +#define reg_tuner_data_1695_1688_len 8 +#define reg_tuner_data_1695_1688_lsb 1688 +#define p_reg_tuner_data_1703_1696 0xF0D4 +#define reg_tuner_data_1703_1696_pos 0 +#define reg_tuner_data_1703_1696_len 8 +#define reg_tuner_data_1703_1696_lsb 1696 +#define p_reg_tuner_data_1711_1704 0xF0D5 +#define reg_tuner_data_1711_1704_pos 0 +#define reg_tuner_data_1711_1704_len 8 +#define reg_tuner_data_1711_1704_lsb 1704 +#define p_reg_tuner_data_1719_1712 0xF0D6 +#define reg_tuner_data_1719_1712_pos 0 +#define reg_tuner_data_1719_1712_len 8 +#define reg_tuner_data_1719_1712_lsb 1712 +#define p_reg_tuner_data_1727_1720 0xF0D7 +#define reg_tuner_data_1727_1720_pos 0 +#define reg_tuner_data_1727_1720_len 8 +#define reg_tuner_data_1727_1720_lsb 1720 +#define p_reg_tuner_data_1735_1728 0xF0D8 +#define reg_tuner_data_1735_1728_pos 0 +#define reg_tuner_data_1735_1728_len 8 +#define reg_tuner_data_1735_1728_lsb 1728 +#define p_reg_tuner_data_1743_1736 0xF0D9 +#define reg_tuner_data_1743_1736_pos 0 +#define reg_tuner_data_1743_1736_len 8 +#define reg_tuner_data_1743_1736_lsb 1736 +#define p_reg_tuner_data_1751_1744 0xF0DA +#define reg_tuner_data_1751_1744_pos 0 +#define reg_tuner_data_1751_1744_len 8 +#define reg_tuner_data_1751_1744_lsb 1744 +#define p_reg_tuner_data_1759_1752 0xF0DB +#define reg_tuner_data_1759_1752_pos 0 +#define reg_tuner_data_1759_1752_len 8 +#define reg_tuner_data_1759_1752_lsb 1752 +#define p_reg_tuner_data_1767_1760 0xF0DC +#define reg_tuner_data_1767_1760_pos 0 +#define reg_tuner_data_1767_1760_len 8 +#define reg_tuner_data_1767_1760_lsb 1760 +#define p_reg_tuner_data_1775_1768 0xF0DD +#define reg_tuner_data_1775_1768_pos 0 +#define reg_tuner_data_1775_1768_len 8 +#define reg_tuner_data_1775_1768_lsb 1768 +#define p_reg_tuner_data_1783_1776 0xF0DE +#define reg_tuner_data_1783_1776_pos 0 +#define reg_tuner_data_1783_1776_len 8 +#define reg_tuner_data_1783_1776_lsb 1776 +#define p_reg_tuner_data_1791_1784 0xF0DF +#define reg_tuner_data_1791_1784_pos 0 +#define reg_tuner_data_1791_1784_len 8 +#define reg_tuner_data_1791_1784_lsb 1784 +#define p_reg_tuner_data_1799_1792 0xF0E0 +#define reg_tuner_data_1799_1792_pos 0 +#define reg_tuner_data_1799_1792_len 8 +#define reg_tuner_data_1799_1792_lsb 1792 +#define p_reg_tuner_data_1807_1800 0xF0E1 +#define reg_tuner_data_1807_1800_pos 0 +#define reg_tuner_data_1807_1800_len 8 +#define reg_tuner_data_1807_1800_lsb 1800 +#define p_reg_tuner_data_1815_1808 0xF0E2 +#define reg_tuner_data_1815_1808_pos 0 +#define reg_tuner_data_1815_1808_len 8 +#define reg_tuner_data_1815_1808_lsb 1808 +#define p_reg_tuner_data_1823_1816 0xF0E3 +#define reg_tuner_data_1823_1816_pos 0 +#define reg_tuner_data_1823_1816_len 8 +#define reg_tuner_data_1823_1816_lsb 1816 +#define p_reg_tuner_data_1831_1824 0xF0E4 +#define reg_tuner_data_1831_1824_pos 0 +#define reg_tuner_data_1831_1824_len 8 +#define reg_tuner_data_1831_1824_lsb 1824 +#define p_reg_tuner_data_1839_1832 0xF0E5 +#define reg_tuner_data_1839_1832_pos 0 +#define reg_tuner_data_1839_1832_len 8 +#define reg_tuner_data_1839_1832_lsb 1832 +#define p_reg_tuner_data_1847_1840 0xF0E6 +#define reg_tuner_data_1847_1840_pos 0 +#define reg_tuner_data_1847_1840_len 8 +#define reg_tuner_data_1847_1840_lsb 1840 +#define p_reg_tuner_data_1855_1848 0xF0E7 +#define reg_tuner_data_1855_1848_pos 0 +#define reg_tuner_data_1855_1848_len 8 +#define reg_tuner_data_1855_1848_lsb 1848 +#define p_reg_tuner_data_1863_1856 0xF0E8 +#define reg_tuner_data_1863_1856_pos 0 +#define reg_tuner_data_1863_1856_len 8 +#define reg_tuner_data_1863_1856_lsb 1856 +#define p_reg_tuner_data_1871_1864 0xF0E9 +#define reg_tuner_data_1871_1864_pos 0 +#define reg_tuner_data_1871_1864_len 8 +#define reg_tuner_data_1871_1864_lsb 1864 +#define p_reg_tuner_data_1879_1872 0xF0EA +#define reg_tuner_data_1879_1872_pos 0 +#define reg_tuner_data_1879_1872_len 8 +#define reg_tuner_data_1879_1872_lsb 1872 +#define p_reg_tuner_data_1887_1880 0xF0EB +#define reg_tuner_data_1887_1880_pos 0 +#define reg_tuner_data_1887_1880_len 8 +#define reg_tuner_data_1887_1880_lsb 1880 +#define p_reg_tuner_data_1895_1888 0xF0EC +#define reg_tuner_data_1895_1888_pos 0 +#define reg_tuner_data_1895_1888_len 8 +#define reg_tuner_data_1895_1888_lsb 1888 +#define p_reg_tuner_data_1903_1896 0xF0ED +#define reg_tuner_data_1903_1896_pos 0 +#define reg_tuner_data_1903_1896_len 8 +#define reg_tuner_data_1903_1896_lsb 1896 +#define p_reg_tuner_data_1911_1904 0xF0EE +#define reg_tuner_data_1911_1904_pos 0 +#define reg_tuner_data_1911_1904_len 8 +#define reg_tuner_data_1911_1904_lsb 1904 +#define p_reg_tuner_data_1919_1912 0xF0EF +#define reg_tuner_data_1919_1912_pos 0 +#define reg_tuner_data_1919_1912_len 8 +#define reg_tuner_data_1919_1912_lsb 1912 +#define p_reg_tuner_data_1927_1920 0xF0F0 +#define reg_tuner_data_1927_1920_pos 0 +#define reg_tuner_data_1927_1920_len 8 +#define reg_tuner_data_1927_1920_lsb 1920 +#define p_reg_tuner_data_1935_1928 0xF0F1 +#define reg_tuner_data_1935_1928_pos 0 +#define reg_tuner_data_1935_1928_len 8 +#define reg_tuner_data_1935_1928_lsb 1928 +#define p_reg_tuner_data_1943_1936 0xF0F2 +#define reg_tuner_data_1943_1936_pos 0 +#define reg_tuner_data_1943_1936_len 8 +#define reg_tuner_data_1943_1936_lsb 1936 +#define p_reg_tuner_data_1951_1944 0xF0F3 +#define reg_tuner_data_1951_1944_pos 0 +#define reg_tuner_data_1951_1944_len 8 +#define reg_tuner_data_1951_1944_lsb 1944 +#define p_reg_tuner_data_1959_1952 0xF0F4 +#define reg_tuner_data_1959_1952_pos 0 +#define reg_tuner_data_1959_1952_len 8 +#define reg_tuner_data_1959_1952_lsb 1952 +#define p_reg_tuner_data_1967_1960 0xF0F5 +#define reg_tuner_data_1967_1960_pos 0 +#define reg_tuner_data_1967_1960_len 8 +#define reg_tuner_data_1967_1960_lsb 1960 +#define p_reg_tuner_data_1975_1968 0xF0F6 +#define reg_tuner_data_1975_1968_pos 0 +#define reg_tuner_data_1975_1968_len 8 +#define reg_tuner_data_1975_1968_lsb 1968 +#define p_reg_tuner_data_1983_1976 0xF0F7 +#define reg_tuner_data_1983_1976_pos 0 +#define reg_tuner_data_1983_1976_len 8 +#define reg_tuner_data_1983_1976_lsb 1976 +#define p_reg_tuner_data_1991_1984 0xF0F8 +#define reg_tuner_data_1991_1984_pos 0 +#define reg_tuner_data_1991_1984_len 8 +#define reg_tuner_data_1991_1984_lsb 1984 +#define p_reg_tuner_data_1999_1992 0xF0F9 +#define reg_tuner_data_1999_1992_pos 0 +#define reg_tuner_data_1999_1992_len 8 +#define reg_tuner_data_1999_1992_lsb 1992 +#define p_reg_tuner_data_2007_2000 0xF0FA +#define reg_tuner_data_2007_2000_pos 0 +#define reg_tuner_data_2007_2000_len 8 +#define reg_tuner_data_2007_2000_lsb 2000 +#define p_reg_tuner_data_2015_2008 0xF0FB +#define reg_tuner_data_2015_2008_pos 0 +#define reg_tuner_data_2015_2008_len 8 +#define reg_tuner_data_2015_2008_lsb 2008 +#define p_reg_tuner_data_2023_2016 0xF0FC +#define reg_tuner_data_2023_2016_pos 0 +#define reg_tuner_data_2023_2016_len 8 +#define reg_tuner_data_2023_2016_lsb 2016 +#define p_reg_tuner_data_2031_2024 0xF0FD +#define reg_tuner_data_2031_2024_pos 0 +#define reg_tuner_data_2031_2024_len 8 +#define reg_tuner_data_2031_2024_lsb 2024 +#define p_reg_tuner_data_2039_2032 0xF0FE +#define reg_tuner_data_2039_2032_pos 0 +#define reg_tuner_data_2039_2032_len 8 +#define reg_tuner_data_2039_2032_lsb 2032 +#define p_reg_tuner_data_2047_2040 0xF0FF +#define reg_tuner_data_2047_2040_pos 0 +#define reg_tuner_data_2047_2040_len 8 +#define reg_tuner_data_2047_2040_lsb 2040 +#define p_reg_tuner_master_rd_wr 0xF100 +#define reg_tuner_master_rd_wr_pos 0 +#define reg_tuner_master_rd_wr_len 1 +#define reg_tuner_master_rd_wr_lsb 0 +#define p_reg_tuner_master_length 0xF101 +#define reg_tuner_master_length_pos 0 +#define reg_tuner_master_length_len 8 +#define reg_tuner_master_length_lsb 0 +#define p_reg_tuner_cmd_exe 0xF102 +#define reg_tuner_cmd_exe_pos 0 +#define reg_tuner_cmd_exe_len 1 +#define reg_tuner_cmd_exe_lsb 0 +#define p_reg_tuner_wdat_done 0xF102 +#define reg_tuner_wdat_done_pos 1 +#define reg_tuner_wdat_done_len 1 +#define reg_tuner_wdat_done_lsb 0 +#define p_reg_tuner_wdat_fail 0xF102 +#define reg_tuner_wdat_fail_pos 2 +#define reg_tuner_wdat_fail_len 1 +#define reg_tuner_wdat_fail_lsb 0 +#define p_reg_tuner_ofsm_i2cm_rdat_rdy 0xF102 +#define reg_tuner_ofsm_i2cm_rdat_rdy_pos 3 +#define reg_tuner_ofsm_i2cm_rdat_rdy_len 1 +#define reg_tuner_ofsm_i2cm_rdat_rdy_lsb 0 +#define p_reg_tuner_current_state 0xF102 +#define reg_tuner_current_state_pos 4 +#define reg_tuner_current_state_len 3 +#define reg_tuner_current_state_lsb 0 +#define p_reg_one_cycle_counter_tuner 0xF103 +#define reg_one_cycle_counter_tuner_pos 0 +#define reg_one_cycle_counter_tuner_len 8 +#define reg_one_cycle_counter_tuner_lsb 0 +#define p_reg_msb_lsb 0xF104 +#define reg_msb_lsb_pos 0 +#define reg_msb_lsb_len 1 +#define reg_msb_lsb_lsb 0 +#define p_reg_ofdm_rst 0xF104 +#define p_reg_sel_thirdi2c 0xF104 +#define reg_sel_thirdi2c_pos 2 +#define reg_sel_thirdi2c_len 1 +#define reg_sel_thirdi2c_lsb 0 +#define p_reg_sel_tuner 0xF104 +#define p_reg_ofdm_rst_en 0xF104 +#define p_reg_sdio_cccr_v 0xF140 +#define reg_sdio_cccr_v_pos 0 +#define reg_sdio_cccr_v_len 4 +#define reg_sdio_cccr_v_lsb 0 +#define p_reg_sdio_sdio_v 0xF140 +#define reg_sdio_sdio_v_pos 4 +#define reg_sdio_sdio_v_len 4 +#define reg_sdio_sdio_v_lsb 0 +#define p_reg_sdioc_sd_v 0xF141 +#define reg_sdioc_sd_v_pos 0 +#define reg_sdioc_sd_v_len 4 +#define reg_sdioc_sd_v_lsb 0 +#define p_reg_sdioc_ior1 0xF143 +#define reg_sdioc_ior1_pos 1 +#define reg_sdioc_ior1_len 1 +#define reg_sdioc_ior1_lsb 0 +#define p_reg_sdioc_int1 0xF145 +#define reg_sdioc_int1_pos 1 +#define reg_sdioc_int1_len 1 +#define reg_sdioc_int1_lsb 0 +#define p_reg_sdioc_scsi 0xF147 +#define reg_sdioc_scsi_pos 6 +#define reg_sdioc_scsi_len 1 +#define reg_sdioc_scsi_lsb 0 +#define p_reg_sdioc_sdc 0xF148 +#define reg_sdioc_sdc_pos 0 +#define reg_sdioc_sdc_len 1 +#define reg_sdioc_sdc_lsb 0 +#define p_reg_sdioc_smb 0xF148 +#define reg_sdioc_smb_pos 1 +#define reg_sdioc_smb_len 1 +#define reg_sdioc_smb_lsb 0 +#define p_reg_sdioc_srw 0xF148 +#define reg_sdioc_srw_pos 2 +#define reg_sdioc_srw_len 1 +#define reg_sdioc_srw_lsb 0 +#define p_reg_sdioc_sbs 0xF148 +#define reg_sdioc_sbs_pos 3 +#define reg_sdioc_sbs_len 1 +#define reg_sdioc_sbs_lsb 0 +#define p_reg_sdioc_s4mi 0xF148 +#define reg_sdioc_s4mi_pos 4 +#define reg_sdioc_s4mi_len 1 +#define reg_sdioc_s4mi_lsb 0 +#define p_reg_sdioc_lsc 0xF148 +#define reg_sdioc_lsc_pos 6 +#define reg_sdioc_lsc_len 1 +#define reg_sdioc_lsc_lsb 0 +#define p_reg_sdioc_4bls 0xF148 +#define reg_sdioc_4bls_pos 7 +#define reg_sdioc_4bls_len 1 +#define reg_sdioc_4bls_lsb 0 +#define p_reg_sdioc_cis_7_0 0xF149 +#define reg_sdioc_cis_7_0_pos 0 +#define reg_sdioc_cis_7_0_len 8 +#define reg_sdioc_cis_7_0_lsb 0 +#define p_reg_sdioc_cis_15_8 0xF14A +#define reg_sdioc_cis_15_8_pos 0 +#define reg_sdioc_cis_15_8_len 8 +#define reg_sdioc_cis_15_8_lsb 8 +#define p_reg_sdioc_cis_23_16 0xF14B +#define reg_sdioc_cis_23_16_pos 0 +#define reg_sdioc_cis_23_16_len 8 +#define reg_sdioc_cis_23_16_lsb 16 +#define p_reg_sdioc_fs 0xF14D +#define reg_sdioc_fs_pos 0 +#define reg_sdioc_fs_len 4 +#define reg_sdioc_fs_lsb 0 +#define p_reg_sdioc_df 0xF14D +#define reg_sdioc_df_pos 7 +#define reg_sdioc_df_len 1 +#define reg_sdioc_df_lsb 0 +#define p_reg_sdioc_ex1 0xF14E +#define reg_sdioc_ex1_pos 1 +#define reg_sdioc_ex1_len 1 +#define reg_sdioc_ex1_lsb 0 +#define p_reg_sdioc_rf1 0xF14F +#define reg_sdioc_rf1_pos 1 +#define reg_sdioc_rf1_len 1 +#define reg_sdioc_rf1_lsb 0 +#define p_reg_sdioc_smpc 0xF152 +#define reg_sdioc_smpc_pos 0 +#define reg_sdioc_smpc_len 1 +#define reg_sdioc_smpc_lsb 0 +#define p_reg_sdioc_f1_code 0xF160 +#define reg_sdioc_f1_code_pos 0 +#define reg_sdioc_f1_code_len 4 +#define reg_sdioc_f1_code_lsb 0 +#define p_reg_sdioc_scsa 0xF160 +#define reg_sdioc_scsa_pos 6 +#define reg_sdioc_scsa_len 1 +#define reg_sdioc_scsa_lsb 0 +#define p_reg_sdioc_csa_en 0xF160 +#define reg_sdioc_csa_en_pos 7 +#define reg_sdioc_csa_en_len 1 +#define reg_sdioc_csa_en_lsb 0 +#define p_reg_sdioc_f1_ext_code 0xF161 +#define reg_sdioc_f1_ext_code_pos 0 +#define reg_sdioc_f1_ext_code_len 8 +#define reg_sdioc_f1_ext_code_lsb 0 +#define p_reg_sdioc_sps 0xF162 +#define reg_sdioc_sps_pos 0 +#define reg_sdioc_sps_len 1 +#define reg_sdioc_sps_lsb 0 +#define p_reg_sdioc_func1_cis_ptr_7_0 0xF169 +#define reg_sdioc_func1_cis_ptr_7_0_pos 0 +#define reg_sdioc_func1_cis_ptr_7_0_len 8 +#define reg_sdioc_func1_cis_ptr_7_0_lsb 0 +#define p_reg_sdioc_func1_cis_ptr_15_8 0xF16A +#define reg_sdioc_func1_cis_ptr_15_8_pos 0 +#define reg_sdioc_func1_cis_ptr_15_8_len 8 +#define reg_sdioc_func1_cis_ptr_15_8_lsb 8 +#define p_reg_sdioc_func1_cis_ptr_23_16 0xF16B +#define reg_sdioc_func1_cis_ptr_23_16_pos 0 +#define reg_sdioc_func1_cis_ptr_23_16_len 8 +#define reg_sdioc_func1_cis_ptr_23_16_lsb 16 +#define p_reg_sdio_FUNCID0_0 0xF180 +#define reg_sdio_FUNCID0_0_pos 0 +#define reg_sdio_FUNCID0_0_len 8 +#define reg_sdio_FUNCID0_0_lsb 0 +#define p_reg_sdio_FUNCID0_1 0xF181 +#define reg_sdio_FUNCID0_1_pos 0 +#define reg_sdio_FUNCID0_1_len 8 +#define reg_sdio_FUNCID0_1_lsb 0 +#define p_reg_sdio_FUNCID0_2 0xF182 +#define reg_sdio_FUNCID0_2_pos 0 +#define reg_sdio_FUNCID0_2_len 8 +#define reg_sdio_FUNCID0_2_lsb 0 +#define p_reg_sdio_FUNCID0_3 0xF183 +#define reg_sdio_FUNCID0_3_pos 0 +#define reg_sdio_FUNCID0_3_len 8 +#define reg_sdio_FUNCID0_3_lsb 0 +#define p_reg_sdio_MANFID0_0 0xF184 +#define reg_sdio_MANFID0_0_pos 0 +#define reg_sdio_MANFID0_0_len 8 +#define reg_sdio_MANFID0_0_lsb 0 +#define p_reg_sdio_MANFID0_1 0xF185 +#define reg_sdio_MANFID0_1_pos 0 +#define reg_sdio_MANFID0_1_len 8 +#define reg_sdio_MANFID0_1_lsb 0 +#define p_reg_sdio_MANFID0_2_7_0 0xF186 +#define reg_sdio_MANFID0_2_7_0_pos 0 +#define reg_sdio_MANFID0_2_7_0_len 8 +#define reg_sdio_MANFID0_2_7_0_lsb 0 +#define p_reg_sdio_MANFID0_2_15_8 0xF187 +#define reg_sdio_MANFID0_2_15_8_pos 0 +#define reg_sdio_MANFID0_2_15_8_len 8 +#define reg_sdio_MANFID0_2_15_8_lsb 8 +#define p_reg_sdio_MANFID0_4_7_0 0xF188 +#define reg_sdio_MANFID0_4_7_0_pos 0 +#define reg_sdio_MANFID0_4_7_0_len 8 +#define reg_sdio_MANFID0_4_7_0_lsb 0 +#define p_reg_sdio_MANFID0_4_15_8 0xF189 +#define reg_sdio_MANFID0_4_15_8_pos 0 +#define reg_sdio_MANFID0_4_15_8_len 8 +#define reg_sdio_MANFID0_4_15_8_lsb 8 +#define p_reg_sdio_FUNCE0_0 0xF18A +#define reg_sdio_FUNCE0_0_pos 0 +#define reg_sdio_FUNCE0_0_len 8 +#define reg_sdio_FUNCE0_0_lsb 0 +#define p_reg_sdio_FUNCE0_1 0xF18B +#define reg_sdio_FUNCE0_1_pos 0 +#define reg_sdio_FUNCE0_1_len 8 +#define reg_sdio_FUNCE0_1_lsb 0 +#define p_reg_sdio_FUNCE0_2 0xF18C +#define reg_sdio_FUNCE0_2_pos 0 +#define reg_sdio_FUNCE0_2_len 8 +#define reg_sdio_FUNCE0_2_lsb 0 +#define p_reg_sdio_FUNCE0_3_7_0 0xF18D +#define reg_sdio_FUNCE0_3_7_0_pos 0 +#define reg_sdio_FUNCE0_3_7_0_len 8 +#define reg_sdio_FUNCE0_3_7_0_lsb 0 +#define p_reg_sdio_FUNCE0_3_15_8 0xF18E +#define reg_sdio_FUNCE0_3_15_8_pos 0 +#define reg_sdio_FUNCE0_3_15_8_len 8 +#define reg_sdio_FUNCE0_3_15_8_lsb 8 +#define p_reg_sdio_FUNCE0_5 0xF18F +#define reg_sdio_FUNCE0_5_pos 0 +#define reg_sdio_FUNCE0_5_len 8 +#define reg_sdio_FUNCE0_5_lsb 0 +#define p_reg_sdio_VERS_10_0 0xF190 +#define reg_sdio_VERS_10_0_pos 0 +#define reg_sdio_VERS_10_0_len 8 +#define reg_sdio_VERS_10_0_lsb 0 +#define p_reg_sdio_VERS_10_1 0xF191 +#define reg_sdio_VERS_10_1_pos 0 +#define reg_sdio_VERS_10_1_len 8 +#define reg_sdio_VERS_10_1_lsb 0 +#define p_reg_sdio_VERS_10_2 0xF192 +#define reg_sdio_VERS_10_2_pos 0 +#define reg_sdio_VERS_10_2_len 8 +#define reg_sdio_VERS_10_2_lsb 0 +#define p_reg_sdio_VERS_10_3 0xF193 +#define reg_sdio_VERS_10_3_pos 0 +#define reg_sdio_VERS_10_3_len 8 +#define reg_sdio_VERS_10_3_lsb 0 +#define p_reg_sdio_VERS_10_4 0xF194 +#define reg_sdio_VERS_10_4_pos 0 +#define reg_sdio_VERS_10_4_len 8 +#define reg_sdio_VERS_10_4_lsb 0 +#define p_reg_sdio_VERS_10_5 0xF195 +#define reg_sdio_VERS_10_5_pos 0 +#define reg_sdio_VERS_10_5_len 8 +#define reg_sdio_VERS_10_5_lsb 0 +#define p_reg_sdio_VERS_10_6 0xF196 +#define reg_sdio_VERS_10_6_pos 0 +#define reg_sdio_VERS_10_6_len 8 +#define reg_sdio_VERS_10_6_lsb 0 +#define p_reg_sdio_VERS_10_7 0xF197 +#define reg_sdio_VERS_10_7_pos 0 +#define reg_sdio_VERS_10_7_len 8 +#define reg_sdio_VERS_10_7_lsb 0 +#define p_reg_sdio_VERS_10_8 0xF198 +#define reg_sdio_VERS_10_8_pos 0 +#define reg_sdio_VERS_10_8_len 8 +#define reg_sdio_VERS_10_8_lsb 0 +#define p_reg_sdio_VERS_10_9 0xF199 +#define reg_sdio_VERS_10_9_pos 0 +#define reg_sdio_VERS_10_9_len 8 +#define reg_sdio_VERS_10_9_lsb 0 +#define p_reg_sdio_VERS_10_A 0xF19A +#define reg_sdio_VERS_10_A_pos 0 +#define reg_sdio_VERS_10_A_len 8 +#define reg_sdio_VERS_10_A_lsb 0 +#define p_reg_sdio_VERS_10_B 0xF19B +#define reg_sdio_VERS_10_B_pos 0 +#define reg_sdio_VERS_10_B_len 8 +#define reg_sdio_VERS_10_B_lsb 0 +#define p_reg_sdio_VERS_10_C 0xF19C +#define reg_sdio_VERS_10_C_pos 0 +#define reg_sdio_VERS_10_C_len 8 +#define reg_sdio_VERS_10_C_lsb 0 +#define p_reg_sdio_VERS_10_D 0xF19D +#define reg_sdio_VERS_10_D_pos 0 +#define reg_sdio_VERS_10_D_len 8 +#define reg_sdio_VERS_10_D_lsb 0 +#define p_reg_sdio_VERS_10_E 0xF19E +#define reg_sdio_VERS_10_E_pos 0 +#define reg_sdio_VERS_10_E_len 8 +#define reg_sdio_VERS_10_E_lsb 0 +#define p_reg_sdio_VERS_10_F 0xF19F +#define reg_sdio_VERS_10_F_pos 0 +#define reg_sdio_VERS_10_F_len 8 +#define reg_sdio_VERS_10_F_lsb 0 +#define p_reg_sdio_VERS_10_10 0xF1A0 +#define reg_sdio_VERS_10_10_pos 0 +#define reg_sdio_VERS_10_10_len 8 +#define reg_sdio_VERS_10_10_lsb 0 +#define p_reg_sdio_VERS_10_11 0xF1A1 +#define reg_sdio_VERS_10_11_pos 0 +#define reg_sdio_VERS_10_11_len 8 +#define reg_sdio_VERS_10_11_lsb 0 +#define p_reg_sdio_VERS_10_12 0xF1A2 +#define reg_sdio_VERS_10_12_pos 0 +#define reg_sdio_VERS_10_12_len 8 +#define reg_sdio_VERS_10_12_lsb 0 +#define p_reg_sdio_VERS_10_13 0xF1A3 +#define reg_sdio_VERS_10_13_pos 0 +#define reg_sdio_VERS_10_13_len 8 +#define reg_sdio_VERS_10_13_lsb 0 +#define p_reg_sdio_VERS_10_14 0xF1A4 +#define reg_sdio_VERS_10_14_pos 0 +#define reg_sdio_VERS_10_14_len 8 +#define reg_sdio_VERS_10_14_lsb 0 +#define p_reg_sdio_VERS_10_15 0xF1A5 +#define reg_sdio_VERS_10_15_pos 0 +#define reg_sdio_VERS_10_15_len 8 +#define reg_sdio_VERS_10_15_lsb 0 +#define p_reg_sdio_VERS_10_16 0xF1A6 +#define reg_sdio_VERS_10_16_pos 0 +#define reg_sdio_VERS_10_16_len 8 +#define reg_sdio_VERS_10_16_lsb 0 +#define p_reg_sdio_VERS_10_17 0xF1A7 +#define reg_sdio_VERS_10_17_pos 0 +#define reg_sdio_VERS_10_17_len 8 +#define reg_sdio_VERS_10_17_lsb 0 +#define p_reg_sdio_VERS_10_18 0xF1A8 +#define reg_sdio_VERS_10_18_pos 0 +#define reg_sdio_VERS_10_18_len 8 +#define reg_sdio_VERS_10_18_lsb 0 +#define p_reg_sdio_VERS_10_19 0xF1A9 +#define reg_sdio_VERS_10_19_pos 0 +#define reg_sdio_VERS_10_19_len 8 +#define reg_sdio_VERS_10_19_lsb 0 +#define p_reg_sdio_VERS_10_1A 0xF1AA +#define reg_sdio_VERS_10_1A_pos 0 +#define reg_sdio_VERS_10_1A_len 8 +#define reg_sdio_VERS_10_1A_lsb 0 +#define p_reg_sdio_VERS_10_1B 0xF1AB +#define reg_sdio_VERS_10_1B_pos 0 +#define reg_sdio_VERS_10_1B_len 8 +#define reg_sdio_VERS_10_1B_lsb 0 +#define p_reg_sdio_VERS_10_1C 0xF1AC +#define reg_sdio_VERS_10_1C_pos 0 +#define reg_sdio_VERS_10_1C_len 8 +#define reg_sdio_VERS_10_1C_lsb 0 +#define p_reg_sdio_VERS_10_1D 0xF1AD +#define reg_sdio_VERS_10_1D_pos 0 +#define reg_sdio_VERS_10_1D_len 8 +#define reg_sdio_VERS_10_1D_lsb 0 +#define p_reg_sdio_VERS_10_1E 0xF1AE +#define reg_sdio_VERS_10_1E_pos 0 +#define reg_sdio_VERS_10_1E_len 8 +#define reg_sdio_VERS_10_1E_lsb 0 +#define p_reg_sdio_VERS_10_1F 0xF1AF +#define reg_sdio_VERS_10_1F_pos 0 +#define reg_sdio_VERS_10_1F_len 8 +#define reg_sdio_VERS_10_1F_lsb 0 +#define p_reg_sdio_VERS_10_20 0xF1B0 +#define reg_sdio_VERS_10_20_pos 0 +#define reg_sdio_VERS_10_20_len 8 +#define reg_sdio_VERS_10_20_lsb 0 +#define p_reg_sdio_VERS_10_21 0xF1B1 +#define reg_sdio_VERS_10_21_pos 0 +#define reg_sdio_VERS_10_21_len 8 +#define reg_sdio_VERS_10_21_lsb 0 +#define p_reg_sdio_VERS_10_22 0xF1B2 +#define reg_sdio_VERS_10_22_pos 0 +#define reg_sdio_VERS_10_22_len 8 +#define reg_sdio_VERS_10_22_lsb 0 +#define p_reg_sdio_VERS_10_23 0xF1B3 +#define reg_sdio_VERS_10_23_pos 0 +#define reg_sdio_VERS_10_23_len 8 +#define reg_sdio_VERS_10_23_lsb 0 +#define p_reg_sdio_VERS_10_24 0xF1B4 +#define reg_sdio_VERS_10_24_pos 0 +#define reg_sdio_VERS_10_24_len 8 +#define reg_sdio_VERS_10_24_lsb 0 +#define p_reg_sdio_VERS_10_25 0xF1B5 +#define reg_sdio_VERS_10_25_pos 0 +#define reg_sdio_VERS_10_25_len 8 +#define reg_sdio_VERS_10_25_lsb 0 +#define p_reg_sdio_VERS_10_26 0xF1B6 +#define reg_sdio_VERS_10_26_pos 0 +#define reg_sdio_VERS_10_26_len 8 +#define reg_sdio_VERS_10_26_lsb 0 +#define p_reg_sdio_VERS_10_27 0xF1B7 +#define reg_sdio_VERS_10_27_pos 0 +#define reg_sdio_VERS_10_27_len 8 +#define reg_sdio_VERS_10_27_lsb 0 +#define p_reg_sdio_END0 0xF1B8 +#define reg_sdio_END0_pos 0 +#define reg_sdio_END0_len 8 +#define reg_sdio_END0_lsb 0 +#define p_reg_sdio_FUNCID1_0 0xF1C0 +#define reg_sdio_FUNCID1_0_pos 0 +#define reg_sdio_FUNCID1_0_len 8 +#define reg_sdio_FUNCID1_0_lsb 0 +#define p_reg_sdio_FUNCID1_1 0xF1C1 +#define reg_sdio_FUNCID1_1_pos 0 +#define reg_sdio_FUNCID1_1_len 8 +#define reg_sdio_FUNCID1_1_lsb 0 +#define p_reg_sdio_FUNCID1_2 0xF1C2 +#define reg_sdio_FUNCID1_2_pos 0 +#define reg_sdio_FUNCID1_2_len 8 +#define reg_sdio_FUNCID1_2_lsb 0 +#define p_reg_sdio_FUNCID1_3 0xF1C3 +#define reg_sdio_FUNCID1_3_pos 0 +#define reg_sdio_FUNCID1_3_len 8 +#define reg_sdio_FUNCID1_3_lsb 0 +#define p_reg_sdio_FUNCE1_0 0xF1C4 +#define reg_sdio_FUNCE1_0_pos 0 +#define reg_sdio_FUNCE1_0_len 8 +#define reg_sdio_FUNCE1_0_lsb 0 +#define p_reg_sdio_FUNCE1_1 0xF1C5 +#define reg_sdio_FUNCE1_1_pos 0 +#define reg_sdio_FUNCE1_1_len 8 +#define reg_sdio_FUNCE1_1_lsb 0 +#define p_reg_sdio_FUNCE1_2 0xF1C6 +#define reg_sdio_FUNCE1_2_pos 0 +#define reg_sdio_FUNCE1_2_len 8 +#define reg_sdio_FUNCE1_2_lsb 0 +#define p_reg_sdio_FUNCE1_3 0xF1C7 +#define reg_sdio_FUNCE1_3_pos 0 +#define reg_sdio_FUNCE1_3_len 8 +#define reg_sdio_FUNCE1_3_lsb 0 +#define p_reg_sdio_FUNCE1_4 0xF1C8 +#define reg_sdio_FUNCE1_4_pos 0 +#define reg_sdio_FUNCE1_4_len 8 +#define reg_sdio_FUNCE1_4_lsb 0 +#define p_reg_sdio_FUNCE1_5_7_0 0xF1C9 +#define reg_sdio_FUNCE1_5_7_0_pos 0 +#define reg_sdio_FUNCE1_5_7_0_len 8 +#define reg_sdio_FUNCE1_5_7_0_lsb 0 +#define p_reg_sdio_FUNCE1_5_15_8 0xF1CA +#define reg_sdio_FUNCE1_5_15_8_pos 0 +#define reg_sdio_FUNCE1_5_15_8_len 8 +#define reg_sdio_FUNCE1_5_15_8_lsb 8 +#define p_reg_sdio_FUNCE1_5_23_16 0xF1CB +#define reg_sdio_FUNCE1_5_23_16_pos 0 +#define reg_sdio_FUNCE1_5_23_16_len 8 +#define reg_sdio_FUNCE1_5_23_16_lsb 16 +#define p_reg_sdio_FUNCE1_5_31_24 0xF1CC +#define reg_sdio_FUNCE1_5_31_24_pos 0 +#define reg_sdio_FUNCE1_5_31_24_len 8 +#define reg_sdio_FUNCE1_5_31_24_lsb 24 +#define p_reg_sdio_FUNCE1_9_7_0 0xF1CD +#define reg_sdio_FUNCE1_9_7_0_pos 0 +#define reg_sdio_FUNCE1_9_7_0_len 8 +#define reg_sdio_FUNCE1_9_7_0_lsb 0 +#define p_reg_sdio_FUNCE1_9_15_8 0xF1CE +#define reg_sdio_FUNCE1_9_15_8_pos 0 +#define reg_sdio_FUNCE1_9_15_8_len 8 +#define reg_sdio_FUNCE1_9_15_8_lsb 8 +#define p_reg_sdio_FUNCE1_9_23_16 0xF1CF +#define reg_sdio_FUNCE1_9_23_16_pos 0 +#define reg_sdio_FUNCE1_9_23_16_len 8 +#define reg_sdio_FUNCE1_9_23_16_lsb 16 +#define p_reg_sdio_FUNCE1_9_31_24 0xF1D0 +#define reg_sdio_FUNCE1_9_31_24_pos 0 +#define reg_sdio_FUNCE1_9_31_24_len 8 +#define reg_sdio_FUNCE1_9_31_24_lsb 24 +#define p_reg_sdio_FUNCE1_D 0xF1D1 +#define reg_sdio_FUNCE1_D_pos 0 +#define reg_sdio_FUNCE1_D_len 8 +#define reg_sdio_FUNCE1_D_lsb 0 +#define p_reg_sdio_FUNCE1_E_7_0 0xF1D2 +#define reg_sdio_FUNCE1_E_7_0_pos 0 +#define reg_sdio_FUNCE1_E_7_0_len 8 +#define reg_sdio_FUNCE1_E_7_0_lsb 0 +#define p_reg_sdio_FUNCE1_E_15_8 0xF1D3 +#define reg_sdio_FUNCE1_E_15_8_pos 0 +#define reg_sdio_FUNCE1_E_15_8_len 8 +#define reg_sdio_FUNCE1_E_15_8_lsb 8 +#define p_reg_sdio_FUNCE1_10_7_0 0xF1D4 +#define reg_sdio_FUNCE1_10_7_0_pos 0 +#define reg_sdio_FUNCE1_10_7_0_len 8 +#define reg_sdio_FUNCE1_10_7_0_lsb 0 +#define p_reg_sdio_FUNCE1_10_15_8 0xF1D5 +#define reg_sdio_FUNCE1_10_15_8_pos 0 +#define reg_sdio_FUNCE1_10_15_8_len 8 +#define reg_sdio_FUNCE1_10_15_8_lsb 8 +#define p_reg_sdio_FUNCE1_10_23_16 0xF1D6 +#define reg_sdio_FUNCE1_10_23_16_pos 0 +#define reg_sdio_FUNCE1_10_23_16_len 8 +#define reg_sdio_FUNCE1_10_23_16_lsb 16 +#define p_reg_sdio_FUNCE1_10_31_24 0xF1D7 +#define reg_sdio_FUNCE1_10_31_24_pos 0 +#define reg_sdio_FUNCE1_10_31_24_len 8 +#define reg_sdio_FUNCE1_10_31_24_lsb 24 +#define p_reg_sdio_FUNCE1_14 0xF1D8 +#define reg_sdio_FUNCE1_14_pos 0 +#define reg_sdio_FUNCE1_14_len 8 +#define reg_sdio_FUNCE1_14_lsb 0 +#define p_reg_sdio_FUNCE1_15 0xF1D9 +#define reg_sdio_FUNCE1_15_pos 0 +#define reg_sdio_FUNCE1_15_len 8 +#define reg_sdio_FUNCE1_15_lsb 0 +#define p_reg_sdio_FUNCE1_16 0xF1DA +#define reg_sdio_FUNCE1_16_pos 0 +#define reg_sdio_FUNCE1_16_len 8 +#define reg_sdio_FUNCE1_16_lsb 0 +#define p_reg_sdio_FUNCE1_17 0xF1DB +#define reg_sdio_FUNCE1_17_pos 0 +#define reg_sdio_FUNCE1_17_len 8 +#define reg_sdio_FUNCE1_17_lsb 0 +#define p_reg_sdio_FUNCE1_18 0xF1DC +#define reg_sdio_FUNCE1_18_pos 0 +#define reg_sdio_FUNCE1_18_len 8 +#define reg_sdio_FUNCE1_18_lsb 0 +#define p_reg_sdio_FUNCE1_19 0xF1DD +#define reg_sdio_FUNCE1_19_pos 0 +#define reg_sdio_FUNCE1_19_len 8 +#define reg_sdio_FUNCE1_19_lsb 0 +#define p_reg_sdio_FUNCE1_1A_7_0 0xF1DE +#define reg_sdio_FUNCE1_1A_7_0_pos 0 +#define reg_sdio_FUNCE1_1A_7_0_len 8 +#define reg_sdio_FUNCE1_1A_7_0_lsb 0 +#define p_reg_sdio_FUNCE1_1A_15_8 0xF1DF +#define reg_sdio_FUNCE1_1A_15_8_pos 0 +#define reg_sdio_FUNCE1_1A_15_8_len 8 +#define reg_sdio_FUNCE1_1A_15_8_lsb 8 +#define p_reg_sdio_FUNCE1_1C_7_0 0xF1E0 +#define reg_sdio_FUNCE1_1C_7_0_pos 0 +#define reg_sdio_FUNCE1_1C_7_0_len 8 +#define reg_sdio_FUNCE1_1C_7_0_lsb 0 +#define p_reg_sdio_FUNCE1_1C_15_8 0xF1E1 +#define reg_sdio_FUNCE1_1C_15_8_pos 0 +#define reg_sdio_FUNCE1_1C_15_8_len 8 +#define reg_sdio_FUNCE1_1C_15_8_lsb 8 +#define p_reg_sdio_FUNCE1_1E_7_0 0xF1E2 +#define reg_sdio_FUNCE1_1E_7_0_pos 0 +#define reg_sdio_FUNCE1_1E_7_0_len 8 +#define reg_sdio_FUNCE1_1E_7_0_lsb 0 +#define p_reg_sdio_FUNCE1_1E_15_8 0xF1E3 +#define reg_sdio_FUNCE1_1E_15_8_pos 0 +#define reg_sdio_FUNCE1_1E_15_8_len 8 +#define reg_sdio_FUNCE1_1E_15_8_lsb 8 +#define p_reg_sdio_FUNCE1_20_7_0 0xF1E4 +#define reg_sdio_FUNCE1_20_7_0_pos 0 +#define reg_sdio_FUNCE1_20_7_0_len 8 +#define reg_sdio_FUNCE1_20_7_0_lsb 0 +#define p_reg_sdio_FUNCE1_20_15_8 0xF1E5 +#define reg_sdio_FUNCE1_20_15_8_pos 0 +#define reg_sdio_FUNCE1_20_15_8_len 8 +#define reg_sdio_FUNCE1_20_15_8_lsb 8 +#define p_reg_sdio_FUNCE1_22_7_0 0xF1E6 +#define reg_sdio_FUNCE1_22_7_0_pos 0 +#define reg_sdio_FUNCE1_22_7_0_len 8 +#define reg_sdio_FUNCE1_22_7_0_lsb 0 +#define p_reg_sdio_FUNCE1_22_15_8 0xF1E7 +#define reg_sdio_FUNCE1_22_15_8_pos 0 +#define reg_sdio_FUNCE1_22_15_8_len 8 +#define reg_sdio_FUNCE1_22_15_8_lsb 8 +#define p_reg_sdio_FUNCE1_24_7_0 0xF1E8 +#define reg_sdio_FUNCE1_24_7_0_pos 0 +#define reg_sdio_FUNCE1_24_7_0_len 8 +#define reg_sdio_FUNCE1_24_7_0_lsb 0 +#define p_reg_sdio_FUNCE1_24_15_8 0xF1E9 +#define reg_sdio_FUNCE1_24_15_8_pos 0 +#define reg_sdio_FUNCE1_24_15_8_len 8 +#define reg_sdio_FUNCE1_24_15_8_lsb 8 +#define p_reg_sdio_FUNCE1_26_7_0 0xF1EA +#define reg_sdio_FUNCE1_26_7_0_pos 0 +#define reg_sdio_FUNCE1_26_7_0_len 8 +#define reg_sdio_FUNCE1_26_7_0_lsb 0 +#define p_reg_sdio_FUNCE1_26_15_8 0xF1EB +#define reg_sdio_FUNCE1_26_15_8_pos 0 +#define reg_sdio_FUNCE1_26_15_8_len 8 +#define reg_sdio_FUNCE1_26_15_8_lsb 8 +#define p_reg_sdio_FUNCE1_28_7_0 0xF1EC +#define reg_sdio_FUNCE1_28_7_0_pos 0 +#define reg_sdio_FUNCE1_28_7_0_len 8 +#define reg_sdio_FUNCE1_28_7_0_lsb 0 +#define p_reg_sdio_FUNCE1_28_15_8 0xF1ED +#define reg_sdio_FUNCE1_28_15_8_pos 0 +#define reg_sdio_FUNCE1_28_15_8_len 8 +#define reg_sdio_FUNCE1_28_15_8_lsb 8 +#define p_reg_sdio_FUNCE1_2A_7_0 0xF1EE +#define reg_sdio_FUNCE1_2A_7_0_pos 0 +#define reg_sdio_FUNCE1_2A_7_0_len 8 +#define reg_sdio_FUNCE1_2A_7_0_lsb 0 +#define p_reg_sdio_FUNCE1_2A_15_8 0xF1EF +#define reg_sdio_FUNCE1_2A_15_8_pos 0 +#define reg_sdio_FUNCE1_2A_15_8_len 8 +#define reg_sdio_FUNCE1_2A_15_8_lsb 8 +#define p_reg_sdio_END1 0xF1F0 +#define reg_sdio_END1_pos 0 +#define reg_sdio_END1_len 8 +#define reg_sdio_END1_lsb 0 +#define r_sdioc_tx_fifo_empty 0xF210 +#define sdioc_tx_fifo_empty_pos 0 +#define sdioc_tx_fifo_empty_len 1 +#define sdioc_tx_fifo_empty_lsb 0 +#define p_reg_sdio_53ra 0xF210 +#define reg_sdio_53ra_pos 1 +#define reg_sdio_53ra_len 1 +#define reg_sdio_53ra_lsb 0 +#define p_reg_sdioc_rd_wait_dly 0xF210 +#define reg_sdioc_rd_wait_dly_pos 4 +#define reg_sdioc_rd_wait_dly_len 2 +#define reg_sdioc_rd_wait_dly_lsb 0 +#define p_reg_write_mbx_complete 0xF211 +#define reg_write_mbx_complete_pos 0 +#define reg_write_mbx_complete_len 1 +#define reg_write_mbx_complete_lsb 0 +#define p_reg_sdioc_sw_err 0xF211 +#define reg_sdioc_sw_err_pos 1 +#define reg_sdioc_sw_err_len 1 +#define reg_sdioc_sw_err_lsb 0 +#define p_reg_sdioc_tran_dat_dly 0xF211 +#define reg_sdioc_tran_dat_dly_pos 4 +#define reg_sdioc_tran_dat_dly_len 3 +#define reg_sdioc_tran_dat_dly_lsb 0 +#define p_reg_sdioc_external_int_en 0xF212 +#define reg_sdioc_external_int_en_pos 1 +#define reg_sdioc_external_int_en_len 1 +#define reg_sdioc_external_int_en_lsb 0 +#define r_reg_sdioc_external_int 0xF212 +#define reg_sdioc_external_int_pos 2 +#define reg_sdioc_external_int_len 1 +#define reg_sdioc_external_int_lsb 0 +#define p_reg_auto_clrWB_en 0xF213 +#define reg_auto_clrWB_en_pos 0 +#define reg_auto_clrWB_en_len 1 +#define reg_auto_clrWB_en_lsb 0 +#define p_reg_sdioc_crc_s_dly 0xF213 +#define reg_sdioc_crc_s_dly_pos 1 +#define reg_sdioc_crc_s_dly_len 1 +#define reg_sdioc_crc_s_dly_lsb 0 +#define p_reg_sdioc_neg_out_sel 0xF213 +#define reg_sdioc_neg_out_sel_pos 2 +#define reg_sdioc_neg_out_sel_len 1 +#define reg_sdioc_neg_out_sel_lsb 0 +#define p_reg_sdioc_tx_fifo_rst 0xF213 +#define reg_sdioc_tx_fifo_rst_pos 4 +#define reg_sdioc_tx_fifo_rst_len 1 +#define reg_sdioc_tx_fifo_rst_lsb 0 +#define p_reg_sdioc_rx_fifo_rst 0xF213 +#define reg_sdioc_rx_fifo_rst_pos 5 +#define reg_sdioc_rx_fifo_rst_len 1 +#define reg_sdioc_rx_fifo_rst_lsb 0 +#define p_reg_sdioc_auto_rst_sm_en 0xF213 +#define reg_sdioc_auto_rst_sm_en_pos 6 +#define reg_sdioc_auto_rst_sm_en_len 1 +#define reg_sdioc_auto_rst_sm_en_lsb 0 +#define p_sdio_link_clr_Wbusy_en 0xF214 +#define sdio_link_clr_Wbusy_en_pos 0 +#define sdio_link_clr_Wbusy_en_len 1 +#define sdio_link_clr_Wbusy_en_lsb 0 +#define p_sdio_link_clr_Wbusy 0xF214 +#define sdio_link_clr_Wbusy_pos 1 +#define sdio_link_clr_Wbusy_len 1 +#define sdio_link_clr_Wbusy_lsb 0 +#define p_reg_sdioc_dbg_sel 0xF214 +#define reg_sdioc_dbg_sel_pos 4 +#define reg_sdioc_dbg_sel_len 4 +#define reg_sdioc_dbg_sel_lsb 0 +#define p_reg_sdioc_skip_ocr 0xF215 +#define reg_sdioc_skip_ocr_pos 0 +#define reg_sdioc_skip_ocr_len 1 +#define reg_sdioc_skip_ocr_lsb 0 +#define p_reg_sdioc_spi_ns 0xF215 +#define reg_sdioc_spi_ns_pos 1 +#define reg_sdioc_spi_ns_len 1 +#define reg_sdioc_spi_ns_lsb 0 +#define r_sdio_spi_mode 0xF215 +#define sdio_spi_mode_pos 7 +#define sdio_spi_mode_len 1 +#define sdio_spi_mode_lsb 0 +#define r_link_ofsm_mailbox_int 0xF402 +#define link_ofsm_mailbox_int_pos 4 +#define link_ofsm_mailbox_int_len 1 +#define link_ofsm_mailbox_int_lsb 0 +#define r_link_ofsm_dvbt_int 0xF403 +#define link_ofsm_dvbt_int_pos 2 +#define link_ofsm_dvbt_int_len 1 +#define link_ofsm_dvbt_int_lsb 0 +#define p_reg_dvbt_intsts 0xF404 +#define reg_dvbt_intsts_pos 2 +#define reg_dvbt_intsts_len 1 +#define reg_dvbt_intsts_lsb 0 +#define p_reg_link_mailbox_int 0xF405 +#define reg_link_mailbox_int_pos 5 +#define reg_link_mailbox_int_len 1 +#define reg_link_mailbox_int_lsb 0 +#define p_reg_mailbox_wptr_rst 0xF408 +#define reg_mailbox_wptr_rst_pos 0 +#define reg_mailbox_wptr_rst_len 1 +#define reg_mailbox_wptr_rst_lsb 0 +#define p_reg_link_mailbox_wptr 0xF409 +#define reg_link_mailbox_wptr_pos 0 +#define reg_link_mailbox_wptr_len 8 +#define reg_link_mailbox_wptr_lsb 0 +#define p_reg_link_mailbox_wend 0xF410 +#define reg_link_mailbox_wend_pos 0 +#define reg_link_mailbox_wend_len 1 +#define reg_link_mailbox_wend_lsb 0 +#define p_reg_rd_data_sel 0xF411 +#define reg_rd_data_sel_pos 0 +#define reg_rd_data_sel_len 2 +#define reg_rd_data_sel_lsb 0 +#define p_reg_fifo_rd_length_7_0 0xF412 +#define reg_fifo_rd_length_7_0_pos 0 +#define reg_fifo_rd_length_7_0_len 8 +#define reg_fifo_rd_length_7_0_lsb 0 +#define p_reg_fifo_rd_length_15_8 0xF413 +#define reg_fifo_rd_length_15_8_pos 0 +#define reg_fifo_rd_length_15_8_len 8 +#define reg_fifo_rd_length_15_8_lsb 8 +#define p_reg_fifo_rd_length_17_16 0xF414 +#define reg_fifo_rd_length_17_16_pos 0 +#define reg_fifo_rd_length_17_16_len 2 +#define reg_fifo_rd_length_17_16_lsb 16 +#define p_reg_rst_fifo_rptr 0xF414 +#define reg_rst_fifo_rptr_pos 6 +#define reg_rst_fifo_rptr_len 1 +#define reg_rst_fifo_rptr_lsb 0 +#define p_reg_force_sel 0xF414 +#define reg_force_sel_pos 7 +#define reg_force_sel_len 1 +#define reg_force_sel_lsb 0 +#define p_reg_fifo_rptr_7_0 0xF415 +#define reg_fifo_rptr_7_0_pos 0 +#define reg_fifo_rptr_7_0_len 8 +#define reg_fifo_rptr_7_0_lsb 0 +#define p_reg_fifo_rptr_15_8 0xF416 +#define reg_fifo_rptr_15_8_pos 0 +#define reg_fifo_rptr_15_8_len 8 +#define reg_fifo_rptr_15_8_lsb 8 +#define p_reg_fifo_rptr_17_16 0xF417 +#define reg_fifo_rptr_17_16_pos 0 +#define reg_fifo_rptr_17_16_len 2 +#define reg_fifo_rptr_17_16_lsb 16 +#define p_reg_max_package_size_7_0 0xF418 +#define reg_max_package_size_7_0_pos 0 +#define reg_max_package_size_7_0_len 8 +#define reg_max_package_size_7_0_lsb 0 +#define p_reg_max_package_size_11_8 0xF419 +#define reg_max_package_size_11_8_pos 0 +#define reg_max_package_size_11_8_len 4 +#define reg_max_package_size_11_8_lsb 8 +#define p_reg_dvbt_en 0xF41A +#define reg_dvbt_en_pos 0 +#define reg_dvbt_en_len 1 +#define reg_dvbt_en_lsb 0 +#define p_reg_dvbt_bufsize 0xF41A +#define reg_dvbt_bufsize_pos 1 +#define reg_dvbt_bufsize_len 1 +#define reg_dvbt_bufsize_lsb 0 +#define p_reg_dvbt_path 0xF41A +#define reg_dvbt_path_pos 2 +#define reg_dvbt_path_len 1 +#define reg_dvbt_path_lsb 0 +#define p_reg_dvbt_r5 0xF41A +#define reg_dvbt_r5_pos 3 +#define reg_dvbt_r5_len 1 +#define reg_dvbt_r5_lsb 0 +#define p_reg_mailbox_inten 0xF41E +#define reg_mailbox_inten_pos 4 +#define reg_mailbox_inten_len 1 +#define reg_mailbox_inten_lsb 0 +#define p_reg_dvbt_inten 0xF41F +#define reg_dvbt_inten_pos 2 +#define reg_dvbt_inten_len 1 +#define reg_dvbt_inten_lsb 0 +#define r_link_ofsm_ip_length_7_0 0xF447 +#define link_ofsm_ip_length_7_0_pos 0 +#define link_ofsm_ip_length_7_0_len 8 +#define link_ofsm_ip_length_7_0_lsb 0 +#define r_link_ofsm_ip_length_11_8 0xF448 +#define link_ofsm_ip_length_11_8_pos 0 +#define link_ofsm_ip_length_11_8_len 4 +#define link_ofsm_ip_length_11_8_lsb 8 +#define r_link_ofsm_ip_valid 0xF448 +#define link_ofsm_ip_valid_pos 7 +#define link_ofsm_ip_valid_len 1 +#define link_ofsm_ip_valid_lsb 0 +#define p_reg_spi_master 0xF600 +#define reg_spi_master_pos 0 +#define reg_spi_master_len 1 +#define reg_spi_master_lsb 0 +#define p_reg_spi_bit 0xF601 +#define reg_spi_bit_pos 0 +#define reg_spi_bit_len 2 +#define reg_spi_bit_lsb 0 +#define p_reg_spi_cs 0xF602 +#define reg_spi_cs_pos 0 +#define reg_spi_cs_len 1 +#define reg_spi_cs_lsb 0 +#define p_reg_spi_polarity 0xF602 +#define reg_spi_polarity_pos 1 +#define reg_spi_polarity_len 1 +#define reg_spi_polarity_lsb 0 +#define p_reg_spi_phase 0xF602 +#define reg_spi_phase_pos 2 +#define reg_spi_phase_len 1 +#define reg_spi_phase_lsb 0 +#define p_reg_spi_1st_byte 0xF603 +#define reg_spi_1st_byte_pos 0 +#define reg_spi_1st_byte_len 4 +#define reg_spi_1st_byte_lsb 0 +#define p_reg_spi_clk_div 0xF603 +#define reg_spi_clk_div_pos 4 +#define reg_spi_clk_div_len 4 +#define reg_spi_clk_div_lsb 0 +#define p_reg_spi_rst 0xF604 +#define reg_spi_rst_pos 0 +#define reg_spi_rst_len 1 +#define reg_spi_rst_lsb 0 +#define r_reg_spi_tx_done 0xF604 +#define reg_spi_tx_done_pos 1 +#define reg_spi_tx_done_len 1 +#define reg_spi_tx_done_lsb 0 +#define r_reg_spi_rx_done 0xF604 +#define reg_spi_rx_done_pos 2 +#define reg_spi_rx_done_len 1 +#define reg_spi_rx_done_lsb 0 +#define p_reg_spi_dbg_sel 0xF604 +#define reg_spi_dbg_sel_pos 3 +#define reg_spi_dbg_sel_len 1 +#define reg_spi_dbg_sel_lsb 0 +#define r_reg_spi_crc_err 0xF604 +#define reg_spi_crc_err_pos 4 +#define reg_spi_crc_err_len 4 +#define reg_spi_crc_err_lsb 0 +#define r_link_ofsm_usb20_mode 0xF613 +#define link_ofsm_usb20_mode_pos 0 +#define link_ofsm_usb20_mode_len 1 +#define link_ofsm_usb20_mode_lsb 0 +#define r_link_ofsm_strap_usb20_mode 0xF613 +#define link_ofsm_strap_usb20_mode_pos 1 +#define link_ofsm_strap_usb20_mode_len 1 +#define link_ofsm_strap_usb20_mode_lsb 0 +#define p_reg_link_stick_mem_end_7_0 0xF618 +#define reg_link_stick_mem_end_7_0_pos 0 +#define reg_link_stick_mem_end_7_0_len 8 +#define reg_link_stick_mem_end_7_0_lsb 0 +#define p_reg_link_stick_mem_end_15_8 0xF619 +#define reg_link_stick_mem_end_15_8_pos 0 +#define reg_link_stick_mem_end_15_8_len 8 +#define reg_link_stick_mem_end_15_8_lsb 8 +#define p_reg_ofdm_auto_write_addr_l 0xF61A +#define reg_ofdm_auto_write_addr_l_pos 0 +#define reg_ofdm_auto_write_addr_l_len 8 +#define reg_ofdm_auto_write_addr_l_lsb 0 +#define p_reg_ofdm_auto_write_addr_h 0xF61B +#define reg_ofdm_auto_write_addr_h_pos 0 +#define reg_ofdm_auto_write_addr_h_len 8 +#define reg_ofdm_auto_write_addr_h_lsb 0 +#define p_reg_link_auto_write_addr_l 0xF61C +#define reg_link_auto_write_addr_l_pos 0 +#define reg_link_auto_write_addr_l_len 8 +#define reg_link_auto_write_addr_l_lsb 0 +#define p_reg_link_auto_write_addr_h 0xF61D +#define reg_link_auto_write_addr_h_pos 0 +#define reg_link_auto_write_addr_h_len 8 +#define reg_link_auto_write_addr_h_lsb 0 +#define p_reg_mailbox_auto_write_addr 0xF61E +#define reg_mailbox_auto_write_addr_pos 0 +#define reg_mailbox_auto_write_addr_len 8 +#define reg_mailbox_auto_write_addr_lsb 0 +#define p_reg_usbmem_auto_write_addr 0xF61F +#define reg_usbmem_auto_write_addr_pos 0 +#define reg_usbmem_auto_write_addr_len 8 +#define reg_usbmem_auto_write_addr_lsb 0 +#define p_reg_mailbox_auto_read_addr 0xF620 +#define reg_mailbox_auto_read_addr_pos 0 +#define reg_mailbox_auto_read_addr_len 8 +#define reg_mailbox_auto_read_addr_lsb 0 +#define p_reg_usbmem_auto_read_addr 0xF621 +#define reg_usbmem_auto_read_addr_pos 0 +#define reg_usbmem_auto_read_addr_len 8 +#define reg_usbmem_auto_read_addr_lsb 0 +#define p_reg_auto_write_ofdm 0xF622 +#define reg_auto_write_ofdm_pos 0 +#define reg_auto_write_ofdm_len 1 +#define reg_auto_write_ofdm_lsb 0 +#define p_reg_auto_write_link 0xF622 +#define reg_auto_write_link_pos 1 +#define reg_auto_write_link_len 1 +#define reg_auto_write_link_lsb 0 +#define p_reg_auto_write_mailbox 0xF622 +#define reg_auto_write_mailbox_pos 2 +#define reg_auto_write_mailbox_len 1 +#define reg_auto_write_mailbox_lsb 0 +#define p_reg_auto_write_usbmem 0xF622 +#define reg_auto_write_usbmem_pos 3 +#define reg_auto_write_usbmem_len 1 +#define reg_auto_write_usbmem_lsb 0 +#define p_reg_auto_write_i2cm 0xF622 +#define reg_auto_write_i2cm_pos 4 +#define reg_auto_write_i2cm_len 1 +#define reg_auto_write_i2cm_lsb 0 +#define p_reg_auto_read_mailbox 0xF623 +#define reg_auto_read_mailbox_pos 0 +#define reg_auto_read_mailbox_len 1 +#define reg_auto_read_mailbox_lsb 0 +#define p_reg_auto_read_rom 0xF623 +#define reg_auto_read_rom_pos 1 +#define reg_auto_read_rom_len 1 +#define reg_auto_read_rom_lsb 0 +#define p_reg_auto_sum_l 0xF624 +#define reg_auto_sum_l_pos 0 +#define reg_auto_sum_l_len 8 +#define reg_auto_sum_l_lsb 0 +#define p_reg_auto_sum_h 0xF625 +#define reg_auto_sum_h_pos 0 +#define reg_auto_sum_h_len 8 +#define reg_auto_sum_h_lsb 0 +#define p_reg_auto_sum_to_h 0xF626 +#define reg_auto_sum_to_h_pos 0 +#define reg_auto_sum_to_h_len 1 +#define reg_auto_sum_to_h_lsb 0 +#define p_reg_auto_sum_en 0xF627 +#define reg_auto_sum_en_pos 0 +#define reg_auto_sum_en_len 1 +#define reg_auto_sum_en_lsb 0 +#define p_reg_rom_remap_begin_7_0 0xF628 +#define reg_rom_remap_begin_7_0_pos 0 +#define reg_rom_remap_begin_7_0_len 8 +#define reg_rom_remap_begin_7_0_lsb 0 +#define p_reg_rom_remap_begin_15_8 0xF629 +#define reg_rom_remap_begin_15_8_pos 0 +#define reg_rom_remap_begin_15_8_len 8 +#define reg_rom_remap_begin_15_8_lsb 8 +#define p_reg_rom_remap_end_7_0 0xF62A +#define reg_rom_remap_end_7_0_pos 0 +#define reg_rom_remap_end_7_0_len 8 +#define reg_rom_remap_end_7_0_lsb 0 +#define p_reg_rom_remap_end_15_8 0xF62B +#define reg_rom_remap_end_15_8_pos 0 +#define reg_rom_remap_end_15_8_len 8 +#define reg_rom_remap_end_15_8_lsb 8 +#define p_reg_rom_remap_delta_7_0 0xF62C +#define reg_rom_remap_delta_7_0_pos 0 +#define reg_rom_remap_delta_7_0_len 8 +#define reg_rom_remap_delta_7_0_lsb 0 +#define p_reg_rom_remap_delta_15_8 0xF62D +#define reg_rom_remap_delta_15_8_pos 0 +#define reg_rom_remap_delta_15_8_len 8 +#define reg_rom_remap_delta_15_8_lsb 8 +#define p_reg_rom_remap_en 0xF62E +#define reg_rom_remap_en_pos 0 +#define reg_rom_remap_en_len 1 +#define reg_rom_remap_en_lsb 0 +#define p_reg_rom_remap_ofdm 0xF62E +#define reg_rom_remap_ofdm_pos 1 +#define reg_rom_remap_ofdm_len 1 +#define reg_rom_remap_ofdm_lsb 0 +#define p_reg_link_cpu_reset 0xF62F +#define reg_link_cpu_reset_pos 0 +#define reg_link_cpu_reset_len 1 +#define reg_link_cpu_reset_lsb 0 +#define p_reg_i2cm_auto_write_addr 0xF630 +#define reg_i2cm_auto_write_addr_pos 0 +#define reg_i2cm_auto_write_addr_len 8 +#define reg_i2cm_auto_write_addr_lsb 0 +#define p_reg_link_bank_float_en 0xF631 +#define reg_link_bank_float_en_pos 0 +#define reg_link_bank_float_en_len 1 +#define reg_link_bank_float_en_lsb 0 +#define p_reg_link_bank_float_start 0xF632 +#define reg_link_bank_float_start_pos 0 +#define reg_link_bank_float_start_len 8 +#define reg_link_bank_float_start_lsb 0 +#define p_reg_link_bank_float_stop 0xF633 +#define reg_link_bank_float_stop_pos 0 +#define reg_link_bank_float_stop_len 8 +#define reg_link_bank_float_stop_lsb 0 +#define p_reg_rom_auto_read_addr_7_0 0xF638 +#define reg_rom_auto_read_addr_7_0_pos 0 +#define reg_rom_auto_read_addr_7_0_len 8 +#define reg_rom_auto_read_addr_7_0_lsb 0 +#define p_reg_rom_auto_read_addr_15_8 0xF639 +#define reg_rom_auto_read_addr_15_8_pos 0 +#define reg_rom_auto_read_addr_15_8_len 8 +#define reg_rom_auto_read_addr_15_8_lsb 8 +#define p_reg_link_ofsm_dummy_7_0 0xF640 +#define reg_link_ofsm_dummy_7_0_pos 0 +#define reg_link_ofsm_dummy_7_0_len 8 +#define reg_link_ofsm_dummy_7_0_lsb 0 +#define p_reg_link_ofsm_dummy_15_8 0xF641 +#define reg_link_ofsm_dummy_15_8_pos 0 +#define reg_link_ofsm_dummy_15_8_len 8 +#define reg_link_ofsm_dummy_15_8_lsb 8 +#define p_reg_link_ofsm_dummy_23_16 0xF642 +#define reg_link_ofsm_dummy_23_16_pos 0 +#define reg_link_ofsm_dummy_23_16_len 8 +#define reg_link_ofsm_dummy_23_16_lsb 16 +#define p_reg_link_ofsm_dummy_31_24 0xF643 +#define reg_link_ofsm_dummy_31_24_pos 0 +#define reg_link_ofsm_dummy_31_24_len 8 +#define reg_link_ofsm_dummy_31_24_lsb 24 +#define p_reg_link_ofsm_dummy_39_32 0xF644 +#define reg_link_ofsm_dummy_39_32_pos 0 +#define reg_link_ofsm_dummy_39_32_len 8 +#define reg_link_ofsm_dummy_39_32_lsb 32 +#define p_reg_link_ofsm_dummy_47_40 0xF645 +#define reg_link_ofsm_dummy_47_40_pos 0 +#define reg_link_ofsm_dummy_47_40_len 8 +#define reg_link_ofsm_dummy_47_40_lsb 40 +#define p_reg_link_ofsm_dummy_55_48 0xF646 +#define reg_link_ofsm_dummy_55_48_pos 0 +#define reg_link_ofsm_dummy_55_48_len 8 +#define reg_link_ofsm_dummy_55_48_lsb 48 +#define p_reg_link_ofsm_dummy_63_56 0xF647 +#define reg_link_ofsm_dummy_63_56_pos 0 +#define reg_link_ofsm_dummy_63_56_len 8 +#define reg_link_ofsm_dummy_63_56_lsb 56 +#define p_reg_link_ofsm_dummy_71_64 0xF648 +#define reg_link_ofsm_dummy_71_64_pos 0 +#define reg_link_ofsm_dummy_71_64_len 8 +#define reg_link_ofsm_dummy_71_64_lsb 64 +#define p_reg_link_ofsm_dummy_79_72 0xF649 +#define reg_link_ofsm_dummy_79_72_pos 0 +#define reg_link_ofsm_dummy_79_72_len 8 +#define reg_link_ofsm_dummy_79_72_lsb 72 +#define p_reg_sdio_mode 0xF66F +#define reg_sdio_mode_pos 0 +#define reg_sdio_mode_len 1 +#define reg_sdio_mode_lsb 0 +#define p_reg_lnk2ofdm_data_7_0 0xF6A0 +#define reg_lnk2ofdm_data_7_0_pos 0 +#define reg_lnk2ofdm_data_7_0_len 8 +#define reg_lnk2ofdm_data_7_0_lsb 0 +#define p_reg_lnk2ofdm_data_15_8 0xF6A1 +#define reg_lnk2ofdm_data_15_8_pos 0 +#define reg_lnk2ofdm_data_15_8_len 8 +#define reg_lnk2ofdm_data_15_8_lsb 8 +#define p_reg_lnk2ofdm_data_23_16 0xF6A2 +#define reg_lnk2ofdm_data_23_16_pos 0 +#define reg_lnk2ofdm_data_23_16_len 8 +#define reg_lnk2ofdm_data_23_16_lsb 16 +#define p_reg_lnk2ofdm_data_31_24 0xF6A3 +#define reg_lnk2ofdm_data_31_24_pos 0 +#define reg_lnk2ofdm_data_31_24_len 8 +#define reg_lnk2ofdm_data_31_24_lsb 24 +#define p_reg_lnk2ofdm_data_39_32 0xF6A4 +#define reg_lnk2ofdm_data_39_32_pos 0 +#define reg_lnk2ofdm_data_39_32_len 8 +#define reg_lnk2ofdm_data_39_32_lsb 32 +#define p_reg_lnk2ofdm_data_47_40 0xF6A5 +#define reg_lnk2ofdm_data_47_40_pos 0 +#define reg_lnk2ofdm_data_47_40_len 8 +#define reg_lnk2ofdm_data_47_40_lsb 40 +#define p_reg_lnk2ofdm_data_55_48 0xF6A6 +#define reg_lnk2ofdm_data_55_48_pos 0 +#define reg_lnk2ofdm_data_55_48_len 8 +#define reg_lnk2ofdm_data_55_48_lsb 48 +#define p_reg_lnk2ofdm_data_63_56 0xF6A7 +#define reg_lnk2ofdm_data_63_56_pos 0 +#define reg_lnk2ofdm_data_63_56_len 8 +#define reg_lnk2ofdm_data_63_56_lsb 56 +#define p_reg_ofdmtolnk_data_7_0 0xF6A8 +#define reg_ofdmtolnk_data_7_0_pos 0 +#define reg_ofdmtolnk_data_7_0_len 8 +#define reg_ofdmtolnk_data_7_0_lsb 0 +#define p_reg_ofdmtolnk_data_15_8 0xF6A9 +#define reg_ofdmtolnk_data_15_8_pos 0 +#define reg_ofdmtolnk_data_15_8_len 8 +#define reg_ofdmtolnk_data_15_8_lsb 8 +#define p_reg_ofdmtolnk_data_23_16 0xF6AA +#define reg_ofdmtolnk_data_23_16_pos 0 +#define reg_ofdmtolnk_data_23_16_len 8 +#define reg_ofdmtolnk_data_23_16_lsb 16 +#define p_reg_ofdmtolnk_data_31_24 0xF6AB +#define reg_ofdmtolnk_data_31_24_pos 0 +#define reg_ofdmtolnk_data_31_24_len 8 +#define reg_ofdmtolnk_data_31_24_lsb 24 +#define p_reg_ofdmtolnk_data_39_32 0xF6AC +#define reg_ofdmtolnk_data_39_32_pos 0 +#define reg_ofdmtolnk_data_39_32_len 8 +#define reg_ofdmtolnk_data_39_32_lsb 32 +#define p_reg_ofdmtolnk_data_47_40 0xF6AD +#define reg_ofdmtolnk_data_47_40_pos 0 +#define reg_ofdmtolnk_data_47_40_len 8 +#define reg_ofdmtolnk_data_47_40_lsb 40 +#define p_reg_ofdmtolnk_data_55_48 0xF6AE +#define reg_ofdmtolnk_data_55_48_pos 0 +#define reg_ofdmtolnk_data_55_48_len 8 +#define reg_ofdmtolnk_data_55_48_lsb 48 +#define p_reg_ofdmtolnk_data_63_56 0xF6AF +#define reg_ofdmtolnk_data_63_56_pos 0 +#define reg_ofdmtolnk_data_63_56_len 8 +#define reg_ofdmtolnk_data_63_56_lsb 56 +#define p_reg_mon51_flag 0xF6B0 +#define reg_mon51_flag_pos 0 +#define reg_mon51_flag_len 1 +#define reg_mon51_flag_lsb 0 +#define p_reg_force_mon51 0xF6B1 +#define reg_force_mon51_pos 0 +#define reg_force_mon51_len 1 +#define reg_force_mon51_lsb 0 +#define p_reg_which_cpu 0xF6B2 +#define reg_which_cpu_pos 0 +#define reg_which_cpu_len 1 +#define reg_which_cpu_lsb 0 +#define p_reg_program_ofdm_code_ready 0xF6B3 +#define reg_program_ofdm_code_ready_pos 0 +#define reg_program_ofdm_code_ready_len 1 +#define reg_program_ofdm_code_ready_lsb 0 +#define p_reg_link_wr_ofdm_en 0xF6B3 +#define reg_link_wr_ofdm_en_pos 1 +#define reg_link_wr_ofdm_en_len 1 +#define reg_link_wr_ofdm_en_lsb 0 +#define p_reg_i2c_mode 0xF6B4 +#define reg_i2c_mode_pos 0 +#define reg_i2c_mode_len 1 +#define reg_i2c_mode_lsb 0 +#define p_reg_sw_reset_sdio 0xF6B4 +#define reg_sw_reset_sdio_pos 1 +#define reg_sw_reset_sdio_len 1 +#define reg_sw_reset_sdio_lsb 0 +#define p_reg_debug_mpefec_sel 0xF6B4 +#define reg_debug_mpefec_sel_pos 2 +#define reg_debug_mpefec_sel_len 1 +#define reg_debug_mpefec_sel_lsb 0 +#define p_reg_lnk_dynamic_clk 0xF6B4 +#define reg_lnk_dynamic_clk_pos 3 +#define reg_lnk_dynamic_clk_len 1 +#define reg_lnk_dynamic_clk_lsb 0 +#define p_reg_lnk_free_clk 0xF6B4 +#define reg_lnk_free_clk_pos 4 +#define reg_lnk_free_clk_len 1 +#define reg_lnk_free_clk_lsb 0 +#define p_reg_i2c_sample_rate_up_en 0xF6B4 +#define reg_i2c_sample_rate_up_en_pos 5 +#define reg_i2c_sample_rate_up_en_len 1 +#define reg_i2c_sample_rate_up_en_lsb 0 +#define p_reg_i2c_start_patch 0xF6B4 +#define reg_i2c_start_patch_pos 6 +#define reg_i2c_start_patch_len 1 +#define reg_i2c_start_patch_lsb 0 +#define p_reg_link_i2cs_msb 0xF6B5 +#define reg_link_i2cs_msb_pos 1 +#define reg_link_i2cs_msb_len 1 +#define reg_link_i2cs_msb_lsb 0 +#define p_reg_link_ofsm_dbg_en 0xF6B5 +#define reg_link_ofsm_dbg_en_pos 4 +#define reg_link_ofsm_dbg_en_len 1 +#define reg_link_ofsm_dbg_en_lsb 0 +#define p_reg_link_i2c_dbg_sel 0xF6B5 +#define reg_link_i2c_dbg_sel_pos 5 +#define reg_link_i2c_dbg_sel_len 1 +#define reg_link_i2c_dbg_sel_lsb 0 +#define p_reg_fast_slow_train 0xF6DD +#define p_reg_lnk2ofdm_int 0xF6DE +#define reg_lnk2ofdm_int_pos 0 +#define reg_lnk2ofdm_int_len 1 +#define reg_lnk2ofdm_int_lsb 0 +#define p_reg_ofdm2lnk_int 0xF6DF +#define reg_ofdm2lnk_int_pos 0 +#define reg_ofdm2lnk_int_len 1 +#define reg_ofdm2lnk_int_lsb 0 +#define p_reg_load_ofdm_reg 0xF6E4 +#define p_link_ofsm_cmd_reg 0xF6EA +#define link_ofsm_cmd_reg_pos 0 +#define link_ofsm_cmd_reg_len 8 +#define link_ofsm_cmd_reg_lsb 0 +#define p_link_ofsm_addr_reg_h 0xF6EB +#define link_ofsm_addr_reg_h_pos 0 +#define link_ofsm_addr_reg_h_len 8 +#define link_ofsm_addr_reg_h_lsb 0 +#define p_link_ofsm_addr_reg_l 0xF6EC +#define link_ofsm_addr_reg_l_pos 0 +#define link_ofsm_addr_reg_l_len 8 +#define link_ofsm_addr_reg_l_lsb 0 +#define p_link_ofsm_data_reg_0 0xF6ED +#define link_ofsm_data_reg_0_pos 0 +#define link_ofsm_data_reg_0_len 8 +#define link_ofsm_data_reg_0_lsb 0 +#define p_link_ofsm_data_reg_1 0xF6EE +#define link_ofsm_data_reg_1_pos 0 +#define link_ofsm_data_reg_1_len 8 +#define link_ofsm_data_reg_1_lsb 0 +#define p_link_ofsm_data_reg_2 0xF6EF +#define link_ofsm_data_reg_2_pos 0 +#define link_ofsm_data_reg_2_len 8 +#define link_ofsm_data_reg_2_lsb 0 +#define p_link_ofsm_data_reg_3 0xF6F0 +#define link_ofsm_data_reg_3_pos 0 +#define link_ofsm_data_reg_3_len 8 +#define link_ofsm_data_reg_3_lsb 0 +#define p_link_ofsm_data_reg_4 0xF6F1 +#define link_ofsm_data_reg_4_pos 0 +#define link_ofsm_data_reg_4_len 8 +#define link_ofsm_data_reg_4_lsb 0 +#define p_link_ofsm_data_reg_5 0xF6F2 +#define link_ofsm_data_reg_5_pos 0 +#define link_ofsm_data_reg_5_len 8 +#define link_ofsm_data_reg_5_lsb 0 +#define p_link_ofsm_data_reg_6 0xF6F3 +#define link_ofsm_data_reg_6_pos 0 +#define link_ofsm_data_reg_6_len 8 +#define link_ofsm_data_reg_6_lsb 0 +#define p_link_ofsm_data_reg_7 0xF6F4 +#define link_ofsm_data_reg_7_pos 0 +#define link_ofsm_data_reg_7_len 8 +#define link_ofsm_data_reg_7_lsb 0 +#define p_link_ofsm_data_reg_8 0xF6F5 +#define link_ofsm_data_reg_8_pos 0 +#define link_ofsm_data_reg_8_len 8 +#define link_ofsm_data_reg_8_lsb 0 +#define p_link_ofsm_data_reg_9 0xF6F6 +#define link_ofsm_data_reg_9_pos 0 +#define link_ofsm_data_reg_9_len 8 +#define link_ofsm_data_reg_9_lsb 0 +#define p_link_ofsm_data_reg_10 0xF6F7 +#define link_ofsm_data_reg_10_pos 0 +#define link_ofsm_data_reg_10_len 8 +#define link_ofsm_data_reg_10_lsb 0 +#define p_link_ofsm_data_reg_11 0xF6F8 +#define link_ofsm_data_reg_11_pos 0 +#define link_ofsm_data_reg_11_len 8 +#define link_ofsm_data_reg_11_lsb 0 +#define p_link_ofsm_data_reg_12 0xF6F9 +#define link_ofsm_data_reg_12_pos 0 +#define link_ofsm_data_reg_12_len 8 +#define link_ofsm_data_reg_12_lsb 0 +#define p_link_ofsm_data_reg_13 0xF6FA +#define link_ofsm_data_reg_13_pos 0 +#define link_ofsm_data_reg_13_len 8 +#define link_ofsm_data_reg_13_lsb 0 +#define p_link_ofsm_data_reg_14 0xF6FB +#define link_ofsm_data_reg_14_pos 0 +#define link_ofsm_data_reg_14_len 8 +#define link_ofsm_data_reg_14_lsb 0 +#define p_link_ofsm_data_reg_15 0xF6FC +#define link_ofsm_data_reg_15_pos 0 +#define link_ofsm_data_reg_15_len 8 +#define link_ofsm_data_reg_15_lsb 0 +#define p_reg_debug_mux 0xF6FE +#define reg_debug_mux_pos 3 +#define reg_debug_mux_len 1 +#define reg_debug_mux_lsb 0 +#define p_reg_top_gpioon0 0xF6FF +#define reg_top_gpioon0_pos 0 +#define reg_top_gpioon0_len 1 +#define reg_top_gpioon0_lsb 0 +#define p_reg_p_dmb_phy_is_dvb 0xDC31 +#define reg_p_dmb_phy_is_dvb_pos 0 +#define reg_p_dmb_phy_is_dvb_len 1 +#define reg_p_dmb_phy_is_dvb_lsb 0 +#define p_reg_p_dmb_xt_reset 0xDC32 +#define reg_p_dmb_xt_reset_pos 0 +#define reg_p_dmb_xt_reset_len 1 +#def